* [PATCH v2] drm/ttm: add pgprot handling for RISC-V
@ 2025-10-20 5:35 Icenowy Zheng
2025-10-27 7:56 ` Christian König
0 siblings, 1 reply; 5+ messages in thread
From: Icenowy Zheng @ 2025-10-20 5:35 UTC (permalink / raw)
To: Christian Koenig, Huang Rui, Matthew Auld, Matthew Brost,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: dri-devel, linux-kernel, linux-riscv, Han Gao, Vivian Wang,
Inochi Amaoto, Yao Zi, Icenowy Zheng
The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Han Gao <rabenda.cn@gmail.com>
---
Changes in v2:
- Added Han Gao's test tag.
drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
index b3fffe7b5062a..aa137ead5cc59 100644
--- a/drivers/gpu/drm/ttm/ttm_module.c
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
#endif /* CONFIG_UML */
#endif /* __i386__ || __x86_64__ */
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
- defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
+ defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
+ defined(__riscv)
if (caching == ttm_write_combined)
tmp = pgprot_writecombine(tmp);
else
--
2.51.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V
2025-10-20 5:35 [PATCH v2] drm/ttm: add pgprot handling for RISC-V Icenowy Zheng
@ 2025-10-27 7:56 ` Christian König
2025-10-27 16:41 ` Paul Walmsley
2025-10-27 17:10 ` Han Gao
0 siblings, 2 replies; 5+ messages in thread
From: Christian König @ 2025-10-27 7:56 UTC (permalink / raw)
To: Icenowy Zheng, Huang Rui, Matthew Auld, Matthew Brost,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: dri-devel, linux-kernel, linux-riscv, Han Gao, Vivian Wang,
Inochi Amaoto, Yao Zi
On 10/20/25 07:35, Icenowy Zheng wrote:
> The RISC-V Svpbmt privileged extension provides support for overriding
> page memory coherency attributes, and, along with vendor extensions like
> Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
>
> Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> access attributes.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Han Gao <rabenda.cn@gmail.com>
> ---
> Changes in v2:
> - Added Han Gao's test tag.
>
> drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> index b3fffe7b5062a..aa137ead5cc59 100644
> --- a/drivers/gpu/drm/ttm/ttm_module.c
> +++ b/drivers/gpu/drm/ttm/ttm_module.c
> @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
> #endif /* CONFIG_UML */
> #endif /* __i386__ || __x86_64__ */
> #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> + defined(__riscv)
Looks reasonable, but does that work on all RISC-V variants?
And while at it maybe please fix the indentation, using a tab here is probably not very adequate. In other words make the defined() match the one on the first line.
Regards,
Christian.
> if (caching == ttm_write_combined)
> tmp = pgprot_writecombine(tmp);
> else
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V
2025-10-27 7:56 ` Christian König
@ 2025-10-27 16:41 ` Paul Walmsley
2025-10-28 8:20 ` Christian König
2025-10-27 17:10 ` Han Gao
1 sibling, 1 reply; 5+ messages in thread
From: Paul Walmsley @ 2025-10-27 16:41 UTC (permalink / raw)
To: Christian König
Cc: Matthew Brost, Simona Vetter, Yao Zi, Albert Ou, Alexandre Ghiti,
Vivian Wang, dri-devel, Han Gao, Maarten Lankhorst, linux-kernel,
Maxime Ripard, Huang Rui, Palmer Dabbelt, Matthew Auld,
Thomas Zimmermann, Paul Walmsley, linux-riscv, David Airlie,
Inochi Amaoto
[-- Attachment #1: Type: text/plain, Size: 1407 bytes --]
On Mon, 27 Oct 2025, Christian König wrote:
> On 10/20/25 07:35, Icenowy Zheng wrote:
> > The RISC-V Svpbmt privileged extension provides support for overriding
> > page memory coherency attributes, and, along with vendor extensions like
> > Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
> >
> > Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> > and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> > access attributes.
[ ... ]
> > diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> > index b3fffe7b5062a..aa137ead5cc59 100644
> > --- a/drivers/gpu/drm/ttm/ttm_module.c
> > +++ b/drivers/gpu/drm/ttm/ttm_module.c
> > @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
> > #endif /* CONFIG_UML */
> > #endif /* __i386__ || __x86_64__ */
> > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> > - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> > + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> > + defined(__riscv)
>
> Looks reasonable, but does that work on all RISC-V variants?
From an RISC-V architectural perspective, yes.
Of course there might be a hardware bug in some given manufacturer's
implementation, but then again, that could happen on the other
architectures as well.
- Paul
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V
2025-10-27 7:56 ` Christian König
2025-10-27 16:41 ` Paul Walmsley
@ 2025-10-27 17:10 ` Han Gao
1 sibling, 0 replies; 5+ messages in thread
From: Han Gao @ 2025-10-27 17:10 UTC (permalink / raw)
To: Christian König
Cc: Matthew Brost, Simona Vetter, Yao Zi, Albert Ou, Alexandre Ghiti,
Vivian Wang, dri-devel, Maarten Lankhorst, linux-kernel,
Maxime Ripard, Huang Rui, Palmer Dabbelt, Matthew Auld,
Thomas Zimmermann, Paul Walmsley, linux-riscv, David Airlie,
Inochi Amaoto
Tested on sophgo sg2042/sophgo sg2044/ultrarisc dp1000.
On Mon, Oct 27, 2025 at 3:57 PM Christian König
<christian.koenig@amd.com> wrote:
>
>
>
> On 10/20/25 07:35, Icenowy Zheng wrote:
> > The RISC-V Svpbmt privileged extension provides support for overriding
> > page memory coherency attributes, and, along with vendor extensions like
> > Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
> >
> > Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> > and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> > access attributes.
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > Tested-by: Han Gao <rabenda.cn@gmail.com>
> > ---
> > Changes in v2:
> > - Added Han Gao's test tag.
> >
> > drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> > index b3fffe7b5062a..aa137ead5cc59 100644
> > --- a/drivers/gpu/drm/ttm/ttm_module.c
> > +++ b/drivers/gpu/drm/ttm/ttm_module.c
> > @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
> > #endif /* CONFIG_UML */
> > #endif /* __i386__ || __x86_64__ */
> > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> > - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> > + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> > + defined(__riscv)
>
> Looks reasonable, but does that work on all RISC-V variants?
>
> And while at it maybe please fix the indentation, using a tab here is probably not very adequate. In other words make the defined() match the one on the first line.
>
> Regards,
> Christian.
>
> > if (caching == ttm_write_combined)
> > tmp = pgprot_writecombine(tmp);
> > else
>
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V
2025-10-27 16:41 ` Paul Walmsley
@ 2025-10-28 8:20 ` Christian König
0 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2025-10-28 8:20 UTC (permalink / raw)
To: Paul Walmsley
Cc: Matthew Brost, Simona Vetter, Yao Zi, Albert Ou, Alexandre Ghiti,
Vivian Wang, dri-devel, Han Gao, Maarten Lankhorst, linux-kernel,
Maxime Ripard, Huang Rui, Palmer Dabbelt, Matthew Auld,
Thomas Zimmermann, Paul Walmsley, linux-riscv, David Airlie,
Inochi Amaoto
On 10/27/25 17:41, Paul Walmsley wrote:
> On Mon, 27 Oct 2025, Christian König wrote:
>
>> On 10/20/25 07:35, Icenowy Zheng wrote:
>>> The RISC-V Svpbmt privileged extension provides support for overriding
>>> page memory coherency attributes, and, along with vendor extensions like
>>> Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
>>>
>>> Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
>>> and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
>>> access attributes.
>
> [ ... ]
>
>>> diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
>>> index b3fffe7b5062a..aa137ead5cc59 100644
>>> --- a/drivers/gpu/drm/ttm/ttm_module.c
>>> +++ b/drivers/gpu/drm/ttm/ttm_module.c
>>> @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
>>> #endif /* CONFIG_UML */
>>> #endif /* __i386__ || __x86_64__ */
>>> #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
>>> - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
>>> + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
>>> + defined(__riscv)
>>
>> Looks reasonable, but does that work on all RISC-V variants?
>
> From an RISC-V architectural perspective, yes.
>
> Of course there might be a hardware bug in some given manufacturer's
> implementation, but then again, that could happen on the other
> architectures as well.
I've added my acked-by and pushed it to drm-misc-next.
Regards,
Christian.
>
>
> - Paul
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2025-10-20 5:35 [PATCH v2] drm/ttm: add pgprot handling for RISC-V Icenowy Zheng
2025-10-27 7:56 ` Christian König
2025-10-27 16:41 ` Paul Walmsley
2025-10-28 8:20 ` Christian König
2025-10-27 17:10 ` Han Gao
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