From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
To: Guodong Xu <guodong@riscstar.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
Kevin Meng Zhang <zhangmeng.kevin@linux.spacemit.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, spacemit@lists.linux.dev,
linux-serial@vger.kernel.org, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Yixun Lan <dlan@gentoo.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Lubomir Rintel <lkundrak@v3.sk>, Yangyu Chen <cyy@cyyself.name>
Subject: Re: [PATCH 7/8] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
Date: Tue, 16 Dec 2025 15:24:05 +0100 [thread overview]
Message-ID: <60948ca2-ed3d-485b-9b11-15df7ef8791d@canonical.com> (raw)
In-Reply-To: <20251216-k3-basic-dt-v1-7-a0d256c9dc92@riscstar.com>
On 12/16/25 14:32, Guodong Xu wrote:
> SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> Add nodes of uarts, timer and interrupt-controllers.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> arch/riscv/boot/dts/spacemit/k3.dtsi | 529 +++++++++++++++++++++++++++++++++++
> 1 file changed, 529 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..cb27b790716fdd6dc2bc89c28dd2588a596a5af9
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -0,0 +1,529 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
> + * Copyright (c) 2025 Guodong Xu <guodong@riscstar.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SpacemiT K3";
> + compatible = "spacemit,k3";
> +
> + aliases {
> + serial0 = &uart0;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + serial6 = &uart6;
> + serial7 = &uart7;
> + serial8 = &uart8;
> + serial9 = &uart9;
> + serial10 = &uart10;
> + };
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + cpu_0: cpu@0 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
This not the description of an RVA23S64 cpu. It is not even RVA23U64,
e.g. `supm` is missing.
Is the description incomplete or is the CPU not compliant?
Best regards
Heinrich
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_1: cpu@1 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <1>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_2: cpu@2 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <2>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_3: cpu@3 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <3>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache0>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_4: cpu@4 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <4>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_5: cpu@5 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <5>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu5_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_6: cpu@6 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <6>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu6_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + cpu_7: cpu@7 {
> + compatible = "spacemit,x100", "riscv";
> + device_type = "cpu";
> + reg = <7>;
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h",
> + "smaia", "smstateen", "ssaia", "sscofpmf",
> + "ssnpm", "sstc", "svade", "svinval", "svnapot",
> + "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs",
> + "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
> + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
> + "zicntr", "zicond", "zicsr", "zifencei",
> + "zihintntl", "zihintpause", "zihpm", "zimop",
> + "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma",
> + "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn",
> + "zvknc", "zvkned", "zvkng", "zvknha",
> + "zvknhb", "zvks", "zvksc", "zvksed",
> + "zvksg", "zvksh", "zvkt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <256>;
> + next-level-cache = <&l2_cache1>;
> + mmu-type = "riscv,sv39";
> +
> + cpu7_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> + l2_cache0: cache-controller-0 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <4194304>;
> + cache-sets = <4096>;
> + cache-unified;
> + };
> +
> + l2_cache1: cache-controller-1 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <4194304>;
> + cache-sets = <4096>;
> + cache-unified;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu_0>;
> + };
> + core1 {
> + cpu = <&cpu_1>;
> + };
> + core2 {
> + cpu = <&cpu_2>;
> + };
> + core3 {
> + cpu = <&cpu_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu_4>;
> + };
> + core1 {
> + cpu = <&cpu_5>;
> + };
> + core2 {
> + cpu = <&cpu_6>;
> + };
> + core3 {
> + cpu = <&cpu_7>;
> + };
> + };
> + };
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&saplic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + uart0: serial@d4017000 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017000 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart2: serial@d4017100 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017100 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart3: serial@d4017200 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017200 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart4: serial@d4017300 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017300 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart5: serial@d4017400 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017400 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart6: serial@d4017500 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017500 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart7: serial@d4017600 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017600 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart8: serial@d4017700 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017700 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart9: serial@d4017800 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017800 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart10: serial@d401f000 {
> + compatible = "spacemit,k3-uart", "intel,xscale-uart";
> + reg = <0x0 0xd401f000 0x0 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <14700000>;
> + interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + simsic: interrupt-controller@e0400000 {
> + compatible = "spacemit,k3-imsics","riscv,imsics";
> + reg = <0x0 0xe0400000 0x0 0x00200000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + msi-controller;
> + #msi-cells = <0>;
> + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
> + <&cpu2_intc 9>, <&cpu3_intc 9>,
> + <&cpu4_intc 9>, <&cpu5_intc 9>,
> + <&cpu6_intc 9>, <&cpu7_intc 9>;
> + riscv,num-ids = <511>;
> + riscv,num-guest-ids = <511>;
> + riscv,hart-index-bits = <4>;
> + riscv,guest-index-bits = <6>;
> + };
> +
> + saplic: interrupt-controller@e0804000 {
> + compatible = "spacemit,k3-aplic", "riscv,aplic";
> + reg = <0x0 0xe0804000 0x0 0x4000>;
> + msi-parent = <&simsic>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + riscv,num-sources = <512>;
> + };
> +
> + clint: timer@e081c000 {
> + compatible = "spacemit,k3-clint", "sifive,clint0";
> + reg = <0x0 0xe081c000 0x0 0x0004000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>,
> + <&cpu5_intc 3>, <&cpu5_intc 7>,
> + <&cpu6_intc 3>, <&cpu6_intc 7>,
> + <&cpu7_intc 3>, <&cpu7_intc 7>;
> + };
> + };
> +};
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-12-16 14:24 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-16 13:32 [PATCH 0/8] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Guodong Xu
2025-12-16 13:32 ` [PATCH 1/8] dt-bindings: riscv: add SpacemiT X100 CPU compatible Guodong Xu
2025-12-16 14:08 ` Heinrich Schuchardt
2025-12-16 15:07 ` Yixun Lan
2025-12-17 2:06 ` Guodong Xu
2025-12-16 15:16 ` Yixun Lan
2025-12-17 3:38 ` Guodong Xu
2025-12-16 15:33 ` Krzysztof Kozlowski
2025-12-17 1:54 ` Guodong Xu
2025-12-16 13:32 ` [PATCH 2/8] dt-bindings: timer: add SpacemiT K3 CLINT Guodong Xu
2025-12-16 16:40 ` Conor Dooley
2025-12-16 13:32 ` [PATCH 3/8] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC Guodong Xu
2025-12-16 16:40 ` Conor Dooley
2025-12-16 13:32 ` [PATCH 4/8] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Guodong Xu
2025-12-16 15:33 ` Krzysztof Kozlowski
2025-12-17 3:48 ` Guodong Xu
2025-12-16 13:32 ` [PATCH 5/8] dt-bindings: serial: 8250: add SpacemiT K3 UART compatible Guodong Xu
2025-12-16 16:41 ` Conor Dooley
2025-12-16 13:32 ` [PATCH 6/8] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Guodong Xu
2025-12-16 15:05 ` Yixun Lan
2025-12-16 16:33 ` Conor Dooley
2025-12-17 1:23 ` Guodong Xu
2025-12-16 13:32 ` [PATCH 7/8] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC Guodong Xu
2025-12-16 14:24 ` Heinrich Schuchardt [this message]
2025-12-17 7:11 ` Guodong Xu
2025-12-17 8:07 ` Heinrich Schuchardt
2025-12-18 0:56 ` Conor Dooley
2025-12-19 2:03 ` Guodong Xu
2025-12-19 8:08 ` Heinrich Schuchardt
2025-12-20 2:48 ` Yao Zi
2025-12-22 9:27 ` Guodong Xu
2025-12-20 23:23 ` Conor Dooley
2025-12-21 0:10 ` Heinrich Schuchardt
2025-12-22 10:32 ` Guodong Xu
2025-12-22 20:36 ` Conor Dooley
2025-12-26 6:53 ` Guodong Xu
2026-01-01 0:24 ` Conor Dooley
2026-01-08 19:23 ` Samuel Holland
2025-12-16 15:35 ` Krzysztof Kozlowski
2025-12-17 5:39 ` Guodong Xu
2025-12-16 13:32 ` [PATCH 8/8] riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree Guodong Xu
2025-12-16 14:33 ` Heinrich Schuchardt
2025-12-17 7:13 ` Guodong Xu
2025-12-17 9:04 ` Bo Gan
2025-12-18 22:43 ` Guodong Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=60948ca2-ed3d-485b-9b11-15df7ef8791d@canonical.com \
--to=heinrich.schuchardt@canonical.com \
--cc=alex@ghiti.fr \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=conor@kernel.org \
--cc=cyy@cyyself.name \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=dlan@gentoo.org \
--cc=gregkh@linuxfoundation.org \
--cc=guodong@riscstar.com \
--cc=jirislaby@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-serial@vger.kernel.org \
--cc=lkundrak@v3.sk \
--cc=palmer@dabbelt.com \
--cc=palmer@sifive.com \
--cc=paul.walmsley@sifive.com \
--cc=pjw@kernel.org \
--cc=robh@kernel.org \
--cc=samuel.holland@sifive.com \
--cc=spacemit@lists.linux.dev \
--cc=tglx@linutronix.de \
--cc=zhangmeng.kevin@linux.spacemit.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox