* [PATCH cmpxchg 14/14] riscv: Emulate one-byte cmpxchg
[not found] <7b3646e0-667c-48e2-8f09-e493c43c30cb@paulmck-laptop>
@ 2024-04-08 17:49 ` Paul E. McKenney
2024-04-09 17:35 ` Andrea Parri
0 siblings, 1 reply; 3+ messages in thread
From: Paul E. McKenney @ 2024-04-08 17:49 UTC (permalink / raw)
To: linux-arch, linux-kernel
Cc: elver, akpm, tglx, peterz, dianders, pmladek, torvalds,
Arnd Bergmann, Paul E. McKenney, Yujie Liu, Andi Shyti,
Andrzej Hajda, linux-riscv, Palmer Dabbelt
Use the new cmpxchg_emu_u8() to emulate one-byte cmpxchg() on riscv.
[ paulmck: Apply kernel test robot feedback. ]
[ paulmck: Drop two-byte support per Arnd Bergmann feedback. ]
Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
Tested-by: Yujie Liu <yujie.liu@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: <linux-riscv@lists.infradead.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/cmpxchg.h | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index be09c8836d56b..3bab9c5c0f465 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
select ARCH_HAS_UBSAN
select ARCH_HAS_VDSO_DATA
select ARCH_KEEP_MEMBLOCK if ACPI
+ select ARCH_NEED_CMPXCHG_1_EMU
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
select ARCH_STACKWALK
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 2fee65cc84432..abcd5543b861b 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -9,6 +9,7 @@
#include <linux/bug.h>
#include <asm/fence.h>
+#include <linux/cmpxchg-emu.h>
#define __xchg_relaxed(ptr, new, size) \
({ \
@@ -170,6 +171,9 @@
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
+ case 1: \
+ __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, (uintptr_t)__old, (uintptr_t)__new); \
+ break; \
case 4: \
__asm__ __volatile__ ( \
"0: lr.w %0, %2\n" \
@@ -214,6 +218,9 @@
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
+ case 1: \
+ __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
+ break; \
case 4: \
__asm__ __volatile__ ( \
"0: lr.w %0, %2\n" \
@@ -260,6 +267,9 @@
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
+ case 1: \
+ __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
+ break; \
case 4: \
__asm__ __volatile__ ( \
RISCV_RELEASE_BARRIER \
@@ -306,6 +316,9 @@
__typeof__(*(ptr)) __ret; \
register unsigned int __rc; \
switch (size) { \
+ case 1: \
+ __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
+ break; \
case 4: \
__asm__ __volatile__ ( \
"0: lr.w %0, %2\n" \
--
2.40.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH cmpxchg 14/14] riscv: Emulate one-byte cmpxchg
2024-04-08 17:49 ` [PATCH cmpxchg 14/14] riscv: Emulate one-byte cmpxchg Paul E. McKenney
@ 2024-04-09 17:35 ` Andrea Parri
2024-04-09 18:08 ` Paul E. McKenney
0 siblings, 1 reply; 3+ messages in thread
From: Andrea Parri @ 2024-04-09 17:35 UTC (permalink / raw)
To: Paul E. McKenney
Cc: linux-arch, linux-kernel, elver, akpm, tglx, peterz, dianders,
pmladek, torvalds, Arnd Bergmann, Yujie Liu, Andi Shyti,
Andrzej Hajda, linux-riscv, Palmer Dabbelt
Hi Paul,
> @@ -170,6 +171,9 @@
> __typeof__(*(ptr)) __ret; \
> register unsigned int __rc; \
> switch (size) { \
> + case 1: \
> + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, (uintptr_t)__old, (uintptr_t)__new); \
> + break; \
> case 4: \
> __asm__ __volatile__ ( \
> "0: lr.w %0, %2\n" \
> @@ -214,6 +218,9 @@
> __typeof__(*(ptr)) __ret; \
> register unsigned int __rc; \
> switch (size) { \
> + case 1: \
> + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
> + break; \
> case 4: \
> __asm__ __volatile__ ( \
> "0: lr.w %0, %2\n" \
> @@ -260,6 +267,9 @@
> __typeof__(*(ptr)) __ret; \
> register unsigned int __rc; \
> switch (size) { \
> + case 1: \
> + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
> + break; \
> case 4: \
> __asm__ __volatile__ ( \
> RISCV_RELEASE_BARRIER \
> @@ -306,6 +316,9 @@
> __typeof__(*(ptr)) __ret; \
> register unsigned int __rc; \
> switch (size) { \
> + case 1: \
> + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
> + break; \
> case 4: \
> __asm__ __volatile__ ( \
> "0: lr.w %0, %2\n" \
Seems the last three are missing uintptr_t casts?
Andrea
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH cmpxchg 14/14] riscv: Emulate one-byte cmpxchg
2024-04-09 17:35 ` Andrea Parri
@ 2024-04-09 18:08 ` Paul E. McKenney
0 siblings, 0 replies; 3+ messages in thread
From: Paul E. McKenney @ 2024-04-09 18:08 UTC (permalink / raw)
To: Andrea Parri
Cc: linux-arch, linux-kernel, elver, akpm, tglx, peterz, dianders,
pmladek, torvalds, Arnd Bergmann, Yujie Liu, Andi Shyti,
Andrzej Hajda, linux-riscv, Palmer Dabbelt
On Tue, Apr 09, 2024 at 07:35:39PM +0200, Andrea Parri wrote:
> Hi Paul,
>
> > @@ -170,6 +171,9 @@
> > __typeof__(*(ptr)) __ret; \
> > register unsigned int __rc; \
> > switch (size) { \
> > + case 1: \
> > + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, (uintptr_t)__old, (uintptr_t)__new); \
> > + break; \
> > case 4: \
> > __asm__ __volatile__ ( \
> > "0: lr.w %0, %2\n" \
> > @@ -214,6 +218,9 @@
> > __typeof__(*(ptr)) __ret; \
> > register unsigned int __rc; \
> > switch (size) { \
> > + case 1: \
> > + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
> > + break; \
> > case 4: \
> > __asm__ __volatile__ ( \
> > "0: lr.w %0, %2\n" \
> > @@ -260,6 +267,9 @@
> > __typeof__(*(ptr)) __ret; \
> > register unsigned int __rc; \
> > switch (size) { \
> > + case 1: \
> > + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
> > + break; \
> > case 4: \
> > __asm__ __volatile__ ( \
> > RISCV_RELEASE_BARRIER \
> > @@ -306,6 +316,9 @@
> > __typeof__(*(ptr)) __ret; \
> > register unsigned int __rc; \
> > switch (size) { \
> > + case 1: \
> > + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \
> > + break; \
> > case 4: \
> > __asm__ __volatile__ ( \
> > "0: lr.w %0, %2\n" \
>
> Seems the last three are missing uintptr_t casts?
Indeed they are, and good eyes!
However, Liu, Yujie beat you to it, and this commit contains the fix:
4d5c72a34948 ("riscv: Emulate one-byte cmpxchg")
Thanx, Paul
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2024-04-08 17:49 ` [PATCH cmpxchg 14/14] riscv: Emulate one-byte cmpxchg Paul E. McKenney
2024-04-09 17:35 ` Andrea Parri
2024-04-09 18:08 ` Paul E. McKenney
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