* [PATCH for-next] riscv: Fix default misaligned access trap
@ 2024-11-07 22:38 Charlie Jenkins
2024-11-08 22:09 ` Jesse T
0 siblings, 1 reply; 4+ messages in thread
From: Charlie Jenkins @ 2024-11-07 22:38 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Jesse Taube
Cc: Palmer Dabbelt, linux-riscv, linux-kernel, Charlie Jenkins
Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
supported") removed the default handlers for handle_misaligned_load()
and handle_misaligned_store(). When the kernel is compiled without
RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing
compilation errors.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
---
arch/riscv/include/asm/entry-common.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
index 7b32d2b08bb6..c2808561df81 100644
--- a/arch/riscv/include/asm/entry-common.h
+++ b/arch/riscv/include/asm/entry-common.h
@@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
void handle_page_fault(struct pt_regs *regs);
void handle_break(struct pt_regs *regs);
+#ifdef CONFIG_RISCV_SCALAR_MISALIGNED
int handle_misaligned_load(struct pt_regs *regs);
int handle_misaligned_store(struct pt_regs *regs);
+#else
+static inline int handle_misaligned_load(struct pt_regs *regs)
+{
+ return -1;
+}
+
+static inline int handle_misaligned_store(struct pt_regs *regs)
+{
+ return -1;
+}
+#endif
#endif /* _ASM_RISCV_ENTRY_COMMON_H */
---
base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2
change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e
--
- Charlie
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH for-next] riscv: Fix default misaligned access trap
2024-11-07 22:38 [PATCH for-next] riscv: Fix default misaligned access trap Charlie Jenkins
@ 2024-11-08 22:09 ` Jesse T
2024-11-08 22:12 ` Jesse T
0 siblings, 1 reply; 4+ messages in thread
From: Jesse T @ 2024-11-08 22:09 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Palmer Dabbelt,
linux-riscv, linux-kernel
On Thu, Nov 7, 2024 at 5:38 PM Charlie Jenkins <charlie@rivosinc.com> wrote:
>
> Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
> supported") removed the default handlers for handle_misaligned_load()
> and handle_misaligned_store(). When the kernel is compiled without
> RISCV_SCALAR_MISALIGNED
Technically CONFIG_RISCV_MISALIGNED.
I apparently changed `+obj-y += traps_misaligned.o` to
`+obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o`
in V2 and didn't change that check back oops sorry.
> , these handlers are never defined, causing
> compilation errors.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Signed-off-by: Jesse Taube <mr.bossman075@gmail.com>
> Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
> ---
> arch/riscv/include/asm/entry-common.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
> index 7b32d2b08bb6..c2808561df81 100644
> --- a/arch/riscv/include/asm/entry-common.h
> +++ b/arch/riscv/include/asm/entry-common.h
> @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
> void handle_page_fault(struct pt_regs *regs);
> void handle_break(struct pt_regs *regs);
>
> +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED
> int handle_misaligned_load(struct pt_regs *regs);
> int handle_misaligned_store(struct pt_regs *regs);
> +#else
> +static inline int handle_misaligned_load(struct pt_regs *regs)
> +{
> + return -1;
> +}
> +
> +static inline int handle_misaligned_store(struct pt_regs *regs)
> +{
> + return -1;
> +}
> +#endif
>
> #endif /* _ASM_RISCV_ENTRY_COMMON_H */
>
> ---
> base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2
> change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e
> --
> - Charlie
>
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH for-next] riscv: Fix default misaligned access trap
2024-11-08 22:09 ` Jesse T
@ 2024-11-08 22:12 ` Jesse T
2024-11-08 23:16 ` Charlie Jenkins
0 siblings, 1 reply; 4+ messages in thread
From: Jesse T @ 2024-11-08 22:12 UTC (permalink / raw)
To: Charlie Jenkins
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Palmer Dabbelt,
linux-riscv, linux-kernel
On Fri, Nov 8, 2024 at 5:09 PM Jesse T <mr.bossman075@gmail.com> wrote:
>
> On Thu, Nov 7, 2024 at 5:38 PM Charlie Jenkins <charlie@rivosinc.com> wrote:
> >
> > Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
> > supported") removed the default handlers for handle_misaligned_load()
> > and handle_misaligned_store(). When the kernel is compiled without
> > RISCV_SCALAR_MISALIGNED
> Technically CONFIG_RISCV_MISALIGNED.
> I apparently changed `+obj-y += traps_misaligned.o` to
> `+obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o`
> in V2 and didn't change that check back oops sorry.
>
> > , these handlers are never defined, causing
> > compilation errors.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> Signed-off-by: Jesse Taube <mr.bossman075@gmail.com>
>
> > Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
> > ---
> > arch/riscv/include/asm/entry-common.h | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
> > index 7b32d2b08bb6..c2808561df81 100644
> > --- a/arch/riscv/include/asm/entry-common.h
> > +++ b/arch/riscv/include/asm/entry-common.h
> > @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
> > void handle_page_fault(struct pt_regs *regs);
> > void handle_break(struct pt_regs *regs);
> >
> > +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED
Meant to say to change this to CONFIG_RISCV_MISALIGNED.
As they are defined when CONFIG_RISCV_SCALAR_MISALIGNED is false
and CONFIG_RISCV_VECTOE_MISALIGNED is true. they are only not defined when
CONFIG_RISCV_SCALAR_MISALIGNED is false.
> > int handle_misaligned_load(struct pt_regs *regs);
> > int handle_misaligned_store(struct pt_regs *regs);
> > +#else
> > +static inline int handle_misaligned_load(struct pt_regs *regs)
> > +{
> > + return -1;
> > +}
> > +
> > +static inline int handle_misaligned_store(struct pt_regs *regs)
> > +{
> > + return -1;
> > +}
> > +#endif
> >
> > #endif /* _ASM_RISCV_ENTRY_COMMON_H */
> >
> > ---
> > base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2
> > change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e
> > --
> > - Charlie
> >
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH for-next] riscv: Fix default misaligned access trap
2024-11-08 22:12 ` Jesse T
@ 2024-11-08 23:16 ` Charlie Jenkins
0 siblings, 0 replies; 4+ messages in thread
From: Charlie Jenkins @ 2024-11-08 23:16 UTC (permalink / raw)
To: Jesse T
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Palmer Dabbelt,
linux-riscv, linux-kernel
On Fri, Nov 08, 2024 at 05:12:04PM -0500, Jesse T wrote:
> On Fri, Nov 8, 2024 at 5:09 PM Jesse T <mr.bossman075@gmail.com> wrote:
> >
> > On Thu, Nov 7, 2024 at 5:38 PM Charlie Jenkins <charlie@rivosinc.com> wrote:
> > >
> > > Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
> > > supported") removed the default handlers for handle_misaligned_load()
> > > and handle_misaligned_store(). When the kernel is compiled without
> > > RISCV_SCALAR_MISALIGNED
> > Technically CONFIG_RISCV_MISALIGNED.
> > I apparently changed `+obj-y += traps_misaligned.o` to
> > `+obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o`
> > in V2 and didn't change that check back oops sorry.
> >
> > > , these handlers are never defined, causing
> > > compilation errors.
> > >
> > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > Signed-off-by: Jesse Taube <mr.bossman075@gmail.com>
> >
> > > Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
> > > ---
> > > arch/riscv/include/asm/entry-common.h | 12 ++++++++++++
> > > 1 file changed, 12 insertions(+)
> > >
> > > diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
> > > index 7b32d2b08bb6..c2808561df81 100644
> > > --- a/arch/riscv/include/asm/entry-common.h
> > > +++ b/arch/riscv/include/asm/entry-common.h
> > > @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
> > > void handle_page_fault(struct pt_regs *regs);
> > > void handle_break(struct pt_regs *regs);
> > >
> > > +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED
>
> Meant to say to change this to CONFIG_RISCV_MISALIGNED.
> As they are defined when CONFIG_RISCV_SCALAR_MISALIGNED is false
> and CONFIG_RISCV_VECTOE_MISALIGNED is true. they are only not defined when
> CONFIG_RISCV_SCALAR_MISALIGNED is false.
Oh yes, thank you!
- Charlie
>
> > > int handle_misaligned_load(struct pt_regs *regs);
> > > int handle_misaligned_store(struct pt_regs *regs);
> > > +#else
> > > +static inline int handle_misaligned_load(struct pt_regs *regs)
> > > +{
> > > + return -1;
> > > +}
> > > +
> > > +static inline int handle_misaligned_store(struct pt_regs *regs)
> > > +{
> > > + return -1;
> > > +}
> > > +#endif
> > >
> > > #endif /* _ASM_RISCV_ENTRY_COMMON_H */
> > >
> > > ---
> > > base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2
> > > change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e
> > > --
> > > - Charlie
> > >
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2024-11-07 22:38 [PATCH for-next] riscv: Fix default misaligned access trap Charlie Jenkins
2024-11-08 22:09 ` Jesse T
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2024-11-08 23:16 ` Charlie Jenkins
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