From: Drew Fustini <fustini@kernel.org>
To: yunhui cui <cuiyunhui@bytedance.com>
Cc: "Adrien Ricciardi" <aricciardi@baylibre.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Babu Moger" <babu.moger@amd.com>,
"Ben Horgan" <ben.horgan@arm.com>,
"Borislav Petkov" <bp@alien8.de>,
"Chen Pei" <cp0613@linux.alibaba.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
"Dave Martin" <Dave.Martin@arm.com>,
"Fenghua Yu" <fenghua.yu@intel.com>,
"Gong Shuai" <gong.shuai@sanechips.com.cn>,
"Gong Shuai" <gsh517@gmail.com>,
guo.wenjia23@zte.com.cn, "James Morse" <james.morse@arm.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
liu.qingtao2@zte.com.cn,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <pjw@kernel.org>,
"Peter Newman" <peternewman@google.com>,
"Radim Krčmář" <rkrcmar@ventanamicro.com>,
"Reinette Chatre" <reinette.chatre@intel.com>,
"Rob Herring" <robh@kernel.org>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
"Tony Luck" <tony.luck@intel.com>,
"Vasudevan Srinivasan" <vasu@rivosinc.com>,
"Ved Shanbhogue" <ved@rivosinc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
x86@kernel.org, devicetree@vger.kernel.org,
linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org
Subject: Re: [External] [PATCH v2 4/8] riscv_cbqri: Add capacity controller probe and allocation device ops
Date: Sat, 27 Jun 2026 15:10:04 -0700 [thread overview]
Message-ID: <akBKPFPi5213WgYX@x1> (raw)
In-Reply-To: <CAEEQ3w=ZVtHPdLfN0tTzG8AACu+rjhEFWY5pCg+uxvmr7ofqfA@mail.gmail.com>
On Sat, Jun 27, 2026 at 05:31:03PM +0800, yunhui cui wrote:
> Hi Drew,
>
> On Thu, Jun 25, 2026 at 9:41 AM Drew Fustini <fustini@kernel.org> wrote:
> >
> > Add support for the RISC-V CBQRI capacity controller. A platform driver
> > passes a cbqri_controller_info descriptor together with the cache level
> > to riscv_cbqri_register_cc_dt(), which probes the controller and adds it
> > to the controller list.
> >
> > Assisted-by: Claude:claude-opus-4-7
> > Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
[..]
> > diff --git a/drivers/resctrl/cbqri_devices.c b/drivers/resctrl/cbqri_devices.c
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..8ad9df404f65d5d82722cf8b78f02936c489ca6d
> > --- /dev/null
> > +++ b/drivers/resctrl/cbqri_devices.c
[..]
> > +
> > +/* Set capacity block mask (cc_block_mask) */
> > +static void cbqri_set_cbm(struct cbqri_controller *ctrl, u64 cbm)
> > +{
> > + iowrite64(cbm, ctrl->base + CBQRI_CC_BLOCK_MASK_OFF);
>
> The CBQRI spec allows naturally aligned 4-byte accesses and only guarantees
> atomicity for 4-byte accesses; 8-byte atomicity is unspecified.
>
> Would 32-bit split accesses be preferable here instead of relying on
> ioread64/iowrite64? This may also make the driver less dependent on native
> 64-bit MMIO support.
I suppose there could be systems that are RV64 but do 4-byte access for
the CBQRI registers. You are right the spec only guarantees atomicity
for naturally aligned 4-byte accesses and leaves 8-byte atomicity
unspecified.
I will switch the controller register accesses to 32-bit reads and
writes. The driver rejects ncblks > 32, so cc_block_mask only uses its
low 32 bits. For cc_alloc_ctl, the writable fields all sit in the low
word while the status and busy bits are read-only in the high word. A
read can reconstruct the value from two 32-bit reads and a write only
needs the low word.
Thanks,
Drew
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next prev parent reply other threads:[~2026-06-27 22:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-25 1:38 [PATCH v2 0/8] riscv: Add Ssqosid and initial CBQRI resctrl support Drew Fustini
2026-06-25 1:38 ` [PATCH v2 1/8] dt-bindings: riscv: Add Ssqosid extension description Drew Fustini
2026-06-25 1:38 ` [PATCH v2 2/8] riscv: Detect the Ssqosid extension Drew Fustini
2026-06-25 1:38 ` [PATCH v2 3/8] riscv: Add support for srmcfg CSR from " Drew Fustini
[not found] ` <20260625015006.DF5041F000E9@smtp.kernel.org>
2026-06-26 0:56 ` Drew Fustini
2026-06-27 9:11 ` [External] " yunhui cui
2026-06-27 21:21 ` Drew Fustini
2026-06-27 9:38 ` yunhui cui
2026-06-27 21:58 ` Drew Fustini
2026-06-25 1:38 ` [PATCH v2 4/8] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-06-27 9:19 ` [External] " yunhui cui
2026-06-27 21:45 ` Drew Fustini
2026-06-27 9:31 ` yunhui cui
2026-06-27 22:10 ` Drew Fustini [this message]
2026-06-25 1:38 ` [PATCH v2 5/8] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
[not found] ` <20260625015355.B997D1F000E9@smtp.kernel.org>
2026-06-26 20:44 ` Drew Fustini
2026-06-25 1:38 ` [PATCH v2 6/8] riscv: Enable resctrl filesystem for Ssqosid Drew Fustini
2026-06-25 1:38 ` [PATCH v2 7/8] dt-bindings: riscv: Add generic CBQRI controller binding Drew Fustini
2026-06-25 16:19 ` Conor Dooley
2026-06-25 19:21 ` Drew Fustini
2026-06-26 15:44 ` Conor Dooley
2026-06-26 16:05 ` Drew Fustini
2026-06-26 16:08 ` Conor Dooley
2026-06-25 1:38 ` [PATCH v2 8/8] riscv_cbqri: Add CBQRI cache capacity-allocation platform driver Drew Fustini
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