[PATCH 0/2] clk: spacemit: fix PLL init and add K3 1.8 GHz rates

[PATCH 0/2] clk: spacemit: fix PLL init and add K3 1.8 GHz rates

[Troy Mitchell]

The PLL and PLLA init callbacks leave a PLL gated off once they
reprogram an unmatched firmware configuration. Re-enable the PLL to
complete the disable-update-enable sequence and propagate any lock
timeout to clock registration. Apply this to both the K1 PLL and K3
PLLA implementations.

The K3 SoC may not remain stable when its A100 CPU clusters operate
persistently at 2 GHz. Updated U-Boot firmware therefore configures
their C2 and C3 clock domains at 1.8 GHz during early initialization.
PLL5 feeds C2 and PLL8 feeds C3, so add 1.8 GHz as the default
rate-table entry for both PLLs.

The related U-Boot change is available at:
https://github.com/spacemit-com/uboot-2022.10/commit/fb95cf3d848b771c61b5a1b3e5cbbee223faf352

Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
Troy Mitchell (2):
      clk: spacemit: re-enable PLLs after init
      clk: spacemit: k3: add 1.8 GHz PLL5 and PLL8 rates

 drivers/clk/spacemit/ccu-k3.c  | 2 ++
 drivers/clk/spacemit/ccu_pll.c | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)
---
base-commit: 1590cf0329716306e948a8fc29f1d3ee87d3989f
change-id: 20260802-k3-pll5-pll8-1800mhz-c81875a0a944

Best regards,
--  
Troy Mitchell <troy.mitchell@linux.spacemit.com>


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[PATCH 1/2] clk: spacemit: re-enable PLLs after init

[Troy Mitchell]

The PLL and PLLA init callbacks gate off and reprogram a PLL when its
firmware configuration is absent from the rate table. However, they
leave the PLL gated off after updating the registers.

Re-enable the PLL to complete the sequence and propagate any lock
timeout to clock registration.

Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
 drivers/clk/spacemit/ccu_pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c
index d4066a0ed452..f9627da0af37 100644
--- a/drivers/clk/spacemit/ccu_pll.c
+++ b/drivers/clk/spacemit/ccu_pll.c
@@ -148,7 +148,7 @@ static int ccu_pll_init(struct clk_hw *hw)
 	ccu_pll_disable(hw);
 	ccu_pll_update_param(pll, &pll->config.rate_tbl[0]);
 
-	return 0;
+	return ccu_pll_enable(hw);
 }
 
 static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll)
@@ -252,7 +252,7 @@ static int ccu_plla_init(struct clk_hw *hw)
 	ccu_plla_disable(hw);
 	ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
 
-	return 0;
+	return ccu_plla_enable(hw);
 }
 
 const struct clk_ops spacemit_ccu_pll_ops = {

-- 
2.55.0


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Re: [PATCH 1/2] clk: spacemit: re-enable PLLs after init

[Yao Zi]

On Tue, Aug 04, 2026 at 12:02:55AM -0700, Troy Mitchell wrote:
> The PLL and PLLA init callbacks gate off and reprogram a PLL when its
> firmware configuration is absent from the rate table. However, they
> leave the PLL gated off after updating the registers.

I don't think this patch makes sense.

If this PLL is essential for some components of the systems to work,
there's no chance to re-program it safely after the kernel gets started,
since all the PLLs in K1 and K3 are specified as CLK_SET_RATE_GATE.

If the essential clocks could be re-parented glitchlessly, registering
a notifier and re-parenting it before the PLL disables might be a
solution. In this case, we need to delay the operation in
ccu_pll*_init() until clock registration fully completes.

Otherwise, re-enabling the PLL seems totally extra here, they could be
enabled on the fly when it's going to be used.

> Re-enable the PLL to complete the sequence and propagate any lock
> timeout to clock registration.

Regards,
Yao Zi

> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>

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[PATCH 2/2] clk: spacemit: k3: add 1.8 GHz PLL5 and PLL8 rates

[Troy Mitchell]

The K3 SoC may not remain stable when its A100 CPU clusters operate
persistently at 2 GHz. Updated U-Boot firmware therefore configures
their C2 and C3 clock domains at 1.8 GHz during early initialization.
PLL5 feeds C2 and PLL8 feeds C3, but 2 GHz is currently the only entry
in both rate tables.

Add 1.8 GHz as the first entry in the PLL5 and PLL8 rate tables,
switching the driver default from 2 GHz to 1.8 GHz.

Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
 drivers/clk/spacemit/ccu-k3.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
index cb0c4277f72a..e8b7ce89c2cb 100644
--- a/drivers/clk/spacemit/ccu-k3.c
+++ b/drivers/clk/spacemit/ccu-k3.c
@@ -38,6 +38,7 @@ static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = {
 };
 
 static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = {
+	CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
 	CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
 };
 
@@ -50,6 +51,7 @@ static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = {
 };
 
 static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = {
+	CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585),
 	CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
 };
 

-- 
2.55.0


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