From: "Stefan O'Rear" <sorear@fastmail.com>
To: "Yong-Xuan Wang" <yongxuan.wang@sifive.com>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Cc: greentime.hu@sifive.com, vincent.chen@sifive.com,
tjytimi@163.com, alex@ghiti.fr, "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/3] dt-bindings: riscv: Add Svadu Entry
Date: Wed, 27 Sep 2023 13:24:03 -0400 [thread overview]
Message-ID: <d141062b-e3e0-45ce-bc61-3404417c7d7c@app.fastmail.com> (raw)
In-Reply-To: <20230922085701.3164-3-yongxuan.wang@sifive.com>
On Fri, Sep 22, 2023, at 4:56 AM, Yong-Xuan Wang wrote:
> Add an entry for the Svadu extension to the riscv,isa-extensions property.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml
> b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..b5a0aed0165b 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -147,6 +147,12 @@ properties:
> ratified at commit 3f9ed34 ("Add ability to manually
> trigger
> workflow. (#2)") of riscv-time-compare.
>
> + - const: svadu
> + description: |
> + The standard Svadu supervisor-level extension for hardware updating
> + of PTE A/D bits as frozen at commit b65e07c ("move to Frozen
> + state") of riscv-svadu.
> +
This is incomplete without a specification of the behavior of the HADE bit implied
by svadu being present.
The ratified RVA20 requires page table accesses with A/D = 0 to trap, in other
words HADE = 0 for RVA20 conformance. If we are serious about compatibility,
I think that we need platforms to be able to conform to both RVA20 and RVA23,
which requires HADE = 0 at kernel entry with a SBI call to set HADE = 1. For
the same reason KVM should probably default to HADE = 0 so that the default
configuration remains conformant to RVA20.
-s
> - const: svinval
> description:
> The standard Svinval supervisor-level extension for fine-grained
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2023-09-27 17:24 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-22 8:56 [PATCH v2 0/3] Add Svadu Extension Support Yong-Xuan Wang
2023-09-22 8:56 ` [PATCH v2 1/3] RISC-V: Detect and Enable " Yong-Xuan Wang
2023-09-22 9:38 ` Conor Dooley
2023-09-27 7:03 ` Andrew Jones
2023-09-27 11:02 ` Yong-Xuan Wang
2023-09-27 7:16 ` Matthew Wilcox
2023-09-22 8:56 ` [PATCH v2 2/3] dt-bindings: riscv: Add Svadu Entry Yong-Xuan Wang
2023-09-22 9:28 ` Conor Dooley
2023-09-27 7:04 ` Andrew Jones
2023-09-27 17:24 ` Stefan O'Rear [this message]
2023-09-27 18:44 ` Jessica Clarke
2023-09-22 8:56 ` [PATCH v2 3/3] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Yong-Xuan Wang
2023-09-27 7:27 ` Andrew Jones
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