* [PATCH v2 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
@ 2018-03-16 3:02 Lin Huang
[not found] ` <1521169348-8552-1-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Lin Huang @ 2018-03-16 3:02 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, Lin Huang,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
briannorris-F7+t8E8rja9g9hUCZPvPmw,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
diander-F7+t8E8rja9g9hUCZPvPmw, linux-clk-u79uwXL29TY76Z2rM5mHXA
Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
and these two PLL may change their frequency. If we do not
assign right id to pclk_ddr and hclk_sd, they will alway use
default cur register value, and may get the frequency
exceed their signed off frequency. So assign correct Id
for them, then we can assign frequency for them in dts.
Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v2:
- add more detail in commit message
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3e57c6e..bca10d6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -671,7 +671,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(9), 7, GFLAGS,
&rk3399_uart3_fracmux),
- COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
+ COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(3), 4, GFLAGS),
@@ -887,7 +887,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(31), 8, GFLAGS),
/* sdio & sdmmc */
- COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
+ COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(12), 13, GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
[not found] ` <1521169348-8552-1-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
@ 2018-03-16 3:02 ` Lin Huang
[not found] ` <1521169348-8552-2-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Lin Huang @ 2018-03-16 3:02 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: dbasehore-F7+t8E8rja9g9hUCZPvPmw, Lin Huang,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
briannorris-F7+t8E8rja9g9hUCZPvPmw,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
diander-F7+t8E8rja9g9hUCZPvPmw, linux-clk-u79uwXL29TY76Z2rM5mHXA
These clocks do not assign default clock frequency, and use the
default cru register value to get frequency, so if cpll increase
frequency, these clocks also increase their frequency, that may
exceed their signed off frequency. So assign default clock for
them to avoid it.
Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 8 +++++++-
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 ++++++++++++--
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 18f546f..84e367b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -588,7 +588,10 @@
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
- <&cru ACLK_VIO>;
+ <&cru ACLK_VIO>,
+ <&cru ACLK_GIC_PRE>,
+ <&cru PCLK_DDR>,
+ <&cru ACLK_HDCP>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
@@ -597,6 +600,9 @@
<100000000>, <100000000>,
<50000000>, <800000000>,
<100000000>, <50000000>,
+ <400000000>,
+ <200000000>,
+ <200000000>,
<400000000>;
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4550c0f..b358533 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,6 +315,8 @@
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ assigned-clocks = <&cru HCLK_SD>;
+ assigned-clock-rates = <200000000>;
fifo-depth = <0x100>;
power-domains = <&power RK3399_PD_SD>;
resets = <&cru SRST_SDMMC>;
@@ -466,8 +468,10 @@
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
- phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
+ assigned-clock-rates = <100000000>, <200000000>;
power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
<&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
reset-names = "spdif", "dptx", "apb", "core";
@@ -1323,7 +1327,10 @@
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
- <&cru ACLK_VIO>;
+ <&cru ACLK_VIO>,
+ <&cru ACLK_GIC_PRE>,
+ <&cru PCLK_DDR>,
+ <&cru ACLK_HDCP>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@@ -1332,6 +1339,9 @@
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>,
+ <400000000>,
+ <200000000>,
+ <200000000>,
<400000000>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock
[not found] ` <1521169348-8552-2-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
@ 2018-03-16 17:16 ` Doug Anderson
0 siblings, 0 replies; 3+ messages in thread
From: Doug Anderson @ 2018-03-16 17:16 UTC (permalink / raw)
To: Lin Huang
Cc: Derek Basehore, Heiko Stübner, Shawn Lin, Brian Norris,
open list:ARM/Rockchip SoC..., diander-F7+t8E8rja9g9hUCZPvPmw,
linux-clk
Hi,
On Thu, Mar 15, 2018 at 8:02 PM, Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> These clocks do not assign default clock frequency, and use the
> default cru register value to get frequency, so if cpll increase
> frequency, these clocks also increase their frequency, that may
> exceed their signed off frequency. So assign default clock for
> them to avoid it.
>
> Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401
> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 8 +++++++-
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 ++++++++++++--
> 2 files changed, 19 insertions(+), 3 deletions(-)
This seems fine to me.
For the previous similar change I liked the idea of explaining in the
commit message why it's a good idea to include these rates in the CRU
node even though the same CRU node explicitly sets the CPLL to 800
MHz. AKA, you could add to the commit message:
NOTE: on none of the boards currently in mainline do we expect CPLL to
be anything other than 800 MHz, but some future boards might have it.
It's still good to be explicit about the clock rates to make diffing
against future boards easier and also to rely less on BIOS muxing.
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 4550c0f..b358533 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -315,6 +315,8 @@
> clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
> <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
> clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + assigned-clocks = <&cru HCLK_SD>;
> + assigned-clock-rates = <200000000>;
To make things symmetric I'd probably also add a similar setting for
hclk_sdio unless there's a reason that 200 MHz isn't the right rate
there.
Oh, actually, the clock tree isn't very symmetric here anyway, is it?
For SDIO the clocks all come straight from "hclk_perilp1". I guess
you could explicitly set "hclk_sdio", and "hclk_sdio_noc" (and
"hclk_sdioaudio_noc"?) to 200 MHz.
In any case, since it's not symmetric then I won't push for it being
in this patch. Certainly the change in CPLL won't affect them since
they're parented off hclk_peripl1 and we already have that taken care
of...
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org><div
class="gmail_extra"><br><div class="gmail_quote">On Thu, Mar 15, 2018
at 8:02 PM, Lin Huang <span dir="ltr"><<a
href="mailto:hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org"
target="_blank">hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org</a>></span> wrote:<br><blockquote
class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc
solid;padding-left:1ex">These clocks do not assign default clock
frequency, and use the<br>
default cru register value to get frequency, so if cpll increase<br>
frequency, these clocks also increase their frequency, that may<br>
exceed their signed off frequency. So assign default clock for<br>
them to avoid it.<br>
<br>
Change-Id: If79368aeda5c51dbf2a3b6659f170<wbr>52a2ae4a401<br>
Signed-off-by: Lin Huang <<a
href="mailto:hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org">hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org</a>><br>
---<br>
arch/arm64/boot/dts/rockchip/<wbr>rk3399-gru.dtsi | 8 +++++++-<br>
arch/arm64/boot/dts/rockchip/<wbr>rk3399.dtsi
| 14 ++++++++++++--<br>
2 files changed, 19 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi
b/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi<br>
index 18f546f..84e367b 100644<br>
--- a/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi<br>
+++ b/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi<br>
@@ -588,7 +588,10 @@<br>
<&cru
ACLK_PERILP0>, <&cru HCLK_PERILP0>,<br>
<&cru
PCLK_PERILP0>, <&cru ACLK_CCI>,<br>
<&cru
HCLK_PERILP1>, <&cru PCLK_PERILP1>,<br>
- <&cru
ACLK_VIO>;<br>
+ <&cru
ACLK_VIO>,<br>
+ <&cru
ACLK_GIC_PRE>,<br>
+ <&cru
PCLK_DDR>,<br>
+ <&cru
ACLK_HDCP>;<br>
assigned-clock-rates =<br>
<600000000>, <800000000>,<br>
<1000000000>,<br>
@@ -597,6 +600,9 @@<br>
<100000000>, <100000000>,<br>
<50000000>, <800000000>,<br>
<100000000>, <50000000>,<br>
+ <400000000>,<br>
+ <200000000>,<br>
+ <200000000>,<br>
<400000000>;<br>
};<br>
<br>
diff --git a/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi<br>
index 4550c0f..b358533 100644<br>
--- a/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi<br>
+++ b/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi<br>
@@ -315,6 +315,8 @@<br>
clocks =
<&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,<br>
<&cru SCLK_SDMMC_DRV>, <&cru
SCLK_SDMMC_SAMPLE>;<br>
clock-names =
"biu", "ciu", "ciu-drive", "ciu-sample";<br>
+
assigned-clocks = <&cru HCLK_SD>;<br>
+
assigned-clock-rates = <200000000>;<br>
fifo-depth =
<0x100>;<br>
power-domains
= <&power RK3399_PD_SD>;<br>
resets =
<&cru SRST_SDMMC>;<br>
@@ -466,8 +468,10 @@<br>
clocks =
<&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,<br>
<&cru SCLK_SPDIF_REC_DPTX>, <&cru
PCLK_VIO_GRF>;<br>
clock-names =
"core-clk", "pclk", "spdif", "grf";<br>
- phys =
<&tcphy0_dp>, <&tcphy1_dp>;<br>
+
assigned-clocks = <&cru SCLK_DP_CORE>, <&cru
SCLK_SPDIF_REC_DPTX>;<br>
+
assigned-clock-rates = <100000000>, <200000000>;<br>
power-domains
= <&power RK3399_PD_HDCP>;<br>
+ phys =
<&tcphy0_dp>, <&tcphy1_dp>;<br>
resets =
<&cru SRST_DPTX_SPDIF_REC>, <&cru
SRST_P_UPHY0_DPTX>,<br>
<&cru SRST_P_UPHY0_APB>, <&cru
SRST_DP_CORE>;<br>
reset-names =
"spdif", "dptx", "apb", "core";<br>
@@ -1323,7 +1327,10 @@<br>
<&cru ACLK_PERILP0>, <&cru
HCLK_PERILP0>,<br>
<&cru PCLK_PERILP0>, <&cru
ACLK_CCI>,<br>
<&cru HCLK_PERILP1>, <&cru
PCLK_PERILP1>,<br>
-
<&cru ACLK_VIO>;<br>
+
<&cru ACLK_VIO>,<br>
+
<&cru ACLK_GIC_PRE>,<br>
+
<&cru PCLK_DDR>,<br>
+
<&cru ACLK_HDCP>;<br>
assigned-clock-rates =<br>
<594000000>, <800000000>,<br>
<1000000000>,<br>
@@ -1332,6 +1339,9 @@<br>
<100000000>, <100000000>,<br>
<50000000>, <600000000>,<br>
<100000000>,
<50000000>,<br>
+
<400000000>,<br>
+
<200000000>,<br>
+
<200000000>,<br>
<400000000>;<br>
};<br>
<span class="HOEnZb"><font color="#888888"><br>
--<br>
2.7.4<br>
<br>
<br>
______________________________<wbr>_________________<br>
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</font></span></blockquote></div><br></div>
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2018-03-16 3:02 [PATCH v2 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Lin Huang
[not found] ` <1521169348-8552-1-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-03-16 3:02 ` [PATCH v2 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock Lin Huang
[not found] ` <1521169348-8552-2-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-03-16 17:16 ` Doug Anderson
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