From: Vinod Koul <vkoul@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
linux-phy@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
Date: Thu, 20 Nov 2025 22:42:00 +0530 [thread overview]
Message-ID: <176365872091.207696.17487424973195215305.b4-ty@kernel.org> (raw)
In-Reply-To: <1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com>
On Tue, 18 Nov 2025 17:52:05 +0800, Shawn Lin wrote:
> When PCIe link enters L1 PM substates, the PHY will turn off its
> PLL for power-saving. However, it turns off the PLL too fast which
> leads the PHY to be broken. According to the PHY document, we need
> to delay PLL turnoff time.
>
>
Applied, thanks!
[1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
commit: a2a18e5da64f8da306fa97c397b4c739ea776f37
[2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
commit: be866e68966d20bcc4a73708093d577176f99c0c
Best regards,
--
~Vinod
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prev parent reply other threads:[~2025-11-20 17:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-18 9:52 [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Shawn Lin
2025-11-18 9:52 ` [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 Shawn Lin
2025-11-18 13:47 ` Neil Armstrong
2025-11-18 13:47 ` [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Neil Armstrong
2025-11-20 17:12 ` Vinod Koul [this message]
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