[PATCH 2/2] PCI: dw-rockchip: Add .ltssm_trace() support

[Shawn Lin <shawn.lin@rock-chips.com>]

Rockchip platforms provide a 64x4 bytes debug FIFO to trace the
LTSSM history. Any LTSSM change will be recorded. It's userful
for debug purpose, for example link failure, etc.

  cat /sys/kernel/debug/dwc_pcie_a40c00000.pcie/ltssm_trace
    DETECT_QUIET (0x00)
    DETECT_ACT (0x01)
    POLL_ACTIVE (0x02)
    POLL_COMPLIANCE (0x03)
    POLL_ACTIVE (0x02)
    POLL_CONFIG (0x04)
    CFG_LINKWD_START (0x07)
    ...
    RCVRY_IDLE (0x10)
    L0 (0x11)
    L123_SEND_EIDLE (0x13)
    L1_IDLE (0x14)
    RCVRY_LOCK (0x0d)
    ...

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 352f513ebf03..0f7430e686b2 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -73,6 +73,17 @@
 #define  PCIE_CLIENT_CDM_RASDES_TBA_L1_1	BIT(4)
 #define  PCIE_CLIENT_CDM_RASDES_TBA_L1_2	BIT(5)
 
+/* Debug FIFO information */
+#define PCIE_CLIENT_DBG_FIFO_MODE_CON	0x310
+#define  PCIE_CLIENT_DBG_EN		0xffff0007
+#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0	0x320
+#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1	0x324
+#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0	0x328
+#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1	0x32c
+#define  PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
+#define PCIE_CLIENT_DBG_FIFO_STATUS	0x350
+#define PCIE_DBG_LTSSM_HISTORY_CNT	64
+
 /* Hot Reset Control Register */
 #define PCIE_CLIENT_HOT_RESET_CTRL	0x180
 #define  PCIE_LTSSM_APP_DLY2_EN		BIT(1)
@@ -96,6 +107,7 @@ struct rockchip_pcie {
 	struct irq_domain *irq_domain;
 	const struct rockchip_pcie_of_data *data;
 	bool supports_clkreq;
+	struct dw_pcie_ltssm_history ltssm_history;
 };
 
 struct rockchip_pcie_of_data {
@@ -206,6 +218,34 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
 	return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;
 }
 
+static void rockchip_pcie_enable_ltssm_trace(struct rockchip_pcie *rockchip)
+{
+        rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
+				 PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0);
+        rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
+				 PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1);
+        rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
+				 PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0);
+        rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_TRANSITION_DATA,
+				 PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1);
+        rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DBG_EN,
+				 PCIE_CLIENT_DBG_FIFO_MODE_CON);
+}
+
+static struct dw_pcie_ltssm_history* rockchip_pcie_ltssm_trace(struct dw_pcie *pci)
+{
+	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
+	u32 loop, val;
+
+	for (loop = 0; loop < PCIE_DBG_LTSSM_HISTORY_CNT; loop++) {
+		val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_DBG_FIFO_STATUS) &
+					PCIE_LTSSM_STATUS_MASK;
+		rockchip->ltssm_history.states[loop] = val;
+	}
+
+	return &rockchip->ltssm_history;
+}
+
 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
 {
 	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
@@ -277,6 +317,8 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)
 	/* Reset device */
 	gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
 
+	rockchip_pcie_enable_ltssm_trace(rockchip);
+
 	rockchip_pcie_enable_ltssm(rockchip);
 
 	/*
@@ -506,6 +548,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 	.start_link = rockchip_pcie_start_link,
 	.stop_link = rockchip_pcie_stop_link,
 	.get_ltssm = rockchip_pcie_get_ltssm,
+	.ltssm_trace = rockchip_pcie_ltssm_trace,
 };
 
 static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
@@ -645,6 +688,12 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	rockchip->pci.ops = &dw_pcie_ops;
 	rockchip->data = data;
 
+	rockchip->ltssm_history.count = PCIE_DBG_LTSSM_HISTORY_CNT;
+	rockchip->ltssm_history.states = devm_kzalloc(dev,
+			PCIE_DBG_LTSSM_HISTORY_CNT * sizeof(u32), GFP_KERNEL);
+	if (!rockchip->ltssm_history.states)
+		return -ENOMEM;
+
 	/* Default N_FTS value (210) is broken, override it to 255 */
 	rockchip->pci.n_fts[0] = 255; /* Gen1 */
 	rockchip->pci.n_fts[1] = 255; /* Gen2+ */
-- 
2.43.0


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