[PATCH 0/3] Correctly implemet the usb480m clock on rk3036

[PATCH 0/3] Correctly implemet the usb480m clock on rk3036

[Heiko Stuebner]

In the original clock driver the usb480m clock was "stubbed" as a fixed
factor clock, but instead it actually does have a mux-bit to switch
between the 24MHz osciallator and the actual 480MHz clock supplied
from the usb-phy.

Both the register layout, as well as the implementation is very similar
to the rk3128, which seems to be some sort of cousin to the rk3036.


Heiko Stuebner (3):
  dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  clk: rockchip: rk3036: mark ddrphy as critical

 drivers/clk/rockchip/clk-rk3036.c      | 11 +++++------
 include/dt-bindings/clock/rk3036-cru.h |  1 +
 2 files changed, 6 insertions(+), 6 deletions(-)

-- 
2.47.2


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[PATCH 1/3] dt-bindings: clock: rk3036: add SCLK_USB480M clock-id

[Heiko Stuebner]

Contrary to how it is implemented right now, the usb480m clock is a
controllable mux that can switch between the 24MHz oscillator and the
clock output of the usb2phy.

Add the needed clock-id to allow setting this mux from DT.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 include/dt-bindings/clock/rk3036-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
index 99cc617e1e54..5cbc0e2b08ff 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -47,6 +47,7 @@
 #define SCLK_MACREF		152
 #define SCLK_MACPLL		153
 #define SCLK_SFC		160
+#define SCLK_USB480M		161
 
 /* aclk gates */
 #define ACLK_DMAC2		194
-- 
2.47.2


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Re: [PATCH 1/3] dt-bindings: clock: rk3036: add SCLK_USB480M clock-id

[Conor Dooley]

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On Sat, May 03, 2025 at 10:25:29PM +0200, Heiko Stuebner wrote:
> Contrary to how it is implemented right now, the usb480m clock is a
> controllable mux that can switch between the 24MHz oscillator and the
> clock output of the usb2phy.
> 
> Add the needed clock-id to allow setting this mux from DT.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  include/dt-bindings/clock/rk3036-cru.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
> index 99cc617e1e54..5cbc0e2b08ff 100644
> --- a/include/dt-bindings/clock/rk3036-cru.h
> +++ b/include/dt-bindings/clock/rk3036-cru.h
> @@ -47,6 +47,7 @@
>  #define SCLK_MACREF		152
>  #define SCLK_MACPLL		153
>  #define SCLK_SFC		160
> +#define SCLK_USB480M		161
>  
>  /* aclk gates */
>  #define ACLK_DMAC2		194
> -- 
> 2.47.2
> 

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[PATCH 2/3] clk: rockchip: rk3036: fix implementation of usb480m clock mux

[Heiko Stuebner]

Contrary to how it is implemented right now, this mux is controllable via
a bit in CRU_MUSC_CON (same bit as on rk3128 even) and allows switching
between xin24m and the 480m output of the usb2phy.

So drop the hard-coded fixed-factor clock and implement the correct mux
instead.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3036.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index d341ce0708aa..41c71bb25171 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -123,6 +123,7 @@ PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };
 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll", "usb480m" };
 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p)   = { "dummy_apll", "dpll", "gpll", "xin24m" };
 
+PNAME(mux_usb480m_p)	= { "usb480m_phy", "xin24m" };
 PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };
 PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_clkout_p)	= { "i2s_pre", "xin12m" };
@@ -423,6 +424,9 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+
+	MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
+			RK2928_MISC_CON, 15, 1, MFLAGS),
 };
 
 static const char *const rk3036_critical_clocks[] __initconst = {
@@ -438,7 +442,6 @@ static void __init rk3036_clk_init(struct device_node *np)
 	struct rockchip_clk_provider *ctx;
 	unsigned long clk_nr_clks;
 	void __iomem *reg_base;
-	struct clk *clk;
 
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
@@ -462,11 +465,6 @@ static void __init rk3036_clk_init(struct device_node *np)
 		return;
 	}
 
-	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
-	if (IS_ERR(clk))
-		pr_warn("%s: could not register clock usb480m: %ld\n",
-			__func__, PTR_ERR(clk));
-
 	rockchip_clk_register_plls(ctx, rk3036_pll_clks,
 				   ARRAY_SIZE(rk3036_pll_clks),
 				   RK3036_GRF_SOC_STATUS0);
-- 
2.47.2


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[PATCH 3/3] clk: rockchip: rk3036: mark ddrphy as critical

[Heiko Stuebner]

The ddrphy is supplied by the dpll, but due to the limited number of PLLs
on the rk3036, the dpll also is used for other periperhals, like the GPU.

So it happened, when the Lima driver turned off the gpu clock, this in
turn also disabled the dpll and thus the ram.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3036.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 41c71bb25171..df9330958c83 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -435,6 +435,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {
 	"hclk_peri",
 	"pclk_peri",
 	"pclk_ddrupctl",
+	"ddrphy",
 };
 
 static void __init rk3036_clk_init(struct device_node *np)
-- 
2.47.2


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Re: [PATCH 0/3] Correctly implemet the usb480m clock on rk3036

[Heiko Stuebner]

On Sat, 03 May 2025 22:25:28 +0200, Heiko Stuebner wrote:
> In the original clock driver the usb480m clock was "stubbed" as a fixed
> factor clock, but instead it actually does have a mux-bit to switch
> between the 24MHz osciallator and the actual 480MHz clock supplied
> from the usb-phy.
> 
> Both the register layout, as well as the implementation is very similar
> to the rk3128, which seems to be some sort of cousin to the rk3036.
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
      commit: 6e06b641ca96c232e0b13f9b44b118742986bcd5
[2/3] clk: rockchip: rk3036: fix implementation of usb480m clock mux
      commit: 897adaf536ab01f130ce0b53a635a592733c0f24
[3/3] clk: rockchip: rk3036: mark ddrphy as critical
      commit: 596a977b34a722c00245801a5774aa79cec4e81d

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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