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From: Niklas Cassel <cassel@kernel.org>
To: "Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Niklas Cassel" <cassel@kernel.org>,
	"Krishna chaitanya chundru" <quic_krichai@quicinc.com>
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
	Damien Le Moal <dlemoal@kernel.org>,
	Laszlo Fiat <laszlo.fiat@proton.me>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-msm@vger.kernel.org
Subject: [PATCH 0/4] PCI: dwc: Do not enumerate bus before endpoint devices are ready
Date: Wed, 11 Jun 2025 12:51:41 +0200	[thread overview]
Message-ID: <20250611105140.1639031-6-cassel@kernel.org> (raw)

Hello all,

The DWC PCIe controller driver currently does not follow the PCIe
specification with regards to the delays after link training, before
sending out configuration requests. This series fixes this.

At the same time, PATCH 1/4 addresses a regression where a Plextor
NVMe drive fails to be configured correctly. With this series, the
Plextor NVMe drive works once again.


Kind regards,
Niklas


Niklas Cassel (4):
  PCI: dw-rockchip: Do not enumerate bus before endpoint devices are
    ready
  PCI: qcom: Do not enumerate bus before endpoint devices are ready
  PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link
    up
  PCI: dwc: Reduce LINK_WAIT_SLEEP_MS

 drivers/pci/controller/dwc/pcie-designware.c  | 13 ++++++++++++-
 drivers/pci/controller/dwc/pcie-designware.h  | 11 ++++++++---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c |  7 +++++++
 drivers/pci/controller/dwc/pcie-qcom.c        |  7 +++++++
 4 files changed, 34 insertions(+), 4 deletions(-)

-- 
2.49.0


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             reply	other threads:[~2025-06-11 14:53 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-11 10:51 Niklas Cassel [this message]
2025-06-11 10:51 ` [PATCH 1/4] PCI: dw-rockchip: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-11 12:33   ` Damien Le Moal
2025-06-11 21:14   ` Bjorn Helgaas
2025-06-12 11:19     ` Niklas Cassel
2025-06-12 11:38       ` Bjorn Helgaas
2025-06-12 11:40         ` Niklas Cassel
2025-06-12 12:21           ` Bjorn Helgaas
2025-06-12 13:00             ` Manivannan Sadhasivam
2025-06-12 14:44               ` Bjorn Helgaas
2025-06-12 15:03                 ` Manivannan Sadhasivam
2025-06-12 15:24                   ` Bjorn Helgaas
2025-06-12 16:51                     ` Manivannan Sadhasivam

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