* [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588
@ 2026-04-24 17:58 Paul Elder
2026-04-24 17:58 ` [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings Paul Elder
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Paul Elder @ 2026-04-24 17:58 UTC (permalink / raw)
To: laurent.pinchart
Cc: Paul Elder, michael.riesch, xuhf, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel
Hello everyone!
This patch series adds a new rkisp2 driver that aims to support all
Rockchip 2.x and 3.x series ISPs. Here we add support for the version on
the RK3588, which as far as I'm aware is a 3.0.
Patches 1 and 2 add dt bindings and dt nodes; patches 3~5 add the actual
driver.
All my discussion points/questions/progress-reports are in patch 3.
The following two series [0] [1] will be helpful for testing the code,
as they enable the VICAP module to work on the RK3588. I've tested this
on the Orange Pi CM5 Base with an imx219. I have a branch here [2] for
convenience. A libcamera branch will be coming soon too!
[0] https://lore.kernel.org/all/20260216-rkcif-fixes-v2-0-ee40931fe0ff@collabora.com/
[1] https://lore.kernel.org/all/20250430-rk3588-vicap-v3-0-e38e428868cc@collabora.com/
[2] https://git.ideasonboard.com/epaul/linux/src/branch/epaul/v7.0/rk3588/rkisp2/upstream
Paul Elder (3):
media: dt-bindings: Add rockchip rkisp2 bindings
media: rkisp2: Add parameters output video node
media: rkisp2: Add statistics capture video node
Xu Hongfei (2):
arm64: dts: rockchip: add ISP nodes to rk3588
media: rockchip: rkisp2: Add rkisp2 driver
.../bindings/media/rockchip-isp2.yaml | 127 +
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 60 +
drivers/media/platform/rockchip/Kconfig | 1 +
drivers/media/platform/rockchip/Makefile | 1 +
.../media/platform/rockchip/rkisp2/Kconfig | 19 +
.../media/platform/rockchip/rkisp2/Makefile | 13 +
.../platform/rockchip/rkisp2/rkisp2-capture.c | 1979 ++++++++++
.../platform/rockchip/rkisp2/rkisp2-common.c | 180 +
.../platform/rockchip/rkisp2/rkisp2-common.h | 565 +++
.../platform/rockchip/rkisp2/rkisp2-debug.c | 236 ++
.../platform/rockchip/rkisp2/rkisp2-dev.c | 376 ++
.../platform/rockchip/rkisp2/rkisp2-dmarx.c | 687 ++++
.../platform/rockchip/rkisp2/rkisp2-isp.c | 917 +++++
.../platform/rockchip/rkisp2/rkisp2-params.c | 1013 +++++
.../rockchip/rkisp2/rkisp2-regs-v2x.h | 2625 +++++++++++++
.../rockchip/rkisp2/rkisp2-regs-v3x.h | 3427 +++++++++++++++++
.../platform/rockchip/rkisp2/rkisp2-regs.h | 1736 +++++++++
.../platform/rockchip/rkisp2/rkisp2-stats.c | 482 +++
drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
include/uapi/linux/rkisp1-config.h | 1 +
include/uapi/linux/rkisp2-config.h | 565 +++
include/uapi/linux/videodev2.h | 4 +
22 files changed, 15016 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp2.yaml
create mode 100644 drivers/media/platform/rockchip/rkisp2/Kconfig
create mode 100644 drivers/media/platform/rockchip/rkisp2/Makefile
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-capture.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-common.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-dmarx.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-regs.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-stats.c
create mode 100644 include/uapi/linux/rkisp2-config.h
--
2.47.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings
2026-04-24 17:58 [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588 Paul Elder
@ 2026-04-24 17:58 ` Paul Elder
2026-04-24 18:05 ` Paul Elder
2026-04-24 17:58 ` [RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588 Paul Elder
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Paul Elder @ 2026-04-24 17:58 UTC (permalink / raw)
To: laurent.pinchart
Cc: Paul Elder, michael.riesch, xuhf, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel, Heiko Stuebner
Add documentation for the Rockchip rkisp2 bindings. This is meant to
support multiple versions of Rockchip ISPs going forward, including the
2.x series and 3.x series. The current version only adds the compatible
for the RK3588, which is a 3.0.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
---
.../bindings/media/rockchip-isp2.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp2.yaml
diff --git a/Documentation/devicetree/bindings/media/rockchip-isp2.yaml b/Documentation/devicetree/bindings/media/rockchip-isp2.yaml
new file mode 100644
index 000000000000..f4ef089adf6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/rockchip-isp2.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip-isp2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Image Signal Processing unit v2
+
+maintainers:
+ - Paul Elder <paul.elder@ideasonboard.com>
+
+description: |
+ Rockchip ISP2 is the Camera interface for the Rockchip series of SoCs which
+ contains image processing, scaling, and compression functions.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3588-isp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: isp_irq
+ - const: mi_irq
+
+ clocks:
+ minItems: 3
+ items:
+ - description: ISP AXI clock (aclk)
+ - description: ISP AHB clock (hclk)
+ - description: ISP core clock (isp)
+ # for rk3588
+ - description: ISP core clock (marvin)
+ - description: ISP core clock (vicap)
+
+ clock-names:
+ minItems: 3
+ items:
+ - const: aclk
+ - const: hclk
+ - const: clk_core
+ # for rk3588
+ - const: clk_core_marvin
+ - const: clk_core_vicap
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ minItems: 1
+ items:
+ - description: ISP power domain
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for VICAP in inline mode
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3588-isp
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ clock-names:
+ minItems: 5
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3588-power.h>
+
+ parent0: parent {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp0: isp@fdcb0000 {
+ compatible = "rockchip,rk3588-isp";
+ reg = <0x0 0xfdcb0000 0x0 0x7f00>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp_irq", "mi_irq";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
+ <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
+ <&cru CLK_ISP0_CORE_VICAP>;
+ clock-names = "aclk", "hclk", "clk_core",
+ "clk_core_marvin", "clk_core_vicap";
+ power-domains = <&power RK3588_PD_VI>;
+ iommus = <&isp0_mmu>;
+ };
+ };
--
2.47.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588
2026-04-24 17:58 [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588 Paul Elder
2026-04-24 17:58 ` [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings Paul Elder
@ 2026-04-24 17:58 ` Paul Elder
2026-04-24 23:00 ` Laurent Pinchart
2026-04-24 17:58 ` [RFC PATCH 3/5] media: rockchip: rkisp2: Add rkisp2 driver Paul Elder
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Paul Elder @ 2026-04-24 17:58 UTC (permalink / raw)
To: laurent.pinchart
Cc: Xu Hongfei, michael.riesch, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel, Paul Elder,
Heiko Stuebner
From: Xu Hongfei <xuhf@rock-chips.com>
Add device tree nodes for the ISP and their iommus on the RK3588.
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 8b98e5c3cc8b..607b03d55dfd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -3535,6 +3535,66 @@ gpio4: gpio@fec50000 {
#interrupt-cells = <2>;
};
};
+
+ isp0: isp@fdcb0000 {
+ compatible = "rockchip,rk3588-isp";
+ reg = <0x0 0xfdcb0000 0x0 0x7f00>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp_irq", "mi_irq";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
+ <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
+ <&cru CLK_ISP0_CORE_VICAP>;
+ clock-names = "aclk", "hclk", "clk_core",
+ "clk_core_marvin", "clk_core_vicap";
+ power-domains = <&power RK3588_PD_VI>;
+ iommus = <&isp0_mmu>;
+ status = "disabled";
+ };
+
+ isp0_mmu: iommu@fdcb7f00 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdcb7f00 0x0 0x100>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp0_mmu";
+ clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_VI>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
+
+ isp1: isp@fdcc0000 {
+ compatible = "rockchip,rk3588-isp";
+ reg = <0x0 0xfdcc0000 0x0 0x7f00>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp_irq", "mi_irq";
+ clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
+ <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>,
+ <&cru CLK_ISP1_CORE_VICAP>;
+ clock-names = "aclk", "hclk", "clk_core",
+ "clk_core_marvin", "clk_core_vicap";
+ power-domains = <&power RK3588_PD_ISP1>;
+ iommus = <&isp1_mmu>;
+ status = "disabled";
+ };
+
+ isp1_mmu: iommu@fdcc7f00 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdcc7f00 0x0 0x100>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp1_mmu";
+ clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3588_PD_ISP1>;
+ #iommu-cells = <0>;
+ rockchip,disable-mmu-reset;
+ status = "disabled";
+ };
};
#include "rk3588-base-pinctrl.dtsi"
--
2.47.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [RFC PATCH 3/5] media: rockchip: rkisp2: Add rkisp2 driver
2026-04-24 17:58 [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588 Paul Elder
2026-04-24 17:58 ` [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings Paul Elder
2026-04-24 17:58 ` [RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588 Paul Elder
@ 2026-04-24 17:58 ` Paul Elder
2026-04-24 17:58 ` [RFC PATCH 4/5] media: rkisp2: Add parameters output video node Paul Elder
2026-04-24 17:58 ` [RFC PATCH 5/5] media: rkisp2: Add statistics capture " Paul Elder
4 siblings, 0 replies; 8+ messages in thread
From: Paul Elder @ 2026-04-24 17:58 UTC (permalink / raw)
To: laurent.pinchart
Cc: Xu Hongfei, michael.riesch, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel, Paul Elder,
Heiko Stuebner
From: Xu Hongfei <xuhf@rock-chips.com>
This patch adds the rkisp2 driver, which aims to support all Rockchip
ISP 2.x and 3.x versions. This initial version only supports the version
of the ISP on the RK3588, which is a 3.0.
The current version of the driver has the following features and
limitations:
Supported features:
- Single frame input/output
- mem-to-mem input via DMARX
- Main path and self path capture with cropping and scaling
- Output formats: UYVY, NV12, NV16, NV61, GREY
- YUYV doesn't seem to be supported by hardware
Limitations:
- No inline mode
- No HDR
- No virtual pipeline (TDM)
- No unite mode (using both ISPs together for one big image)
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
---
Work in progress notes:
- Using 8-bit raw as input to the ISP causes an unending page fault
storm that stalls capture
- After a stream ends there is a usually-finite page fault storm. This
is under investigation
- NV21 and YUV422 and YVU422 need some debugging
- I haven't tested raw output yet since VICAP can be used on its own for
raw output
- Self path and dual crop and resizer are implemented but I haven't
tested them yet. Given how similar the code and hardware is to rkisp1
they *should* work.
Discussion points:
- I want to redesign the media graph so that there are no more resizer
subdev nodes, and the ISP source pads connect directly to the capture
video nodes.
This is based on my experience working with the i.MX8MP on the rkisp1
driver, as that hardware had no dual crop (corresponding to the
resizer sink crop) which made it impossible to implement runtime
scaler crop as the image stabilizer (ISP source crop) could not be
changed due to the V4L2 API.
An alternative idea is to leave the media graph as-is and implement
scaler crop in ISP parameters buffer. At the moment scaler crop is
done via V4L2 crop rectangles, which cannot be synchronized with the
other parameters. Thus moving scaling and cropping to parameter
buffers might be a better solution.
Misc notes:
- The features flag isn't really necessary at this stage (since we only
support one ISP version) but I wanted to include it already since as
soon as we add support for another ISP version we will need it. I've
used dual crop as the first feature flag because that is one known
difference between rk3588 and rk3568 afaia.
---
drivers/media/platform/rockchip/Kconfig | 1 +
drivers/media/platform/rockchip/Makefile | 1 +
.../media/platform/rockchip/rkisp2/Kconfig | 19 +
.../media/platform/rockchip/rkisp2/Makefile | 11 +
.../platform/rockchip/rkisp2/rkisp2-capture.c | 1979 ++++++++++
.../platform/rockchip/rkisp2/rkisp2-common.c | 180 +
.../platform/rockchip/rkisp2/rkisp2-common.h | 459 +++
.../platform/rockchip/rkisp2/rkisp2-debug.c | 220 ++
.../platform/rockchip/rkisp2/rkisp2-dev.c | 348 ++
.../platform/rockchip/rkisp2/rkisp2-dmarx.c | 687 ++++
.../platform/rockchip/rkisp2/rkisp2-isp.c | 902 +++++
.../rockchip/rkisp2/rkisp2-regs-v2x.h | 2588 +++++++++++++
.../rockchip/rkisp2/rkisp2-regs-v3x.h | 3383 +++++++++++++++++
.../platform/rockchip/rkisp2/rkisp2-regs.h | 1736 +++++++++
include/uapi/linux/rkisp1-config.h | 1 +
include/uapi/linux/rkisp2-config.h | 20 +
16 files changed, 12535 insertions(+)
create mode 100644 drivers/media/platform/rockchip/rkisp2/Kconfig
create mode 100644 drivers/media/platform/rockchip/rkisp2/Makefile
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-capture.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-common.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-dmarx.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-regs.h
create mode 100644 include/uapi/linux/rkisp2-config.h
diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig
index ba401d32f01b..b008652cf515 100644
--- a/drivers/media/platform/rockchip/Kconfig
+++ b/drivers/media/platform/rockchip/Kconfig
@@ -6,3 +6,4 @@ source "drivers/media/platform/rockchip/rga/Kconfig"
source "drivers/media/platform/rockchip/rkcif/Kconfig"
source "drivers/media/platform/rockchip/rkisp1/Kconfig"
source "drivers/media/platform/rockchip/rkvdec/Kconfig"
+source "drivers/media/platform/rockchip/rkisp2/Kconfig"
diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile
index 0e0b2cbbd4bd..9e2ac1e51c93 100644
--- a/drivers/media/platform/rockchip/Makefile
+++ b/drivers/media/platform/rockchip/Makefile
@@ -3,3 +3,4 @@ obj-y += rga/
obj-y += rkcif/
obj-y += rkisp1/
obj-y += rkvdec/
+obj-y += rkisp2/
diff --git a/drivers/media/platform/rockchip/rkisp2/Kconfig b/drivers/media/platform/rockchip/rkisp2/Kconfig
new file mode 100644
index 000000000000..96a200a9ae7b
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_ROCKCHIP_ISP2
+ tristate "Rockchip Image Signal Processing v2 Unit driver"
+ depends on V4L_PLATFORM_DRIVERS
+ depends on VIDEO_DEV && OF
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select VIDEOBUF2_DMA_CONTIG
+ select VIDEOBUF2_VMALLOC
+ select V4L2_FWNODE
+ select GENERIC_PHY_MIPI_DPHY
+ default n
+ help
+ Enable this to support the Image Signal Processing (ISP) module
+ present in RK3588 SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called rockchip-isp2.
diff --git a/drivers/media/platform/rockchip/rkisp2/Makefile b/drivers/media/platform/rockchip/rkisp2/Makefile
new file mode 100644
index 000000000000..9a9d7b5233c4
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+rockchip-isp2-y := rkisp2-capture.o \
+ rkisp2-common.o \
+ rkisp2-dev.o \
+ rkisp2-dmarx.o \
+ rkisp2-isp.o
+
+rockchip-isp2-$(CONFIG_DEBUG_FS) += rkisp2-debug.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_ISP2) += rockchip-isp2.o
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-capture.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-capture.c
new file mode 100644
index 000000000000..fdae6d3747ff
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-capture.c
@@ -0,0 +1,1979 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - V4L2 capture device
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mc.h>
+#include <media/v4l2-subdev.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "rkisp2-common.h"
+
+#define RKISP2_SP_DEV_NAME RKISP2_DRIVER_NAME "_selfpath"
+#define RKISP2_MP_DEV_NAME RKISP2_DRIVER_NAME "_mainpath"
+
+enum rkisp2_plane {
+ RKISP2_PLANE_Y = 0,
+ RKISP2_PLANE_CB = 1,
+ RKISP2_PLANE_CR = 2
+};
+
+/*
+ * @fourcc: pixel format
+ * @fmt_type: helper filed for pixel format
+ * @uv_swap: if cb cr swapped, for yuv
+ * @write_format: defines how YCbCr self picture data is written to memory
+ * @output_format: defines the output format (RKISP2_CIF_MI_INIT_MP_OUTPUT_* for
+ * the main path and RKISP2_MI_CTRL_SP_OUTPUT_* for the self path)
+ * @mbus: the mbus code associated with the pixel format
+ */
+struct rkisp2_capture_fmt_cfg {
+ u32 fourcc;
+ u32 uv_swap : 1;
+ u32 write_format;
+ u32 output_format;
+ u32 mbus;
+};
+
+struct rkisp2_capture_ops {
+ void (*config)(struct rkisp2_capture *cap);
+ void (*stop)(struct rkisp2_capture *cap);
+ void (*enable)(struct rkisp2_capture *cap);
+ void (*disable)(struct rkisp2_capture *cap);
+ void (*set_data_path)(struct rkisp2_capture *cap);
+ bool (*is_stopped)(struct rkisp2_capture *cap);
+};
+
+struct rkisp2_capture_config {
+ const struct rkisp2_capture_fmt_cfg *fmts;
+ int fmt_size;
+ int max_rsz_width;
+ int max_rsz_height;
+ int min_rsz_width;
+ int min_rsz_height;
+ struct {
+ u32 ctrl;
+ u32 ctrl_shd;
+ u32 update;
+ u32 src_size;
+ u32 dst_size;
+ u32 scale_hy_offs_mi;
+ u32 scale_hc_offs_mi;
+ u32 scale_in_crop_offs;
+ u32 scale_hy_offs;
+ u32 scale_hc_offs;
+ u32 scale_hy_size;
+ u32 scale_hc_size;
+ u32 scale_hy;
+ u32 scale_hcr;
+ u32 scale_hcb;
+ u32 scale_vy;
+ u32 scale_vc;
+ u32 scale_lut;
+ u32 scale_lut_addr;
+ u32 scale_hy_shd;
+ u32 scale_hcr_shd;
+ u32 scale_hcb_shd;
+ u32 scale_vy_shd;
+ u32 scale_vc_shd;
+ u32 phase_hy;
+ u32 phase_hc;
+ u32 phase_vy;
+ u32 phase_vc;
+ u32 phase_hy_shd;
+ u32 phase_hc_shd;
+ u32 phase_vy_shd;
+ u32 phase_vc_shd;
+ } rsz;
+ struct {
+ u32 ctrl;
+ u32 yuvmode_mask;
+ u32 rawmode_mask;
+ u32 h_offset;
+ u32 v_offset;
+ u32 h_size;
+ u32 v_size;
+ } dual_crop;
+ struct {
+ u32 y_size_init;
+ u32 cb_size_init;
+ u32 cr_size_init;
+ u32 y_base_ad_init;
+ u32 cb_base_ad_init;
+ u32 cr_base_ad_init;
+ u32 y_offs_cnt_init;
+ u32 cb_offs_cnt_init;
+ u32 cr_offs_cnt_init;
+ u32 y_base_ad_shd;
+ u32 length;
+ u32 ctrl;
+ u32 y_pic_size;
+ } mi;
+};
+
+/*
+ * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus'
+ * are grouped together. This is assumed and used by the function rkisp2_cap_enum_mbus_codes
+ */
+static const struct rkisp2_capture_fmt_cfg rkisp2_mp_fmts[] = {
+ /* yuv422 */
+ /*
+ * Y and U/V are swapped, and there doesn't seem to be a register that
+ * allows swapping them like the i.MX8MP did, so we only support UYVY
+ * and not YUYV for now.
+ */
+ {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUVINT,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV422P,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV61,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV16M,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV61M,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU422M,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv400 */
+ {
+ .fourcc = V4L2_PIX_FMT_GREY,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV400,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv420 */
+ {
+ .fourcc = V4L2_PIX_FMT_NV21,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = ISP32_MI_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = ISP32_MI_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV21M,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU420,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ },
+};
+
+/*
+ * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus'
+ * are grouped together. This is assumed and used by the function rkisp2_cap_enum_mbus_codes
+ */
+static const struct rkisp2_capture_fmt_cfg rkisp2_sp_fmts[] = {
+ /* yuv422 */
+ {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_INT,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV422P,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV61,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV16M,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV61M,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU422M,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv400 */
+ {
+ .fourcc = V4L2_PIX_FMT_GREY,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* rgb */
+ {
+ .fourcc = V4L2_PIX_FMT_XBGR32,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_RGB888,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB565,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_RGB565,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv420 */
+ {
+ .fourcc = V4L2_PIX_FMT_NV21,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV21M,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .uv_swap = 0,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU420,
+ .uv_swap = 1,
+ .write_format = RKISP2_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP2_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ },
+};
+
+static const struct rkisp2_capture_config rkisp2_capture_config_mp = {
+ .fmts = rkisp2_mp_fmts,
+ .fmt_size = ARRAY_SIZE(rkisp2_mp_fmts),
+ .rsz = {
+ .ctrl = RKISP2_CIF_MRSZ_CTRL,
+ .scale_hy = RKISP2_CIF_MRSZ_SCALE_HY,
+ .scale_hcr = RKISP2_CIF_MRSZ_SCALE_HCR,
+ .scale_hcb = RKISP2_CIF_MRSZ_SCALE_HCB,
+ .scale_vy = RKISP2_CIF_MRSZ_SCALE_VY,
+ .scale_vc = RKISP2_CIF_MRSZ_SCALE_VC,
+ .scale_lut = RKISP2_CIF_MRSZ_SCALE_LUT,
+ .scale_lut_addr = RKISP2_CIF_MRSZ_SCALE_LUT_ADDR,
+ .scale_hy_shd = RKISP2_CIF_MRSZ_SCALE_HY_SHD,
+ .scale_hcr_shd = RKISP2_CIF_MRSZ_SCALE_HCR_SHD,
+ .scale_hcb_shd = RKISP2_CIF_MRSZ_SCALE_HCB_SHD,
+ .scale_vy_shd = RKISP2_CIF_MRSZ_SCALE_VY_SHD,
+ .scale_vc_shd = RKISP2_CIF_MRSZ_SCALE_VC_SHD,
+ .phase_hy = RKISP2_CIF_MRSZ_PHASE_HY,
+ .phase_hc = RKISP2_CIF_MRSZ_PHASE_HC,
+ .phase_vy = RKISP2_CIF_MRSZ_PHASE_VY,
+ .phase_vc = RKISP2_CIF_MRSZ_PHASE_VC,
+ .ctrl_shd = RKISP2_CIF_MRSZ_CTRL_SHD,
+ .phase_hy_shd = RKISP2_CIF_MRSZ_PHASE_HY_SHD,
+ .phase_hc_shd = RKISP2_CIF_MRSZ_PHASE_HC_SHD,
+ .phase_vy_shd = RKISP2_CIF_MRSZ_PHASE_VY_SHD,
+ .phase_vc_shd = RKISP2_CIF_MRSZ_PHASE_VC_SHD,
+ },
+ .dual_crop = {
+ .ctrl = RKISP2_CIF_DUAL_CROP_CTRL,
+ .yuvmode_mask = RKISP2_CIF_DUAL_CROP_MP_MODE_YUV,
+ .rawmode_mask = RKISP2_CIF_DUAL_CROP_MP_MODE_RAW,
+ .h_offset = RKISP2_CIF_DUAL_CROP_M_H_OFFS,
+ .v_offset = RKISP2_CIF_DUAL_CROP_M_V_OFFS,
+ .h_size = RKISP2_CIF_DUAL_CROP_M_H_SIZE,
+ .v_size = RKISP2_CIF_DUAL_CROP_M_V_SIZE,
+ },
+ .mi = {
+ .y_size_init = RKISP2_CIF_MI_MP_Y_SIZE_INIT,
+ .cb_size_init = RKISP2_CIF_MI_MP_CB_SIZE_INIT,
+ .cr_size_init = RKISP2_CIF_MI_MP_CR_SIZE_INIT,
+ .y_base_ad_init = RKISP2_CIF_MI_MP_Y_BASE_AD_INIT,
+ .cb_base_ad_init = RKISP2_CIF_MI_MP_CB_BASE_AD_INIT,
+ .cr_base_ad_init = RKISP2_CIF_MI_MP_CR_BASE_AD_INIT,
+ .y_offs_cnt_init = RKISP2_CIF_MI_MP_Y_OFFS_CNT_INIT,
+ .cb_offs_cnt_init = RKISP2_CIF_MI_MP_CB_OFFS_CNT_INIT,
+ .cr_offs_cnt_init = RKISP2_CIF_MI_MP_CR_OFFS_CNT_INIT,
+ .y_base_ad_shd = RKISP2_CIF_MI_MP_Y_BASE_AD_SHD,
+ .y_pic_size = ISP3X_MI_MP_WR_Y_PIC_SIZE,
+ },
+};
+
+static const struct rkisp2_capture_config rkisp2_capture_config_sp = {
+ .fmts = rkisp2_sp_fmts,
+ .fmt_size = ARRAY_SIZE(rkisp2_sp_fmts),
+ .rsz = {
+ .ctrl = RKISP2_CIF_SRSZ_CTRL,
+ .scale_hy = RKISP2_CIF_SRSZ_SCALE_HY,
+ .scale_hcr = RKISP2_CIF_SRSZ_SCALE_HCR,
+ .scale_hcb = RKISP2_CIF_SRSZ_SCALE_HCB,
+ .scale_vy = RKISP2_CIF_SRSZ_SCALE_VY,
+ .scale_vc = RKISP2_CIF_SRSZ_SCALE_VC,
+ .scale_lut = RKISP2_CIF_SRSZ_SCALE_LUT,
+ .scale_lut_addr = RKISP2_CIF_SRSZ_SCALE_LUT_ADDR,
+ .scale_hy_shd = RKISP2_CIF_SRSZ_SCALE_HY_SHD,
+ .scale_hcr_shd = RKISP2_CIF_SRSZ_SCALE_HCR_SHD,
+ .scale_hcb_shd = RKISP2_CIF_SRSZ_SCALE_HCB_SHD,
+ .scale_vy_shd = RKISP2_CIF_SRSZ_SCALE_VY_SHD,
+ .scale_vc_shd = RKISP2_CIF_SRSZ_SCALE_VC_SHD,
+ .phase_hy = RKISP2_CIF_SRSZ_PHASE_HY,
+ .phase_hc = RKISP2_CIF_SRSZ_PHASE_HC,
+ .phase_vy = RKISP2_CIF_SRSZ_PHASE_VY,
+ .phase_vc = RKISP2_CIF_SRSZ_PHASE_VC,
+ .ctrl_shd = RKISP2_CIF_SRSZ_CTRL_SHD,
+ .phase_hy_shd = RKISP2_CIF_SRSZ_PHASE_HY_SHD,
+ .phase_hc_shd = RKISP2_CIF_SRSZ_PHASE_HC_SHD,
+ .phase_vy_shd = RKISP2_CIF_SRSZ_PHASE_VY_SHD,
+ .phase_vc_shd = RKISP2_CIF_SRSZ_PHASE_VC_SHD,
+ },
+ .dual_crop = {
+ .ctrl = RKISP2_CIF_DUAL_CROP_CTRL,
+ .yuvmode_mask = RKISP2_CIF_DUAL_CROP_SP_MODE_YUV,
+ .rawmode_mask = RKISP2_CIF_DUAL_CROP_SP_MODE_RAW,
+ .h_offset = RKISP2_CIF_DUAL_CROP_S_H_OFFS,
+ .v_offset = RKISP2_CIF_DUAL_CROP_S_V_OFFS,
+ .h_size = RKISP2_CIF_DUAL_CROP_S_H_SIZE,
+ .v_size = RKISP2_CIF_DUAL_CROP_S_V_SIZE,
+ },
+ .mi = {
+ .y_size_init = RKISP2_CIF_MI_SP_Y_SIZE_INIT,
+ .cb_size_init = RKISP2_CIF_MI_SP_CB_SIZE_INIT,
+ .cr_size_init = RKISP2_CIF_MI_SP_CR_SIZE_INIT,
+ .y_base_ad_init = RKISP2_CIF_MI_SP_Y_BASE_AD_INIT,
+ .cb_base_ad_init = RKISP2_CIF_MI_SP_CB_BASE_AD_INIT,
+ .cr_base_ad_init = RKISP2_CIF_MI_SP_CR_BASE_AD_INIT,
+ .y_offs_cnt_init = RKISP2_CIF_MI_SP_Y_OFFS_CNT_INIT,
+ .cb_offs_cnt_init = RKISP2_CIF_MI_SP_CB_OFFS_CNT_INIT,
+ .cr_offs_cnt_init = RKISP2_CIF_MI_SP_CR_OFFS_CNT_INIT,
+ .y_base_ad_shd = RKISP2_CIF_MI_SP_Y_BASE_AD_SHD,
+ .y_pic_size = ISP3X_MI_SP_WR_Y_PIC_SIZE,
+ },
+};
+
+static inline struct rkisp2_vdev_node *
+rkisp2_vdev_to_node(struct video_device *vdev)
+{
+ return container_of(vdev, struct rkisp2_vdev_node, vdev);
+}
+
+int rkisp2_cap_enum_mbus_codes(struct rkisp2_capture *cap,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ const struct rkisp2_capture_fmt_cfg *fmts = cap->config->fmts;
+ /*
+ * initialize curr_mbus to non existing mbus code 0 to ensure it is
+ * different from fmts[0].mbus
+ */
+ u32 curr_mbus = 0;
+ int i, n = 0;
+
+ for (i = 0; i < cap->config->fmt_size; i++) {
+ if (fmts[i].mbus == curr_mbus)
+ continue;
+
+ curr_mbus = fmts[i].mbus;
+ if (n++ == code->index) {
+ code->code = curr_mbus;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+/* ----------------------------------------------------------------------------
+ * Stream operations for self-picture path (sp) and main-picture path (mp)
+ */
+
+static void rkisp2_mi_config_ctrl(struct rkisp2_capture *cap)
+{
+ u32 mi_ctrl = rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL);
+
+ mi_ctrl &= ~GENMASK(17, 16);
+ mi_ctrl |= RKISP2_CIF_MI_CTRL_BURST_LEN_LUM_64;
+
+ mi_ctrl &= ~GENMASK(19, 18);
+ mi_ctrl |= RKISP2_CIF_MI_CTRL_BURST_LEN_CHROM_64;
+
+ mi_ctrl |= RKISP2_CIF_MI_CTRL_INIT_BASE_EN |
+ RKISP2_CIF_MI_CTRL_INIT_OFFSET_EN;
+
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_CTRL, mi_ctrl);
+}
+
+static u32 rkisp2_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm,
+ unsigned int component)
+{
+ /*
+ * If packed format, then plane_fmt[0].sizeimage is the sum of all
+ * components, so we need to calculate just the size of Y component.
+ * See rkisp2_fill_pixfmt().
+ */
+ if (!component && pixm->num_planes == 1)
+ return pixm->plane_fmt[0].bytesperline * pixm->height;
+ return pixm->plane_fmt[component].sizeimage;
+}
+
+static void rkisp2_irq_frame_end_enable(struct rkisp2_capture *cap)
+{
+ u32 mi_imsc = rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_IMSC);
+
+ mi_imsc |= RKISP2_CIF_MI_FRAME(cap);
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_IMSC, mi_imsc);
+}
+
+static void rkisp2_mp_config(struct rkisp2_capture *cap)
+{
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ u32 reg;
+
+ rkisp2_write(rkisp2, cap->config->mi.y_size_init,
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_Y));
+ rkisp2_write(rkisp2, cap->config->mi.cb_size_init,
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CB));
+ rkisp2_write(rkisp2, cap->config->mi.cr_size_init,
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CR));
+
+ rkisp2_write(rkisp2, ISP3X_MI_MP_WR_Y_LLENGTH, cap->stride);
+ rkisp2_write(rkisp2, ISP3X_MI_MP_WR_Y_PIC_WIDTH, pixm->width);
+ rkisp2_write(rkisp2, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, pixm->height);
+ rkisp2_write(rkisp2, ISP3X_MI_MP_WR_Y_PIC_SIZE,
+ cap->stride * pixm->height);
+
+ rkisp2_irq_frame_end_enable(cap);
+
+ /* set uv swapping for semiplanar formats */
+ if (cap->pix.info->comp_planes == 2) {
+ reg = rkisp2_read(rkisp2, ISP3X_MI_WR_XTD_FORMAT_CTRL);
+ if (cap->pix.cfg->uv_swap)
+ reg |= ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
+ else
+ reg &= ~ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
+ rkisp2_write(rkisp2, ISP3X_MI_WR_XTD_FORMAT_CTRL, reg);
+ }
+
+ /*
+ * 2.x and 3.x are both missing the register that allows swapping
+ * bytes, and at least on the rk3588 the bytes are output in UYVY
+ * order. Thus without byte swap, YUYV cannot be achieved.
+ */
+
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_INIT,
+ cap->pix.cfg->output_format);
+
+ u32 mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
+
+ reg = rkisp2_read(rkisp2, ISP3X_MPFBC_CTRL) & ~mask;
+ if (pixm->pixelformat == V4L2_PIX_FMT_NV21 ||
+ pixm->pixelformat == V4L2_PIX_FMT_NV12 ||
+ pixm->pixelformat == V4L2_PIX_FMT_NV21M ||
+ pixm->pixelformat == V4L2_PIX_FMT_NV21M ||
+ pixm->pixelformat == V4L2_PIX_FMT_YVU420)
+ reg |= ISP3X_SEPERATE_YUV_CFG;
+ else
+ reg |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
+ rkisp2_write(rkisp2, ISP3X_MPFBC_CTRL, reg);
+
+ rkisp2_mi_config_ctrl(cap);
+
+ reg = rkisp2_read(rkisp2, RKISP2_CIF_MI_CTRL);
+ reg &= ~RKISP2_MI_CTRL_MP_FMT_MASK;
+ reg |= cap->pix.cfg->write_format | RKISP2_CIF_MI_MP_AUTOUPDATE_ENABLE;
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_CTRL, reg);
+}
+
+static void rkisp2_sp_config(struct rkisp2_capture *cap)
+{
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ u32 mi_ctrl, reg;
+
+ rkisp2_write(rkisp2, cap->config->mi.y_size_init,
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_Y));
+ rkisp2_write(rkisp2, cap->config->mi.cb_size_init,
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CB));
+ rkisp2_write(rkisp2, cap->config->mi.cr_size_init,
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CR));
+
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_SP_Y_LLENGTH, cap->stride);
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_SP_Y_PIC_WIDTH, pixm->width);
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_SP_Y_PIC_HEIGHT, pixm->height);
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_SP_Y_PIC_SIZE, cap->stride * pixm->height);
+
+ rkisp2_irq_frame_end_enable(cap);
+
+ /* set uv swapping for semiplanar formats */
+ if (cap->pix.info->comp_planes == 2) {
+ reg = rkisp2_read(rkisp2, ISP3X_MI_WR_XTD_FORMAT_CTRL);
+ if (cap->pix.cfg->uv_swap)
+ reg |= ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
+ else
+ reg &= ~ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
+ rkisp2_write(rkisp2, ISP3X_MI_WR_XTD_FORMAT_CTRL, reg);
+ }
+
+ /*
+ * 2.x and 3.x are both missing the register that allows swapping
+ * bytes, and at least on the rk3588 the bytes are output in UYVY
+ * order. Thus without byte swap, YUYV cannot be achieved.
+ */
+
+ u32 mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
+
+ reg = rkisp2_read(rkisp2, ISP3X_MPFBC_CTRL) & ~mask;
+ if (pixm->pixelformat == V4L2_PIX_FMT_NV21 ||
+ pixm->pixelformat == V4L2_PIX_FMT_NV12 ||
+ pixm->pixelformat == V4L2_PIX_FMT_NV21M ||
+ pixm->pixelformat == V4L2_PIX_FMT_NV21M ||
+ pixm->pixelformat == V4L2_PIX_FMT_YVU420)
+ reg |= ISP3X_SEPERATE_YUV_CFG;
+ else
+ reg |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
+ rkisp2_write(rkisp2, ISP3X_MPFBC_CTRL, reg);
+
+ rkisp2_mi_config_ctrl(cap);
+
+ mi_ctrl = rkisp2_read(rkisp2, RKISP2_CIF_MI_CTRL);
+ mi_ctrl &= ~RKISP2_MI_CTRL_SP_FMT_MASK;
+ mi_ctrl |= cap->pix.cfg->write_format |
+ RKISP2_MI_CTRL_SP_INPUT_YUV422 |
+ cap->pix.cfg->output_format |
+ RKISP2_CIF_MI_SP_AUTOUPDATE_ENABLE;
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_CTRL, mi_ctrl);
+}
+
+static void rkisp2_mp_disable(struct rkisp2_capture *cap)
+{
+ u32 mi_ctrl = rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL);
+
+ mi_ctrl &= ~(RKISP2_CIF_MI_CTRL_MP_ENABLE |
+ RKISP2_CIF_MI_CTRL_RAW_ENABLE);
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_CTRL, mi_ctrl);
+}
+
+static void rkisp2_sp_disable(struct rkisp2_capture *cap)
+{
+ u32 mi_ctrl = rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL);
+
+ mi_ctrl &= ~RKISP2_CIF_MI_CTRL_SP_ENABLE;
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_CTRL, mi_ctrl);
+}
+
+static void rkisp2_mp_enable(struct rkisp2_capture *cap)
+{
+ u32 mi_ctrl;
+
+ rkisp2_mp_disable(cap);
+
+ mi_ctrl = rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL);
+ if (v4l2_is_format_bayer(cap->pix.info))
+ mi_ctrl |= RKISP2_CIF_MI_CTRL_RAW_ENABLE;
+ /* YUV */
+ else
+ mi_ctrl |= RKISP2_CIF_MI_CTRL_MP_ENABLE;
+
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_CTRL, mi_ctrl);
+}
+
+static void rkisp2_sp_enable(struct rkisp2_capture *cap)
+{
+ u32 mi_ctrl = rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL);
+
+ mi_ctrl |= RKISP2_CIF_MI_CTRL_SP_ENABLE;
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_CTRL, mi_ctrl);
+}
+
+static void rkisp2_mp_sp_stop(struct rkisp2_capture *cap)
+{
+ if (!cap->is_streaming)
+ return;
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_MI_ICR, RKISP2_CIF_MI_FRAME(cap));
+ cap->ops->disable(cap);
+}
+
+static bool rkisp2_mp_is_stopped(struct rkisp2_capture *cap)
+{
+ u32 en = RKISP2_CIF_MI_CTRL_SHD_MP_IN_ENABLED |
+ RKISP2_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
+
+ return !(rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL_SHD) & en);
+}
+
+static bool rkisp2_sp_is_stopped(struct rkisp2_capture *cap)
+{
+ return !(rkisp2_read(cap->rkisp2, RKISP2_CIF_MI_CTRL_SHD) &
+ RKISP2_CIF_MI_CTRL_SHD_SP_IN_ENABLED);
+}
+
+static void rkisp2_mp_set_data_path(struct rkisp2_capture *cap)
+{
+ u32 dpcl = rkisp2_read(cap->rkisp2, RKISP2_CIF_VI_DPCL);
+
+ dpcl = dpcl | RKISP2_CIF_VI_DPCL_CHAN_MODE_MP |
+ RKISP2_CIF_VI_DPCL_MP_MUX_MRSZ_MI;
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_VI_DPCL, dpcl);
+}
+
+static void rkisp2_sp_set_data_path(struct rkisp2_capture *cap)
+{
+ u32 dpcl = rkisp2_read(cap->rkisp2, RKISP2_CIF_VI_DPCL);
+
+ dpcl |= RKISP2_CIF_VI_DPCL_CHAN_MODE_SP;
+ rkisp2_write(cap->rkisp2, RKISP2_CIF_VI_DPCL, dpcl);
+}
+
+static const struct rkisp2_capture_ops rkisp2_capture_ops_mp = {
+ .config = rkisp2_mp_config,
+ .enable = rkisp2_mp_enable,
+ .disable = rkisp2_mp_disable,
+ .stop = rkisp2_mp_sp_stop,
+ .set_data_path = rkisp2_mp_set_data_path,
+ .is_stopped = rkisp2_mp_is_stopped,
+};
+
+static const struct rkisp2_capture_ops rkisp2_capture_ops_sp = {
+ .config = rkisp2_sp_config,
+ .enable = rkisp2_sp_enable,
+ .disable = rkisp2_sp_disable,
+ .stop = rkisp2_mp_sp_stop,
+ .set_data_path = rkisp2_sp_set_data_path,
+ .is_stopped = rkisp2_sp_is_stopped,
+};
+
+/* ----------------------------------------------------------------------------
+ * Frame buffer operations
+ */
+
+static int rkisp2_dummy_buf_create(struct rkisp2_capture *cap)
+{
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ struct rkisp2_dummy_buffer *dummy_buf = &cap->buf.dummy;
+
+ dummy_buf->size = max3(rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_Y),
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CB),
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CR));
+
+ /* The driver never access vaddr, no mapping is required */
+ dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp2->dev,
+ dummy_buf->size,
+ &dummy_buf->dma_addr,
+ GFP_KERNEL,
+ DMA_ATTR_NO_KERNEL_MAPPING);
+ if (!dummy_buf->vaddr)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void rkisp2_dummy_buf_destroy(struct rkisp2_capture *cap)
+{
+ dma_free_attrs(cap->rkisp2->dev,
+ cap->buf.dummy.size, cap->buf.dummy.vaddr,
+ cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING);
+}
+
+static void rkisp2_set_next_buf(struct rkisp2_capture *cap)
+{
+ cap->buf.curr = cap->buf.next;
+ cap->buf.next = NULL;
+
+ if (!list_empty(&cap->buf.queue)) {
+ dma_addr_t *buff_addr;
+
+ cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp2_buffer, queue);
+ list_del(&cap->buf.next->queue);
+
+ buff_addr = cap->buf.next->buff_addr;
+
+ rkisp2_write(cap->rkisp2, cap->config->mi.y_base_ad_init,
+ buff_addr[RKISP2_PLANE_Y]);
+ /*
+ * In order to support grey format we capture
+ * YUV422 planar format from the camera and
+ * set the U and V planes to the dummy buffer
+ */
+ if (cap->pix.cfg->fourcc == V4L2_PIX_FMT_GREY) {
+ rkisp2_write(cap->rkisp2,
+ cap->config->mi.cb_base_ad_init,
+ cap->buf.dummy.dma_addr);
+ } else {
+ rkisp2_write(cap->rkisp2,
+ cap->config->mi.cb_base_ad_init,
+ buff_addr[RKISP2_PLANE_CB]);
+ }
+ } else {
+ /*
+ * Use the dummy space allocated by dma_alloc_coherent to
+ * throw data if there is no available buffer.
+ */
+ rkisp2_write(cap->rkisp2, cap->config->mi.y_base_ad_init,
+ cap->buf.dummy.dma_addr);
+ rkisp2_write(cap->rkisp2, cap->config->mi.cb_base_ad_init,
+ cap->buf.dummy.dma_addr);
+ }
+
+ /* Set plane offsets */
+ rkisp2_write(cap->rkisp2, cap->config->mi.y_offs_cnt_init, 0);
+ rkisp2_write(cap->rkisp2, cap->config->mi.cb_offs_cnt_init, 0);
+ rkisp2_write(cap->rkisp2, cap->config->mi.cr_offs_cnt_init, 0);
+}
+
+/*
+ * This function is called when a frame end comes. The next frame
+ * is processing and we should set up buffer for next-next frame,
+ * otherwise it will overflow.
+ */
+static void rkisp2_handle_buffer(struct rkisp2_capture *cap)
+{
+ struct rkisp2_isp *isp = &cap->rkisp2->isp;
+ struct rkisp2_buffer *curr_buf;
+
+ spin_lock(&cap->buf.lock);
+ curr_buf = cap->buf.curr;
+
+ if (curr_buf) {
+ curr_buf->vb.sequence = isp->frame_sequence;
+ curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns();
+ curr_buf->vb.field = V4L2_FIELD_NONE;
+ vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+ } else {
+ cap->rkisp2->debug.frame_drop[cap->id]++;
+ }
+
+ rkisp2_set_next_buf(cap);
+ spin_unlock(&cap->buf.lock);
+}
+
+irqreturn_t rkisp2_capture_isr(int irq, void *ctx)
+{
+ struct device *dev = ctx;
+ struct rkisp2_device *rkisp2 = dev_get_drvdata(dev);
+ unsigned int i;
+ u32 status;
+
+ if (!rkisp2->irqs_enabled)
+ return IRQ_NONE;
+
+ status = rkisp2_read(rkisp2, RKISP2_CIF_MI_MIS);
+ if (!status)
+ return IRQ_NONE;
+
+ for (i = 0; i < 2; ++i) {
+ struct rkisp2_capture *cap = &rkisp2->capture_devs[i];
+
+ if (!(status & RKISP2_CIF_MI_FRAME(cap)))
+ continue;
+ if (!cap->is_stopping) {
+ rkisp2_handle_buffer(cap);
+ continue;
+ }
+ /*
+ * Make sure stream is actually stopped, whose state
+ * can be read from the shadow register, before
+ * wake_up() thread which would immediately free all
+ * frame buffers. stop() takes effect at the next
+ * frame end that sync the configurations to shadow
+ * regs.
+ */
+ if (!cap->ops->is_stopped(cap)) {
+ cap->ops->stop(cap);
+ continue;
+ }
+ cap->is_stopping = false;
+ cap->is_streaming = false;
+ wake_up(&cap->done);
+ }
+
+ rkisp2_dmarx_isr(rkisp2, status);
+
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_ICR, status);
+
+ return IRQ_HANDLED;
+}
+
+/* ----------------------------------------------------------------------------
+ * Vb2 operations
+ */
+
+static int rkisp2_vb2_queue_setup(struct vb2_queue *queue,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct rkisp2_capture *cap = queue->drv_priv;
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ unsigned int i;
+
+ if (*num_planes) {
+ if (*num_planes != pixm->num_planes)
+ return -EINVAL;
+
+ for (i = 0; i < pixm->num_planes; i++)
+ if (sizes[i] < pixm->plane_fmt[i].sizeimage)
+ return -EINVAL;
+ } else {
+ *num_planes = pixm->num_planes;
+ for (i = 0; i < pixm->num_planes; i++)
+ sizes[i] = pixm->plane_fmt[i].sizeimage;
+ }
+
+ return 0;
+}
+
+static int rkisp2_vb2_buf_init(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_buffer *ispbuf =
+ container_of(vbuf, struct rkisp2_buffer, vb);
+ struct rkisp2_capture *cap = vb->vb2_queue->drv_priv;
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ unsigned int i;
+
+ memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
+ for (i = 0; i < pixm->num_planes; i++)
+ ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+ /* Convert to non-MPLANE */
+ if (pixm->num_planes == 1) {
+ ispbuf->buff_addr[RKISP2_PLANE_CB] =
+ ispbuf->buff_addr[RKISP2_PLANE_Y] +
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_Y);
+ ispbuf->buff_addr[RKISP2_PLANE_CR] =
+ ispbuf->buff_addr[RKISP2_PLANE_CB] +
+ rkisp2_pixfmt_comp_size(pixm, RKISP2_PLANE_CB);
+ }
+
+ /*
+ * uv swap can be supported for planar formats by switching
+ * the address of cb and cr
+ */
+ if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap)
+ swap(ispbuf->buff_addr[RKISP2_PLANE_CR],
+ ispbuf->buff_addr[RKISP2_PLANE_CB]);
+ return 0;
+}
+
+static void rkisp2_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_buffer *ispbuf =
+ container_of(vbuf, struct rkisp2_buffer, vb);
+ struct rkisp2_capture *cap = vb->vb2_queue->drv_priv;
+
+ spin_lock_irq(&cap->buf.lock);
+ list_add_tail(&ispbuf->queue, &cap->buf.queue);
+ spin_unlock_irq(&cap->buf.lock);
+}
+
+static int rkisp2_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ struct rkisp2_capture *cap = vb->vb2_queue->drv_priv;
+ unsigned int i;
+
+ for (i = 0; i < cap->pix.fmt.num_planes; i++) {
+ unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage;
+
+ if (vb2_plane_size(vb, i) < size) {
+ dev_err(cap->rkisp2->dev,
+ "User buffer too small (%ld < %ld)\n",
+ vb2_plane_size(vb, i), size);
+ return -EINVAL;
+ }
+ vb2_set_plane_payload(vb, i, size);
+ }
+
+ return 0;
+}
+
+static void rkisp2_return_all_buffers(struct rkisp2_capture *cap,
+ enum vb2_buffer_state state)
+{
+ struct rkisp2_buffer *buf;
+
+ spin_lock_irq(&cap->buf.lock);
+ if (cap->buf.curr) {
+ vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state);
+ cap->buf.curr = NULL;
+ }
+ if (cap->buf.next) {
+ vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state);
+ cap->buf.next = NULL;
+ }
+ while (!list_empty(&cap->buf.queue)) {
+ buf = list_first_entry(&cap->buf.queue,
+ struct rkisp2_buffer, queue);
+ list_del(&buf->queue);
+ vb2_buffer_done(&buf->vb.vb2_buf, state);
+ }
+ spin_unlock_irq(&cap->buf.lock);
+}
+
+static bool rkisp2_rect_equals(const struct v4l2_rect *a,
+ const struct v4l2_rect *b)
+{
+ return a->left == b->left && a->top == b->top &&
+ a->width == b->width && a->height == b->height;
+}
+
+static void rkisp2_capture_disable_dcrop(struct rkisp2_capture *cap)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ u32 mask = cap->config->dual_crop.yuvmode_mask |
+ cap->config->dual_crop.rawmode_mask;
+ u32 ctrl = rkisp2_read(rkisp2, cap->config->dual_crop.ctrl);
+
+ ctrl &= ~mask;
+ ctrl |= RKISP2_CIF_DUAL_CROP_CFG_UPD;
+ rkisp2_write(rkisp2, cap->config->dual_crop.ctrl, ctrl);
+}
+
+static void rkisp2_capture_config_dcrop(struct rkisp2_capture *cap,
+ const struct v4l2_rect *crop)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ u32 mask = cap->config->dual_crop.yuvmode_mask |
+ cap->config->dual_crop.rawmode_mask;
+ u32 ctrl = rkisp2_read(rkisp2, cap->config->dual_crop.ctrl);
+ bool is_raw = v4l2_is_format_bayer(cap->pix.info);
+
+ rkisp2_write(rkisp2, cap->config->dual_crop.h_offset, crop->left);
+ rkisp2_write(rkisp2, cap->config->dual_crop.v_offset, crop->top);
+ rkisp2_write(rkisp2, cap->config->dual_crop.h_size, crop->width);
+ rkisp2_write(rkisp2, cap->config->dual_crop.v_size, crop->height);
+
+ ctrl &= ~mask;
+ if (is_raw)
+ ctrl |= cap->config->dual_crop.rawmode_mask;
+ else
+ ctrl |= cap->config->dual_crop.yuvmode_mask;
+ ctrl |= RKISP2_CIF_DUAL_CROP_CFG_UPD;
+ rkisp2_write(rkisp2, cap->config->dual_crop.ctrl, ctrl);
+}
+
+static void rkisp2_capture_disable_rsz(struct rkisp2_capture *cap)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+
+ rkisp2_write(rkisp2, cap->config->rsz.ctrl, 0);
+ rkisp2_write(rkisp2, cap->config->rsz.ctrl, RKISP2_CIF_RSZ_CTRL_CFG_UPD);
+}
+
+static int rkisp2_mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs)
+{
+ switch (code) {
+ case MEDIA_BUS_FMT_YUYV8_2X8:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ case MEDIA_BUS_FMT_YVYU8_1X16:
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ case MEDIA_BUS_FMT_VYUY8_1X16:
+ *xsubs = 2;
+ *ysubs = 1;
+ return 0;
+ default:
+ *xsubs = 1;
+ *ysubs = 1;
+ return 0;
+ }
+}
+
+static void rkisp2_format_xysubs(const struct v4l2_format_info *info,
+ u32 *xsubs, u32 *ysubs)
+{
+ if (info && v4l2_is_format_yuv(info)) {
+ *xsubs = info->hdiv ?: 1;
+ *ysubs = info->vdiv ?: 1;
+ } else {
+ *xsubs = 1;
+ *ysubs = 1;
+ }
+}
+
+static u32 rkisp2_scale_up_factor(u32 src, u32 dst)
+{
+ if (src <= 1 || dst <= 1)
+ return RKISP2_CIF_RSZ_SCALER_FACTOR;
+ return ((src - 1) * RKISP2_CIF_RSZ_SCALER_FACTOR) / (dst - 1);
+}
+
+static u32 rkisp2_scale_down_factor(u32 src, u32 dst)
+{
+ if (src <= 1 || dst <= 1)
+ return RKISP2_CIF_RSZ_SCALER_FACTOR;
+ return ((dst - 1) * RKISP2_CIF_RSZ_SCALER_FACTOR) / (src - 1) + 1;
+}
+
+static void rkisp2_capture_prepare_lut(struct rkisp2_capture *cap)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ unsigned int i;
+
+ for (i = 0; i < 64; i++) {
+ rkisp2_write(rkisp2, cap->config->rsz.scale_lut_addr, i);
+ rkisp2_write(rkisp2, cap->config->rsz.scale_lut, i);
+ }
+}
+
+static void rkisp2_capture_config_rsz(struct rkisp2_capture *cap,
+ const struct v4l2_rect *in_rect,
+ const struct v4l2_rect *out_rect,
+ const struct v4l2_mbus_framefmt *src_fmt)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ struct v4l2_rect in_c, out_c;
+ u32 in_xsubs = 1, in_ysubs = 1;
+ u32 out_xsubs = 1, out_ysubs = 1;
+ u32 rsz_ctrl = 0;
+
+ rkisp2_mbus_code_xysubs(src_fmt->code, &in_xsubs, &in_ysubs);
+ rkisp2_format_xysubs(cap->pix.info, &out_xsubs, &out_ysubs);
+
+ in_c.width = DIV_ROUND_UP(in_rect->width, in_xsubs);
+ in_c.height = DIV_ROUND_UP(in_rect->height, in_ysubs);
+ out_c.width = DIV_ROUND_UP(out_rect->width, out_xsubs);
+ out_c.height = DIV_ROUND_UP(out_rect->height, out_ysubs);
+
+ rkisp2_write(rkisp2, cap->config->rsz.phase_hy, 0);
+ rkisp2_write(rkisp2, cap->config->rsz.phase_hc, 0);
+ rkisp2_write(rkisp2, cap->config->rsz.phase_vy, 0);
+ rkisp2_write(rkisp2, cap->config->rsz.phase_vc, 0);
+
+ rkisp2_capture_prepare_lut(cap);
+
+ if (in_rect->width != out_rect->width) {
+ u32 hy;
+
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_HY_ENABLE;
+ if (in_rect->width < out_rect->width) {
+ hy = rkisp2_scale_up_factor(in_rect->width, out_rect->width);
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_HY_UP;
+ } else {
+ hy = rkisp2_scale_down_factor(in_rect->width, out_rect->width);
+ }
+ rkisp2_write(rkisp2, cap->config->rsz.scale_hy, hy);
+ }
+
+ if (in_c.width != out_c.width) {
+ u32 hc;
+
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_HC_ENABLE;
+ if (in_c.width < out_c.width) {
+ hc = rkisp2_scale_up_factor(in_c.width, out_c.width);
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_HC_UP;
+ } else {
+ hc = rkisp2_scale_down_factor(in_c.width, out_c.width);
+ }
+ rkisp2_write(rkisp2, cap->config->rsz.scale_hcb, hc);
+ rkisp2_write(rkisp2, cap->config->rsz.scale_hcr, hc);
+ }
+
+ if (in_rect->height != out_rect->height) {
+ u32 vy;
+
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_VY_ENABLE;
+ if (in_rect->height < out_rect->height) {
+ vy = rkisp2_scale_up_factor(in_rect->height, out_rect->height);
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_VY_UP;
+ } else {
+ vy = rkisp2_scale_down_factor(in_rect->height, out_rect->height);
+ }
+ rkisp2_write(rkisp2, cap->config->rsz.scale_vy, vy);
+ }
+
+ if (in_c.height != out_c.height) {
+ u32 vc;
+
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_VC_ENABLE;
+ if (in_c.height < out_c.height) {
+ vc = rkisp2_scale_up_factor(in_c.height, out_c.height);
+ rsz_ctrl |= RKISP2_CIF_RSZ_CTRL_SCALE_VC_UP;
+ } else {
+ vc = rkisp2_scale_down_factor(in_c.height, out_c.height);
+ }
+ rkisp2_write(rkisp2, cap->config->rsz.scale_vc, vc);
+ }
+
+ rkisp2_write(rkisp2, cap->config->rsz.ctrl,
+ rsz_ctrl | RKISP2_CIF_RSZ_CTRL_CFG_UPD);
+}
+
+static int rkisp2_capture_setup_path(struct rkisp2_capture *cap)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ struct v4l2_subdev *sd = &rkisp2->isp.sd;
+ struct v4l2_subdev_selection sel = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = RKISP2_ISP_PAD_SOURCE_VIDEO,
+ };
+ struct v4l2_subdev_format fmt = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = RKISP2_ISP_PAD_SOURCE_VIDEO,
+ };
+ struct v4l2_rect input = { 0 };
+ struct v4l2_rect crop = { 0 };
+ struct v4l2_rect out = {
+ .left = 0,
+ .top = 0,
+ .width = cap->pix.fmt.width,
+ .height = cap->pix.fmt.height,
+ };
+ int ret;
+
+ ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
+ if (ret == -ENOIOCTLCMD)
+ ret = 0;
+ else if (ret)
+ return ret;
+
+ sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
+ ret = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
+ if (ret == -ENOIOCTLCMD) {
+ input.left = 0;
+ input.top = 0;
+ input.width = fmt.format.width;
+ input.height = fmt.format.height;
+ ret = 0;
+ } else if (ret) {
+ return ret;
+ } else {
+ input = sel.r;
+ }
+
+ sel.target = V4L2_SEL_TGT_CROP;
+ ret = v4l2_subdev_call(sd, pad, get_selection, NULL, &sel);
+ if (ret == -ENOIOCTLCMD) {
+ crop = input;
+ ret = 0;
+ } else if (ret) {
+ return ret;
+ } else {
+ crop = sel.r;
+ }
+
+ if (rkisp2_has_feature(cap->rkisp2, DUAL_CROP)) {
+ if (rkisp2_rect_equals(&crop, &input))
+ rkisp2_capture_disable_dcrop(cap);
+ else
+ rkisp2_capture_config_dcrop(cap, &crop);
+ }
+
+ cap->crop = crop;
+
+ if (!v4l2_is_format_yuv(cap->pix.info)) {
+ if (crop.width != out.width || crop.height != out.height)
+ return -EINVAL;
+ rkisp2_capture_disable_rsz(cap);
+ return 0;
+ }
+
+ if (crop.width == out.width && crop.height == out.height)
+ rkisp2_capture_disable_rsz(cap);
+ else
+ rkisp2_capture_config_rsz(cap, &crop, &out, &fmt.format);
+
+ return 0;
+}
+
+/*
+ * Most registers inside the rockchip ISP2 have shadow register since
+ * they must not be changed while processing a frame.
+ * Usually, each sub-module updates its shadow register after
+ * processing the last pixel of a frame.
+ */
+static void rkisp2_cap_stream_enable(struct rkisp2_capture *cap)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ struct rkisp2_capture *other = &rkisp2->capture_devs[cap->id ^ 1];
+
+ cap->ops->set_data_path(cap);
+ cap->ops->config(cap);
+
+ /* Setup a buffer for the next frame */
+ spin_lock_irq(&cap->buf.lock);
+ rkisp2_set_next_buf(cap);
+ cap->ops->enable(cap);
+
+ /*
+ * It's safe to configure ACTIVE and SHADOW registers for the first
+ * stream. While when the second is starting, do NOT force update
+ * because it also updates the first one.
+ *
+ * The latter case would drop one more buffer(that is 2) since there's
+ * no buffer in a shadow register when the second FE received. This's
+ * also required because the second FE maybe corrupt especially when
+ * run at 120fps.
+ */
+ if (!other->is_streaming) {
+ u32 reg;
+
+ /* Force cfg update. */
+ reg = rkisp2_read(rkisp2, RKISP2_CIF_MI_INIT)
+ & RKISP2_CIF_MI_INIT_MP_OUTPUT_MASK;
+
+ reg |= RKISP2_CIF_MI_INIT_SOFT_UPD;
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_INIT, reg);
+
+ rkisp2_set_next_buf(cap);
+ }
+
+ spin_unlock_irq(&cap->buf.lock);
+ cap->is_streaming = true;
+}
+
+static void rkisp2_cap_stream_disable(struct rkisp2_capture *cap)
+{
+ int ret;
+
+ /* Stream should stop in interrupt. If it doesn't, stop it by force. */
+ cap->is_stopping = true;
+ ret = wait_event_timeout(cap->done,
+ !cap->is_streaming,
+ msecs_to_jiffies(1000));
+ if (!ret) {
+ cap->rkisp2->debug.stop_timeout[cap->id]++;
+ cap->ops->stop(cap);
+ cap->is_stopping = false;
+ cap->is_streaming = false;
+ }
+}
+
+/*
+ * rkisp2_pipeline_stream_disable - disable nodes in the pipeline
+ *
+ * Call s_stream(false) in the reverse order from
+ * rkisp2_pipeline_stream_enable() and disable the DMA engine.
+ * Should be called before video_device_pipeline_stop()
+ */
+static void rkisp2_pipeline_stream_disable(struct rkisp2_capture *cap)
+ __must_hold(&cap->rkisp2->stream_lock)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+
+ rkisp2_cap_stream_disable(cap);
+
+ /*
+ * If the other capture is streaming, isp and sensor nodes shouldn't
+ * be disabled, skip them.
+ */
+ if (rkisp2->pipe.start_count < (rkisp2->source ? 2 : 3))
+ v4l2_subdev_call(&rkisp2->isp.sd, video, s_stream, false);
+
+}
+
+/*
+ * rkisp2_pipeline_stream_enable - enable nodes in the pipeline
+ *
+ * Enable the DMA Engine and call s_stream(true) through the pipeline.
+ * Should be called after video_device_pipeline_start()
+ */
+static int rkisp2_pipeline_stream_enable(struct rkisp2_capture *cap)
+ __must_hold(&cap->rkisp2->stream_lock)
+{
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+ int ret;
+
+ ret = rkisp2_capture_setup_path(cap);
+ if (ret)
+ return ret;
+
+ rkisp2_cap_stream_enable(cap);
+
+ /*
+ * If the other capture is streaming, isp and sensor nodes are already
+ * enabled, skip them.
+ */
+ if (rkisp2->pipe.start_count > 1)
+ return 0;
+
+ ret = v4l2_subdev_call(&rkisp2->isp.sd, video, s_stream, true);
+ if (ret)
+ goto err_disable_cap;
+
+ return 0;
+
+err_disable_cap:
+ rkisp2_cap_stream_disable(cap);
+
+ return ret;
+}
+
+static void rkisp2_vb2_stop_streaming(struct vb2_queue *queue)
+{
+ struct rkisp2_capture *cap = queue->drv_priv;
+ struct rkisp2_vdev_node *node = &cap->vnode;
+ struct rkisp2_device *rkisp2 = cap->rkisp2;
+
+ dev_dbg(cap->rkisp2->dev, "%s, enter\n", __func__);
+
+ mutex_lock(&cap->rkisp2->stream_lock);
+
+ rkisp2_pipeline_stream_disable(cap);
+
+ rkisp2_return_all_buffers(cap, VB2_BUF_STATE_ERROR);
+
+ v4l2_pipeline_pm_put(&node->vdev.entity);
+ pm_runtime_put(rkisp2->dev);
+
+ rkisp2_dummy_buf_destroy(cap);
+
+ video_device_pipeline_stop(&node->vdev);
+
+ mutex_unlock(&cap->rkisp2->stream_lock);
+}
+
+static int
+rkisp2_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
+{
+ struct rkisp2_capture *cap = queue->drv_priv;
+ struct media_entity *entity = &cap->vnode.vdev.entity;
+ int ret;
+
+ mutex_lock(&cap->rkisp2->stream_lock);
+
+ ret = video_device_pipeline_start(&cap->vnode.vdev, &cap->rkisp2->pipe);
+ if (ret) {
+ dev_err(cap->rkisp2->dev, "start pipeline failed %d\n", ret);
+ goto err_ret_buffers;
+ }
+
+ ret = rkisp2_dummy_buf_create(cap);
+ if (ret)
+ goto err_pipeline_stop;
+
+ ret = pm_runtime_resume_and_get(cap->rkisp2->dev);
+ if (ret < 0) {
+ dev_err(cap->rkisp2->dev, "power up failed %d\n", ret);
+ goto err_destroy_dummy;
+ }
+ ret = v4l2_pipeline_pm_get(entity);
+ if (ret) {
+ dev_err(cap->rkisp2->dev, "open cif pipeline failed %d\n", ret);
+ goto err_pipe_pm_put;
+ }
+
+ ret = rkisp2_pipeline_stream_enable(cap);
+ if (ret)
+ goto err_v4l2_pm_put;
+
+ mutex_unlock(&cap->rkisp2->stream_lock);
+
+ return 0;
+
+err_v4l2_pm_put:
+ v4l2_pipeline_pm_put(entity);
+err_pipe_pm_put:
+ pm_runtime_put(cap->rkisp2->dev);
+err_destroy_dummy:
+ rkisp2_dummy_buf_destroy(cap);
+err_pipeline_stop:
+ video_device_pipeline_stop(&cap->vnode.vdev);
+err_ret_buffers:
+ rkisp2_return_all_buffers(cap, VB2_BUF_STATE_QUEUED);
+ mutex_unlock(&cap->rkisp2->stream_lock);
+
+ return ret;
+}
+
+static const struct vb2_ops rkisp2_vb2_ops = {
+ .queue_setup = rkisp2_vb2_queue_setup,
+ .buf_init = rkisp2_vb2_buf_init,
+ .buf_queue = rkisp2_vb2_buf_queue,
+ .buf_prepare = rkisp2_vb2_buf_prepare,
+ .stop_streaming = rkisp2_vb2_stop_streaming,
+ .start_streaming = rkisp2_vb2_start_streaming,
+};
+
+/* ----------------------------------------------------------------------------
+ * IOCTLs operations
+ */
+
+static const struct v4l2_format_info *
+rkisp2_fill_pixfmt(const struct rkisp2_capture *cap,
+ struct v4l2_pix_format_mplane *pixm)
+{
+ struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0];
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ u32 stride;
+
+ memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt));
+ info = v4l2_format_info(pixm->pixelformat);
+ pixm->num_planes = info->mem_planes;
+
+ /*
+ * Clamp the stride to a reasonable value to avoid integer overflows
+ * when calculating the bytesperline and sizeimage values.
+ */
+ stride = clamp(DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]),
+ pixm->width, 65536U);
+
+ plane_y->bytesperline = stride * info->bpp[0];
+ plane_y->sizeimage = plane_y->bytesperline * pixm->height;
+
+ for (i = 1; i < info->comp_planes; i++) {
+ struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i];
+
+ /* bytesperline for other components derive from Y component */
+ plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) *
+ info->bpp[i];
+ plane->sizeimage = plane->bytesperline *
+ DIV_ROUND_UP(pixm->height, info->vdiv);
+ }
+
+ /*
+ * If pixfmt is packed, then plane_fmt[0] should contain the total size
+ * considering all components. plane_fmt[i] for i > 0 should be ignored
+ * by userspace as mem_planes == 1, but we are keeping information there
+ * for convenience.
+ */
+ if (info->mem_planes == 1)
+ for (i = 1; i < info->comp_planes; i++)
+ plane_y->sizeimage += pixm->plane_fmt[i].sizeimage;
+
+ return info;
+}
+
+static const struct rkisp2_capture_fmt_cfg *
+rkisp2_find_fmt_cfg(const struct rkisp2_capture *cap, const u32 pixelfmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < cap->config->fmt_size; i++) {
+ const struct rkisp2_capture_fmt_cfg *fmt = &cap->config->fmts[i];
+
+ if (fmt->fourcc == pixelfmt)
+ return &cap->config->fmts[i];
+ }
+ return NULL;
+}
+
+static void rkisp2_try_fmt(const struct rkisp2_capture *cap,
+ struct v4l2_pix_format_mplane *pixm,
+ const struct rkisp2_capture_fmt_cfg **fmt_cfg,
+ const struct v4l2_format_info **fmt_info)
+{
+ const struct rkisp2_capture_config *config = cap->config;
+ const struct rkisp2_capture_fmt_cfg *fmt;
+ const struct v4l2_format_info *info;
+ static const unsigned int max_widths[] = {
+ RKISP2_RSZ_MP_SRC_MAX_WIDTH, RKISP2_RSZ_SP_SRC_MAX_WIDTH
+ };
+ static const unsigned int max_heights[] = {
+ RKISP2_RSZ_MP_SRC_MAX_HEIGHT, RKISP2_RSZ_SP_SRC_MAX_HEIGHT
+ };
+
+ fmt = rkisp2_find_fmt_cfg(cap, pixm->pixelformat);
+ if (!fmt) {
+ fmt = config->fmts;
+ pixm->pixelformat = fmt->fourcc;
+ }
+
+ pixm->width = clamp_t(u32, pixm->width,
+ RKISP2_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]);
+ pixm->height = clamp_t(u32, pixm->height,
+ RKISP2_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]);
+
+ pixm->field = V4L2_FIELD_NONE;
+ pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
+ pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
+
+ info = rkisp2_fill_pixfmt(cap, pixm);
+
+ if (fmt_cfg)
+ *fmt_cfg = fmt;
+ if (fmt_info)
+ *fmt_info = info;
+}
+
+static void rkisp2_set_fmt(struct rkisp2_capture *cap,
+ struct v4l2_pix_format_mplane *pixm)
+{
+ rkisp2_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info);
+
+ cap->pix.fmt = *pixm;
+ /*
+ * If you're having stride issues implementing this on new hardware,
+ * check here. For example, on rkisp 3.0 this is in bytes, but on rkisp
+ * 1.0 it's in pixels.
+ */
+ cap->stride = pixm->plane_fmt[0].bytesperline;
+}
+
+static int rkisp2_enum_input(struct file *file, void *priv,
+ struct v4l2_input *input)
+{
+ if (input->index > 0)
+ return -EINVAL;
+
+ input->type = V4L2_INPUT_TYPE_CAMERA;
+ strscpy(input->name, "Camera", sizeof(input->name));
+
+ return 0;
+}
+
+static int rkisp2_try_fmt_vid_cap_mplane(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp2_capture *cap = video_drvdata(file);
+
+ rkisp2_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL);
+
+ return 0;
+}
+
+static int rkisp2_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct rkisp2_capture *cap = video_drvdata(file);
+ const struct rkisp2_capture_fmt_cfg *fmt = NULL;
+ unsigned int i, n = 0;
+
+ if (!f->mbus_code) {
+ if (f->index >= cap->config->fmt_size)
+ return -EINVAL;
+
+ fmt = &cap->config->fmts[f->index];
+ f->pixelformat = fmt->fourcc;
+ return 0;
+ }
+
+ for (i = 0; i < cap->config->fmt_size; i++) {
+ fmt = &cap->config->fmts[i];
+
+ if (f->mbus_code && fmt->mbus != f->mbus_code)
+ continue;
+
+ if (n++ == f->index) {
+ f->pixelformat = fmt->fourcc;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int rkisp2_enum_framesizes(struct file *file, void *fh,
+ struct v4l2_frmsizeenum *fsize)
+{
+ static const unsigned int max_widths[] = {
+ RKISP2_RSZ_MP_SRC_MAX_WIDTH,
+ RKISP2_RSZ_SP_SRC_MAX_WIDTH,
+ };
+ static const unsigned int max_heights[] = {
+ RKISP2_RSZ_MP_SRC_MAX_HEIGHT,
+ RKISP2_RSZ_SP_SRC_MAX_HEIGHT,
+ };
+ struct rkisp2_capture *cap = video_drvdata(file);
+
+ if (fsize->index != 0)
+ return -EINVAL;
+
+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
+
+ fsize->stepwise.min_width = RKISP2_RSZ_SRC_MIN_WIDTH;
+ fsize->stepwise.max_width = max_widths[cap->id];
+ fsize->stepwise.step_width = 2;
+
+ fsize->stepwise.min_height = RKISP2_RSZ_SRC_MIN_HEIGHT;
+ fsize->stepwise.max_height = max_heights[cap->id];
+ fsize->stepwise.step_height = 2;
+
+ return 0;
+}
+
+static int rkisp2_s_fmt_vid_cap_mplane(struct file *file,
+ void *priv, struct v4l2_format *f)
+{
+ struct rkisp2_capture *cap = video_drvdata(file);
+ struct rkisp2_vdev_node *node =
+ rkisp2_vdev_to_node(&cap->vnode.vdev);
+
+ if (vb2_is_busy(&node->buf_queue))
+ return -EBUSY;
+
+ rkisp2_set_fmt(cap, &f->fmt.pix_mp);
+
+ return 0;
+}
+
+static int rkisp2_g_fmt_vid_cap_mplane(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp2_capture *cap = video_drvdata(file);
+
+ f->fmt.pix_mp = cap->pix.fmt;
+
+ return 0;
+}
+
+static int rkisp2_g_selection(struct file *file, void *prv,
+ struct v4l2_selection *sel)
+{
+ struct rkisp2_capture *cap = video_drvdata(file);
+ struct v4l2_subdev *sd = &cap->rkisp2->isp.sd;
+ struct v4l2_subdev_selection sd_sel = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = RKISP2_ISP_PAD_SOURCE_VIDEO,
+ .target = sel->target,
+ };
+ int ret;
+
+ if (!V4L2_TYPE_IS_CAPTURE(sel->type))
+ return -EINVAL;
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ ret = v4l2_subdev_call(sd, pad, get_selection, NULL, &sd_sel);
+ if (ret)
+ return ret;
+ sel->r = sd_sel.r;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rkisp2_s_selection(struct file *file, void *prv,
+ struct v4l2_selection *sel)
+{
+ struct rkisp2_capture *cap = video_drvdata(file);
+ struct v4l2_subdev *sd = &cap->rkisp2->isp.sd;
+ struct v4l2_subdev_selection sd_sel = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = RKISP2_ISP_PAD_SOURCE_VIDEO,
+ .target = V4L2_SEL_TGT_CROP,
+ };
+ int ret;
+
+ if (!V4L2_TYPE_IS_CAPTURE(sel->type) || sel->target != V4L2_SEL_TGT_CROP)
+ return -EINVAL;
+
+ if (sel->flags)
+ return -EINVAL;
+
+ sd_sel.r = sel->r;
+
+ ret = v4l2_subdev_call(sd, pad, set_selection, NULL, &sd_sel);
+ if (ret)
+ return ret;
+
+ sel->r = sd_sel.r;
+
+ return 0;
+}
+
+static int
+rkisp2_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
+{
+ strscpy(cap->driver, RKISP2_DRIVER_NAME, sizeof(cap->driver));
+ strscpy(cap->card, RKISP2_DRIVER_NAME, sizeof(cap->card));
+ strscpy(cap->bus_info, RKISP2_BUS_INFO, sizeof(cap->bus_info));
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops rkisp2_v4l2_ioctl_ops = {
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_enum_input = rkisp2_enum_input,
+ .vidioc_try_fmt_vid_cap_mplane = rkisp2_try_fmt_vid_cap_mplane,
+ .vidioc_s_fmt_vid_cap_mplane = rkisp2_s_fmt_vid_cap_mplane,
+ .vidioc_g_fmt_vid_cap_mplane = rkisp2_g_fmt_vid_cap_mplane,
+ .vidioc_enum_fmt_vid_cap = rkisp2_enum_fmt_vid_cap_mplane,
+ .vidioc_enum_framesizes = rkisp2_enum_framesizes,
+ .vidioc_s_selection = rkisp2_s_selection,
+ .vidioc_g_selection = rkisp2_g_selection,
+ .vidioc_querycap = rkisp2_querycap,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static int rkisp2_capture_link_validate(struct media_link *link)
+{
+ struct video_device *vdev =
+ media_entity_to_video_device(link->sink->entity);
+ struct v4l2_subdev *sd =
+ media_entity_to_v4l2_subdev(link->source->entity);
+ struct rkisp2_capture *cap = video_get_drvdata(vdev);
+ const struct rkisp2_capture_fmt_cfg *fmt =
+ rkisp2_find_fmt_cfg(cap, cap->pix.fmt.pixelformat);
+ struct v4l2_subdev_format sd_fmt = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = link->source->index,
+ };
+ int ret;
+
+ ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt);
+ if (ret)
+ return ret;
+
+ if (sd_fmt.format.code != fmt->mbus) {
+ dev_dbg(cap->rkisp2->dev,
+ "link '%s':%u -> '%s':%u not valid: 0x%04x/%ux%u != 0x%04x/%ux%u\n",
+ link->source->entity->name, link->source->index,
+ link->sink->entity->name, link->sink->index,
+ sd_fmt.format.code, sd_fmt.format.width,
+ sd_fmt.format.height, fmt->mbus, cap->pix.fmt.width,
+ cap->pix.fmt.height);
+ return -EPIPE;
+ }
+
+ return 0;
+}
+
+/* ----------------------------------------------------------------------------
+ * core functions
+ */
+
+static const struct media_entity_operations rkisp2_media_ops = {
+ .link_validate = rkisp2_capture_link_validate,
+};
+
+static const struct v4l2_file_operations rkisp2_fops = {
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vb2_fop_poll,
+ .mmap = vb2_fop_mmap,
+};
+
+static void rkisp2_unregister_capture(struct rkisp2_capture *cap)
+{
+ if (!video_is_registered(&cap->vnode.vdev))
+ return;
+
+ media_entity_cleanup(&cap->vnode.vdev.entity);
+ vb2_video_unregister_device(&cap->vnode.vdev);
+ mutex_destroy(&cap->vnode.vlock);
+}
+
+void rkisp2_capture_devs_unregister(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_capture *mp = &rkisp2->capture_devs[RKISP2_MAINPATH];
+ struct rkisp2_capture *sp = &rkisp2->capture_devs[RKISP2_SELFPATH];
+
+ rkisp2_unregister_capture(mp);
+ rkisp2_unregister_capture(sp);
+}
+
+static int rkisp2_register_capture(struct rkisp2_capture *cap)
+{
+ static const char * const dev_names[] = {
+ RKISP2_MP_DEV_NAME, RKISP2_SP_DEV_NAME
+ };
+ struct v4l2_device *v4l2_dev = &cap->rkisp2->v4l2_dev;
+ struct video_device *vdev = &cap->vnode.vdev;
+ struct rkisp2_vdev_node *node;
+ struct vb2_queue *q;
+ int ret;
+
+ strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name));
+ node = rkisp2_vdev_to_node(vdev);
+ mutex_init(&node->vlock);
+
+ vdev->ioctl_ops = &rkisp2_v4l2_ioctl_ops;
+ vdev->release = video_device_release_empty;
+ vdev->fops = &rkisp2_fops;
+ vdev->minor = -1;
+ vdev->v4l2_dev = v4l2_dev;
+ vdev->lock = &node->vlock;
+ vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
+ V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
+ vdev->entity.ops = &rkisp2_media_ops;
+ video_set_drvdata(vdev, cap);
+ vdev->vfl_dir = VFL_DIR_RX;
+ node->pad.flags = MEDIA_PAD_FL_SINK;
+
+ q = &node->buf_queue;
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->drv_priv = cap;
+ q->ops = &rkisp2_vb2_ops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->gfp_flags = GFP_DMA32;
+ q->buf_struct_size = sizeof(struct rkisp2_buffer);
+ q->min_queued_buffers = 1;
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->vlock;
+ q->dev = cap->rkisp2->dev;
+ ret = vb2_queue_init(q);
+ if (ret) {
+ dev_err(cap->rkisp2->dev,
+ "vb2 queue init failed (err=%d)\n", ret);
+ goto error;
+ }
+
+ vdev->queue = q;
+
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret)
+ goto error;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(cap->rkisp2->dev,
+ "failed to register %s, ret=%d\n", vdev->name, ret);
+ goto error;
+ }
+
+ v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name,
+ vdev->num);
+
+ return 0;
+
+error:
+ media_entity_cleanup(&vdev->entity);
+ mutex_destroy(&node->vlock);
+ return ret;
+}
+
+static void
+rkisp2_capture_init(struct rkisp2_device *rkisp2, enum rkisp2_stream_id id)
+{
+ struct rkisp2_capture *cap = &rkisp2->capture_devs[id];
+ struct v4l2_pix_format_mplane pixm;
+
+ memset(cap, 0, sizeof(*cap));
+ cap->id = id;
+ cap->rkisp2 = rkisp2;
+
+ INIT_LIST_HEAD(&cap->buf.queue);
+ init_waitqueue_head(&cap->done);
+ spin_lock_init(&cap->buf.lock);
+ if (cap->id == RKISP2_SELFPATH) {
+ cap->ops = &rkisp2_capture_ops_sp;
+ cap->config = &rkisp2_capture_config_sp;
+ } else {
+ cap->ops = &rkisp2_capture_ops_mp;
+ cap->config = &rkisp2_capture_config_mp;
+ }
+
+ cap->is_streaming = false;
+
+ memset(&pixm, 0, sizeof(pixm));
+ pixm.pixelformat = V4L2_PIX_FMT_YUYV;
+ pixm.width = RKISP2_DEFAULT_WIDTH;
+ pixm.height = RKISP2_DEFAULT_HEIGHT;
+ rkisp2_set_fmt(cap, &pixm);
+ cap->crop.left = 0;
+ cap->crop.top = 0;
+ cap->crop.width = pixm.width;
+ cap->crop.height = pixm.height;
+}
+
+int rkisp2_capture_devs_register(struct rkisp2_device *rkisp2)
+{
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < 2; i++) {
+ struct rkisp2_capture *cap = &rkisp2->capture_devs[i];
+
+ rkisp2_capture_init(rkisp2, i);
+
+ ret = rkisp2_register_capture(cap);
+ if (ret) {
+ rkisp2_capture_devs_unregister(rkisp2);
+ return ret;
+ }
+ }
+
+ return 0;
+
+}
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-common.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.c
new file mode 100644
index 000000000000..c09438c8b7b0
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - Common definitions
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ */
+
+#include <media/mipi-csi2.h>
+#include <media/v4l2-rect.h>
+
+#include "rkisp2-common.h"
+
+static const struct rkisp2_mbus_info rkisp2_formats[] = {
+ {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .direction = RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW10,
+ .bayer_pat = RKISP2_RAW_RGGB,
+ .bus_width = 10,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW10,
+ .bayer_pat = RKISP2_RAW_BGGR,
+ .bus_width = 10,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW10,
+ .bayer_pat = RKISP2_RAW_GBRG,
+ .bus_width = 10,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW10,
+ .bayer_pat = RKISP2_RAW_GRBG,
+ .bus_width = 10,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW12,
+ .bayer_pat = RKISP2_RAW_RGGB,
+ .bus_width = 12,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW12,
+ .bayer_pat = RKISP2_RAW_BGGR,
+ .bus_width = 12,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW12,
+ .bayer_pat = RKISP2_RAW_GBRG,
+ .bus_width = 12,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW12,
+ .bayer_pat = RKISP2_RAW_GRBG,
+ .bus_width = 12,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW8,
+ .bayer_pat = RKISP2_RAW_RGGB,
+ .bus_width = 8,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW8,
+ .bayer_pat = RKISP2_RAW_BGGR,
+ .bus_width = 8,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW8,
+ .bayer_pat = RKISP2_RAW_GBRG,
+ .bus_width = 8,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = MIPI_CSI2_DT_RAW8,
+ .bayer_pat = RKISP2_RAW_GRBG,
+ .bus_width = 8,
+ .direction = RKISP2_ISP_SD_SINK | RKISP2_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = MIPI_CSI2_DT_YUV422_8B,
+ .yuv_seq = RKISP2_CIF_ISP_ACQ_PROP_YCBYCR,
+ .bus_width = 16,
+ .direction = RKISP2_ISP_SD_SINK,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = MIPI_CSI2_DT_YUV422_8B,
+ .yuv_seq = RKISP2_CIF_ISP_ACQ_PROP_YCRYCB,
+ .bus_width = 16,
+ .direction = RKISP2_ISP_SD_SINK,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = MIPI_CSI2_DT_YUV422_8B,
+ .yuv_seq = RKISP2_CIF_ISP_ACQ_PROP_CBYCRY,
+ .bus_width = 16,
+ .direction = RKISP2_ISP_SD_SINK,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = MIPI_CSI2_DT_YUV422_8B,
+ .yuv_seq = RKISP2_CIF_ISP_ACQ_PROP_CRYCBY,
+ .bus_width = 16,
+ .direction = RKISP2_ISP_SD_SINK,
+ },
+};
+
+const struct rkisp2_mbus_info *rkisp2_mbus_info_get_by_index(unsigned int index)
+{
+ if (index >= ARRAY_SIZE(rkisp2_formats))
+ return NULL;
+
+ return &rkisp2_formats[index];
+}
+
+const struct rkisp2_mbus_info *rkisp2_mbus_info_get_by_code(u32 mbus_code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rkisp2_formats); i++) {
+ const struct rkisp2_mbus_info *fmt = &rkisp2_formats[i];
+
+ if (fmt->mbus_code == mbus_code)
+ return fmt;
+ }
+
+ return NULL;
+}
+
+static const struct v4l2_rect rkisp2_sd_min_crop = {
+ .width = RKISP2_ISP_MIN_WIDTH,
+ .height = RKISP2_ISP_MIN_HEIGHT,
+ .top = 0,
+ .left = 0,
+};
+
+void rkisp2_sd_adjust_crop_rect(struct v4l2_rect *crop,
+ const struct v4l2_rect *bounds)
+{
+ v4l2_rect_set_min_size(crop, &rkisp2_sd_min_crop);
+ v4l2_rect_map_inside(crop, bounds);
+}
+
+void rkisp2_sd_adjust_crop(struct v4l2_rect *crop,
+ const struct v4l2_mbus_framefmt *bounds)
+{
+ struct v4l2_rect crop_bounds = {
+ .left = 0,
+ .top = 0,
+ .width = bounds->width,
+ .height = bounds->height,
+ };
+
+ rkisp2_sd_adjust_crop_rect(crop, &crop_bounds);
+}
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
new file mode 100644
index 000000000000..e08adfec2c50
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
@@ -0,0 +1,459 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
+/*
+ * Rockchip ISP2 Driver - Common definitions
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ *
+ * Based on Rockchip ISP2 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _RKISP2_COMMON_H
+#define _RKISP2_COMMON_H
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/rkisp2-config.h>
+#include <media/media-device.h>
+#include <media/media-entity.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "rkisp2-regs.h"
+
+struct dentry;
+struct regmap;
+
+/*
+ * flags on the 'direction' field in struct rkisp2_mbus_info' that indicate
+ * on which pad the media bus format is supported
+ */
+#define RKISP2_ISP_SD_SRC BIT(0)
+#define RKISP2_ISP_SD_SINK BIT(1)
+
+/*
+ * Minimum values for the width and height of entities. The maximum values are
+ * model-specific and stored in the rkisp2_info structure.
+ */
+#define RKISP2_ISP_MIN_WIDTH 32
+#define RKISP2_ISP_MIN_HEIGHT 32
+
+#define RKISP2_RSZ_MP_SRC_MAX_WIDTH 4416
+#define RKISP2_RSZ_MP_SRC_MAX_HEIGHT 3312
+#define RKISP2_RSZ_SP_SRC_MAX_WIDTH 1920
+#define RKISP2_RSZ_SP_SRC_MAX_HEIGHT 1920
+#define RKISP2_RSZ_SRC_MIN_WIDTH 32
+#define RKISP2_RSZ_SRC_MIN_HEIGHT 16
+
+/* the default width and height of all the entities */
+#define RKISP2_DEFAULT_WIDTH 800
+#define RKISP2_DEFAULT_HEIGHT 600
+
+#define RKISP2_DRIVER_NAME "rkisp2"
+#define RKISP2_BUS_INFO "platform:" RKISP2_DRIVER_NAME
+
+/* maximum number of clocks */
+#define RKISP2_MAX_BUS_CLK 8
+
+/* IRQ lines */
+enum rkisp2_irq_line {
+ RKISP2_IRQ_ISP = 0,
+ RKISP2_IRQ_MI,
+ RKISP2_IRQ_MIPI,
+ RKISP2_NUM_IRQS,
+};
+
+/* enum for the resizer pads */
+/* enum for the csi receiver pads */
+/* enum for the capture id */
+enum rkisp2_stream_id {
+ RKISP2_MAINPATH,
+ RKISP2_SELFPATH,
+ RKISP2_MAINPATH_FBC = 31,
+};
+
+/* bayer patterns */
+enum rkisp2_fmt_raw_pat_type {
+ RKISP2_RAW_RGGB = 0,
+ RKISP2_RAW_GRBG,
+ RKISP2_RAW_GBRG,
+ RKISP2_RAW_BGGR,
+};
+
+/* enum for the isp pads */
+enum rkisp2_isp_pad {
+ RKISP2_ISP_PAD_SINK_VIDEO,
+ RKISP2_ISP_PAD_SOURCE_VIDEO,
+ RKISP2_ISP_PAD_MAX
+};
+
+/*
+ * enum rkisp2_feature - ISP features
+ *
+ * @RKISP2_FEATURE_DUAL_CROP: The ISP has the dual crop block at the resizer input
+ *
+ * The ISP features are stored in a bitmask in &rkisp2_info.features and allow
+ * the driver to implement support for features present in some ISP versions
+ * only.
+ */
+enum rkisp2_feature {
+ RKISP2_FEATURE_DUAL_CROP = BIT(0),
+};
+
+#define rkisp2_has_feature(rkisp2, feature) \
+ ((rkisp2)->info->features & RKISP2_FEATURE_##feature)
+
+/*
+ * struct rkisp2_info - Model-specific ISP Information
+ *
+ * @clks: array of ISP clock names
+ * @clk_size: number of entries in the @clks array
+ * @isrs: array of ISP interrupt descriptors
+ * @isr_size: number of entries in the @isrs array
+ * @isp_ver: ISP version
+ * @features: bitmask of rkisp2_feature features implemented by the ISP
+ * @max_width: maximum input frame width
+ * @max_height: maximum input frame height
+ *
+ * This structure contains information about the ISP specific to a particular
+ * ISP model, version, or integration in a particular SoC.
+ */
+struct rkisp2_info {
+ const char * const *clks;
+ unsigned int clk_size;
+ const struct rkisp2_isr_data *isrs;
+ unsigned int isr_size;
+ enum rkisp2_isp_version isp_ver;
+ unsigned int features;
+ unsigned int max_width;
+ unsigned int max_height;
+};
+
+/*
+ * struct rkisp2_isp - ISP subdev entity
+ *
+ * @sd: v4l2_subdev variable
+ * @rkisp2: pointer to rkisp2_device
+ * @pads: media pads
+ * @sink_fmt: input format
+ * @frame_sequence: used to synchronize frame_id between video devices.
+ * @dphy_errctrl_disabled: flag to re-enable DPHY errctrl interrupt after error
+ */
+struct rkisp2_isp {
+ struct v4l2_subdev sd;
+ struct rkisp2_device *rkisp2;
+ struct media_pad pads[RKISP2_ISP_PAD_MAX];
+ const struct rkisp2_mbus_info *sink_fmt;
+ __u32 frame_sequence;
+ bool dphy_errctrl_disabled;
+};
+
+/*
+ * struct rkisp2_vdev_node - Container for the video nodes: params, stats, mainpath, selfpath
+ *
+ * @buf_queue: queue of buffers
+ * @vlock: lock of the video node
+ * @vdev: video node
+ * @pad: media pad
+ */
+struct rkisp2_vdev_node {
+ struct vb2_queue buf_queue;
+ struct mutex vlock; /* ioctl serialization mutex */
+ struct video_device vdev;
+ struct media_pad pad;
+};
+
+/*
+ * struct rkisp2_buffer - A container for the vb2 buffers used by the video devices:
+ * stats, mainpath, selfpath
+ *
+ * @vb: vb2 buffer
+ * @queue: entry of the buffer in the queue
+ * @buff_addr: dma addresses of each plane, used only by the capture devices: selfpath, mainpath
+ */
+struct rkisp2_buffer {
+ struct vb2_v4l2_buffer vb;
+ struct list_head queue;
+ dma_addr_t buff_addr[VIDEO_MAX_PLANES];
+};
+
+/*
+ * struct rkisp2_dummy_buffer - A buffer to write the next frame to in case
+ * there are no vb2 buffers available.
+ *
+ * @vaddr: return value of call to dma_alloc_attrs.
+ * @dma_addr: dma address of the buffer.
+ * @size: size of the buffer.
+ */
+struct rkisp2_dummy_buffer {
+ void *vaddr;
+ dma_addr_t dma_addr;
+ u32 size;
+};
+
+struct rkisp2_device;
+
+struct rkisp2_dmarx_fmt {
+ u32 fourcc;
+ u8 bpp;
+};
+
+enum rkisp2_rawrd_id {
+ RKISP2_RAWRD0,
+ RKISP2_RAWRD1,
+ RKISP2_RAWRD2,
+ RKISP2_RAWRD_MAX,
+};
+
+struct rkisp2_rawrd_cfg {
+ const char *name;
+ u32 ready_mask;
+ u32 base_reg;
+ u32 length_reg;
+ u32 enable_mask;
+ u8 channel_sel;
+};
+
+struct rkisp2_dmarx_chan {
+ struct rkisp2_device *rkisp2;
+ struct rkisp2_vdev_node vnode;
+ spinlock_t buf_lock;
+ struct list_head buf_queue;
+ struct rkisp2_buffer *curr_buf;
+ const struct rkisp2_dmarx_fmt *fmts;
+ unsigned int fmt_cnt;
+ const struct rkisp2_dmarx_fmt *fmt;
+ struct v4l2_pix_format_mplane pix;
+ const struct rkisp2_rawrd_cfg *cfg;
+ enum rkisp2_rawrd_id id;
+ bool streaming;
+};
+
+struct rkisp2_dmarx {
+ struct rkisp2_dmarx_chan chan[RKISP2_RAWRD_MAX];
+ unsigned int num_chans;
+};
+
+/*
+ * struct rkisp2_capture - ISP capture video device
+ *
+ * @vnode: video node
+ * @rkisp2: pointer to rkisp2_device
+ * @id: id of the capture, one of RKISP2_SELFPATH, RKISP2_MAINPATH
+ * @ops: list of callbacks to configure the capture device.
+ * @config: a pointer to the list of registers to configure the capture format.
+ * @is_streaming: device is streaming
+ * @is_stopping: stop_streaming callback was called and the device is in the process of
+ * stopping the streaming.
+ * @done: when stop_streaming callback is called, the device waits for the next irq
+ * handler to stop the streaming by waiting on the 'done' wait queue.
+ * If the irq handler is not called, the stream is stopped by the callback
+ * after timeout.
+ * @stride: the line stride for the first plane, in pixel units
+ * @buf.lock: lock to protect buf.queue
+ * @buf.queue: queued buffer list
+ * @buf.dummy: dummy space to store dropped data
+ *
+ * rkisp2 uses shadow registers, so it needs two buffers at a time
+ * @buf.curr: the buffer used for current frame
+ * @buf.next: the buffer used for next frame
+ * @pix.cfg: pixel configuration
+ * @pix.info: a pointer to the v4l2_format_info of the pixel format
+ * @pix.fmt: buffer format
+ */
+struct rkisp2_capture {
+ struct rkisp2_vdev_node vnode;
+ struct rkisp2_device *rkisp2;
+ enum rkisp2_stream_id id;
+ const struct rkisp2_capture_ops *ops;
+ const struct rkisp2_capture_config *config;
+ bool is_streaming;
+ bool is_stopping;
+ wait_queue_head_t done;
+ unsigned int stride;
+ struct {
+ /* protects queue, curr and next */
+ spinlock_t lock;
+ struct list_head queue;
+ struct rkisp2_dummy_buffer dummy;
+ struct rkisp2_buffer *curr;
+ struct rkisp2_buffer *next;
+ } buf;
+ struct {
+ const struct rkisp2_capture_fmt_cfg *cfg;
+ const struct v4l2_format_info *info;
+ struct v4l2_pix_format_mplane fmt;
+ } pix;
+ struct v4l2_rect crop;
+};
+
+struct rkisp2_debug {
+ struct dentry *debugfs_dir;
+ unsigned long data_loss;
+ unsigned long outform_size_error;
+ unsigned long img_stabilization_size_error;
+ unsigned long inform_size_error;
+ unsigned long irq_delay;
+ unsigned long mipi_error;
+ unsigned long stats_error;
+ unsigned long stop_timeout[2];
+ unsigned long frame_drop[2];
+ unsigned long complete_frames;
+};
+
+/*
+ * struct rkisp2_device - ISP platform device
+ *
+ * @base_addr: base register address
+ * @dev: a pointer to the struct device
+ * @clk_size: number of clocks
+ * @clks: array of clocks
+ * @gasket: the gasket - i.MX8MP only
+ * @gasket_id: the gasket ID (0 or 1) - i.MX8MP only
+ * @v4l2_dev: v4l2_device variable
+ * @media_dev: media_device variable
+ * @notifier: a notifier to register on the v4l2-async API to be notified on the sensor
+ * @source: source subdev in-use, set when starting streaming
+ * @csi: internal CSI-2 receiver
+ * @isp: ISP sub-device
+ * @resizer_devs: resizer sub-devices
+ * @capture_devs: capture devices
+ * @dmarx: ISP memory read device
+ * @pipe: media pipeline
+ * @stream_lock: serializes {start/stop}_streaming callbacks between the capture devices.
+ * @debug: debug params to be exposed on debugfs
+ * @info: version-specific ISP information
+ * @irqs: IRQ line numbers
+ * @irqs_enabled: the hardware is enabled and can cause interrupts
+ */
+struct rkisp2_device {
+ void __iomem *base_addr;
+ struct device *dev;
+ unsigned int clk_size;
+ struct clk_bulk_data clks[RKISP2_MAX_BUS_CLK];
+ struct regmap *gasket;
+ unsigned int gasket_id;
+ struct v4l2_device v4l2_dev;
+ struct media_device media_dev;
+ struct v4l2_async_notifier notifier;
+ struct v4l2_subdev *source;
+ struct rkisp2_isp isp;
+ struct rkisp2_capture capture_devs[2];
+ struct rkisp2_dmarx dmarx;
+ struct media_pipeline pipe;
+ struct mutex stream_lock; /* serialize {start/stop}_streaming cb between capture devices */
+ struct rkisp2_debug debug;
+ const struct rkisp2_info *info;
+ int irqs[RKISP2_NUM_IRQS];
+ bool irqs_enabled;
+};
+
+/*
+ * struct rkisp2_mbus_info - ISP media bus info, Translates media bus code to hardware
+ * format values
+ *
+ * @mbus_code: media bus code
+ * @pixel_enc: pixel encoding
+ * @mipi_dt: mipi data type
+ * @yuv_seq: the order of the Y, Cb, Cr values
+ * @bus_width: bus width
+ * @bayer_pat: bayer pattern
+ * @direction: a bitmask of the flags indicating on which pad the format is supported on
+ */
+struct rkisp2_mbus_info {
+ u32 mbus_code;
+ enum v4l2_pixel_encoding pixel_enc;
+ u32 mipi_dt;
+ u32 yuv_seq;
+ u8 bus_width;
+ enum rkisp2_fmt_raw_pat_type bayer_pat;
+ unsigned int direction;
+};
+
+static inline void
+rkisp2_write(struct rkisp2_device *rkisp2, unsigned int addr, u32 val)
+{
+ writel(val, rkisp2->base_addr + addr);
+}
+
+static inline u32 rkisp2_read(struct rkisp2_device *rkisp2, unsigned int addr)
+{
+ return readl(rkisp2->base_addr + addr);
+}
+
+/*
+ * rkisp2_cap_enum_mbus_codes - A helper function that return the i'th supported mbus code
+ * of the capture entity. This is used to enumerate the supported
+ * mbus codes on the source pad of the resizer.
+ *
+ * @cap: the capture entity
+ * @code: the mbus code, the function reads the code->index and fills the code->code
+ */
+int rkisp2_cap_enum_mbus_codes(struct rkisp2_capture *cap,
+ struct v4l2_subdev_mbus_code_enum *code);
+
+/*
+ * rkisp2_mbus_info_get_by_index - Retrieve the ith supported mbus info
+ *
+ * @index: index of the mbus info to fetch
+ */
+const struct rkisp2_mbus_info *rkisp2_mbus_info_get_by_index(unsigned int index);
+
+/*
+ * rkisp2_sd_adjust_crop_rect - adjust a rectangle to fit into another rectangle.
+ *
+ * @crop: rectangle to adjust.
+ * @bounds: rectangle used as bounds.
+ */
+void rkisp2_sd_adjust_crop_rect(struct v4l2_rect *crop,
+ const struct v4l2_rect *bounds);
+
+/*
+ * rkisp2_sd_adjust_crop - adjust a rectangle to fit into media bus format
+ *
+ * @crop: rectangle to adjust.
+ * @bounds: media bus format used as bounds.
+ */
+void rkisp2_sd_adjust_crop(struct v4l2_rect *crop,
+ const struct v4l2_mbus_framefmt *bounds);
+
+/*
+ * rkisp2_mbus_info_get_by_code - get the isp info of the media bus code
+ *
+ * @mbus_code: the media bus code
+ */
+const struct rkisp2_mbus_info *rkisp2_mbus_info_get_by_code(u32 mbus_code);
+
+/* irq handlers */
+irqreturn_t rkisp2_isp_isr(int irq, void *ctx);
+irqreturn_t rkisp2_capture_isr(int irq, void *ctx);
+irqreturn_t rkisp2_mipi_isr(int irq, void *ctx);
+void rkisp2_dmarx_isr(struct rkisp2_device *rkisp2, u32 status);
+
+/* register/unregisters functions of the entities */
+int rkisp2_capture_devs_register(struct rkisp2_device *rkisp2);
+void rkisp2_capture_devs_unregister(struct rkisp2_device *rkisp2);
+
+int rkisp2_isp_register(struct rkisp2_device *rkisp2);
+void rkisp2_isp_unregister(struct rkisp2_device *rkisp2);
+int rkisp2_dmarx_register(struct rkisp2_device *rkisp2);
+void rkisp2_dmarx_unregister(struct rkisp2_device *rkisp2);
+
+#if IS_ENABLED(CONFIG_DEBUG_FS)
+void rkisp2_debug_init(struct rkisp2_device *rkisp2);
+void rkisp2_debug_cleanup(struct rkisp2_device *rkisp2);
+#else
+static inline void rkisp2_debug_init(struct rkisp2_device *rkisp2)
+{
+}
+static inline void rkisp2_debug_cleanup(struct rkisp2_device *rkisp2)
+{
+}
+#endif
+
+#endif /* _RKISP2_COMMON_H */
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
new file mode 100644
index 000000000000..4f439bd9156b
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - Base driver
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ *
+ * Based on Rockchip ISP2 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/minmax.h>
+#include <linux/pm_runtime.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+
+#include "rkisp2-common.h"
+
+struct rkisp2_debug_register {
+ u32 reg;
+ u32 shd;
+ const char * const name;
+};
+
+#define RKISP2_DEBUG_REG(name) { RKISP2_CIF_##name, 0, #name }
+#define RKISP2_DEBUG_SHD_REG(name) { \
+ RKISP2_CIF_##name, RKISP2_CIF_##name##_SHD, #name \
+}
+
+/* Keep this up-to-date when adding new registers. */
+#define RKISP2_MAX_REG_LENGTH 21
+
+static int rkisp2_debug_dump_regs(struct rkisp2_device *rkisp2,
+ struct seq_file *m, unsigned int offset,
+ const struct rkisp2_debug_register *regs)
+{
+ const int width = RKISP2_MAX_REG_LENGTH;
+ u32 val, shd;
+ int ret;
+
+ ret = pm_runtime_get_if_in_use(rkisp2->dev);
+ if (ret <= 0)
+ return ret ? : -ENODATA;
+
+ for (; regs->name; ++regs) {
+ val = rkisp2_read(rkisp2, offset + regs->reg);
+
+ if (regs->shd) {
+ shd = rkisp2_read(rkisp2, offset + regs->shd);
+ seq_printf(m, "%*s: 0x%08x/0x%08x\n", width, regs->name,
+ val, shd);
+ } else {
+ seq_printf(m, "%*s: 0x%08x\n", width, regs->name, val);
+ }
+ }
+
+ pm_runtime_put(rkisp2->dev);
+
+ return 0;
+}
+
+static int rkisp2_debug_dump_core_regs_show(struct seq_file *m, void *p)
+{
+ static const struct rkisp2_debug_register registers[] = {
+ RKISP2_DEBUG_REG(VI_ICCL),
+ RKISP2_DEBUG_REG(VI_IRCL),
+ RKISP2_DEBUG_REG(VI_DPCL),
+ RKISP2_DEBUG_REG(MI_CTRL),
+ RKISP2_DEBUG_REG(MI_BYTE_CNT),
+ RKISP2_DEBUG_REG(MI_CTRL_SHD),
+ RKISP2_DEBUG_REG(MI_RIS),
+ RKISP2_DEBUG_REG(MI_STATUS),
+ RKISP2_DEBUG_REG(MI_DMA_CTRL),
+ RKISP2_DEBUG_REG(MI_DMA_STATUS),
+ { /* Sentinel */ },
+ };
+ struct rkisp2_device *rkisp2 = m->private;
+
+ return rkisp2_debug_dump_regs(rkisp2, m, 0, registers);
+}
+DEFINE_SHOW_ATTRIBUTE(rkisp2_debug_dump_core_regs);
+
+static int rkisp2_debug_dump_isp_regs_show(struct seq_file *m, void *p)
+{
+ static const struct rkisp2_debug_register registers[] = {
+ RKISP2_DEBUG_REG(ISP_CTRL),
+ RKISP2_DEBUG_REG(ISP_ACQ_PROP),
+ RKISP2_DEBUG_REG(ISP_FLAGS_SHD),
+ RKISP2_DEBUG_REG(ISP_RIS),
+ RKISP2_DEBUG_REG(ISP_ERR),
+ RKISP2_DEBUG_SHD_REG(ISP_IS_H_OFFS),
+ RKISP2_DEBUG_SHD_REG(ISP_IS_V_OFFS),
+ RKISP2_DEBUG_SHD_REG(ISP_IS_H_SIZE),
+ RKISP2_DEBUG_SHD_REG(ISP_IS_V_SIZE),
+ { /* Sentinel */ },
+ };
+ struct rkisp2_device *rkisp2 = m->private;
+
+ return rkisp2_debug_dump_regs(rkisp2, m, 0, registers);
+}
+DEFINE_SHOW_ATTRIBUTE(rkisp2_debug_dump_isp_regs);
+
+static int rkisp2_debug_dump_mi_mp_show(struct seq_file *m, void *p)
+{
+ static const struct rkisp2_debug_register registers[] = {
+ RKISP2_DEBUG_REG(MI_MP_Y_BASE_AD_INIT),
+ RKISP2_DEBUG_REG(MI_MP_Y_BASE_AD_INIT2),
+ RKISP2_DEBUG_REG(MI_MP_Y_BASE_AD_SHD),
+ RKISP2_DEBUG_REG(MI_MP_Y_SIZE_INIT),
+ RKISP2_DEBUG_REG(MI_MP_Y_SIZE_INIT),
+ RKISP2_DEBUG_REG(MI_MP_Y_SIZE_SHD),
+ RKISP2_DEBUG_REG(MI_MP_Y_OFFS_CNT_SHD),
+ { /* Sentinel */ },
+ };
+ struct rkisp2_device *rkisp2 = m->private;
+
+ return rkisp2_debug_dump_regs(rkisp2, m, 0, registers);
+}
+DEFINE_SHOW_ATTRIBUTE(rkisp2_debug_dump_mi_mp);
+
+#define RKISP2_DEBUG_DATA_COUNT_BINS 32
+#define RKISP2_DEBUG_DATA_COUNT_STEP (4096 / RKISP2_DEBUG_DATA_COUNT_BINS)
+
+static int rkisp2_debug_input_status_show(struct seq_file *m, void *p)
+{
+ struct rkisp2_device *rkisp2 = m->private;
+ u16 data_count[RKISP2_DEBUG_DATA_COUNT_BINS] = { };
+ unsigned int hsync_count = 0;
+ unsigned int vsync_count = 0;
+ unsigned int i;
+ u32 data;
+ u32 val;
+ int ret;
+
+ ret = pm_runtime_get_if_in_use(rkisp2->dev);
+ if (ret <= 0)
+ return ret ? : -ENODATA;
+
+ /* Sample the ISP input port status 10000 times with a 1µs interval. */
+ for (i = 0; i < 10000; ++i) {
+ val = rkisp2_read(rkisp2, RKISP2_CIF_ISP_FLAGS_SHD);
+
+ data = (val & RKISP2_CIF_ISP_FLAGS_SHD_S_DATA_MASK)
+ >> RKISP2_CIF_ISP_FLAGS_SHD_S_DATA_SHIFT;
+ data_count[data / RKISP2_DEBUG_DATA_COUNT_STEP]++;
+
+ if (val & RKISP2_CIF_ISP_FLAGS_SHD_S_HSYNC)
+ hsync_count++;
+ if (val & RKISP2_CIF_ISP_FLAGS_SHD_S_VSYNC)
+ vsync_count++;
+
+ udelay(1);
+ }
+
+ pm_runtime_put(rkisp2->dev);
+
+ seq_printf(m, "vsync: %u, hsync: %u\n", vsync_count, hsync_count);
+ seq_puts(m, "data:\n");
+ for (i = 0; i < ARRAY_SIZE(data_count); ++i)
+ seq_printf(m, "- [%04u:%04u]: %u\n",
+ i * RKISP2_DEBUG_DATA_COUNT_STEP,
+ (i + 1) * RKISP2_DEBUG_DATA_COUNT_STEP - 1,
+ data_count[i]);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(rkisp2_debug_input_status);
+
+void rkisp2_debug_init(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_debug *debug = &rkisp2->debug;
+ struct dentry *regs_dir;
+
+ debug->debugfs_dir = debugfs_create_dir(dev_name(rkisp2->dev), NULL);
+
+ debugfs_create_ulong("data_loss", 0444, debug->debugfs_dir,
+ &debug->data_loss);
+ debugfs_create_ulong("outform_size_err", 0444, debug->debugfs_dir,
+ &debug->outform_size_error);
+ debugfs_create_ulong("img_stabilization_size_error", 0444,
+ debug->debugfs_dir,
+ &debug->img_stabilization_size_error);
+ debugfs_create_ulong("inform_size_error", 0444, debug->debugfs_dir,
+ &debug->inform_size_error);
+ debugfs_create_ulong("irq_delay", 0444, debug->debugfs_dir,
+ &debug->irq_delay);
+ debugfs_create_ulong("mipi_error", 0444, debug->debugfs_dir,
+ &debug->mipi_error);
+ debugfs_create_ulong("stats_error", 0444, debug->debugfs_dir,
+ &debug->stats_error);
+ debugfs_create_ulong("mp_stop_timeout", 0444, debug->debugfs_dir,
+ &debug->stop_timeout[RKISP2_MAINPATH]);
+ debugfs_create_ulong("sp_stop_timeout", 0444, debug->debugfs_dir,
+ &debug->stop_timeout[RKISP2_SELFPATH]);
+ debugfs_create_ulong("mp_frame_drop", 0444, debug->debugfs_dir,
+ &debug->frame_drop[RKISP2_MAINPATH]);
+ debugfs_create_ulong("sp_frame_drop", 0444, debug->debugfs_dir,
+ &debug->frame_drop[RKISP2_SELFPATH]);
+ debugfs_create_ulong("complete_frames", 0444, debug->debugfs_dir,
+ &debug->complete_frames);
+ debugfs_create_file("input_status", 0444, debug->debugfs_dir, rkisp2,
+ &rkisp2_debug_input_status_fops);
+
+ regs_dir = debugfs_create_dir("regs", debug->debugfs_dir);
+
+ debugfs_create_file("core", 0444, regs_dir, rkisp2,
+ &rkisp2_debug_dump_core_regs_fops);
+ debugfs_create_file("isp", 0444, regs_dir, rkisp2,
+ &rkisp2_debug_dump_isp_regs_fops);
+ debugfs_create_file("mi_mp", 0444, regs_dir, rkisp2,
+ &rkisp2_debug_dump_mi_mp_fops);
+}
+
+void rkisp2_debug_cleanup(struct rkisp2_device *rkisp2)
+{
+ debugfs_remove_recursive(rkisp2->debug.debugfs_dir);
+}
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
new file mode 100644
index 000000000000..4d5c41850395
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - Base driver
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/iommu.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-mc.h>
+
+#include "rkisp2-common.h"
+
+struct rkisp2_isr_data {
+ const char *name;
+ irqreturn_t (*isr)(int irq, void *ctx);
+ u32 line_mask;
+};
+
+/* ----------------------------------------------------------------------------
+ * Power
+ */
+
+static int __maybe_unused rkisp2_runtime_suspend(struct device *dev)
+{
+ struct rkisp2_device *rkisp2 = dev_get_drvdata(dev);
+
+ rkisp2->irqs_enabled = false;
+ /* Make sure the IRQ handler will see the above */
+ mb();
+
+ /*
+ * Wait until any running IRQ handler has returned. The IRQ handler
+ * may get called even after this (as it's a shared interrupt line)
+ * but the 'irqs_enabled' flag will make the handler return immediately.
+ */
+ for (unsigned int il = 0; il < ARRAY_SIZE(rkisp2->irqs); ++il) {
+ if (rkisp2->irqs[il] == -1)
+ continue;
+
+ /* Skip if the irq line is the same as previous */
+ if (il == 0 || rkisp2->irqs[il - 1] != rkisp2->irqs[il])
+ synchronize_irq(rkisp2->irqs[il]);
+ }
+
+ clk_bulk_disable_unprepare(rkisp2->clk_size, rkisp2->clks);
+ return pinctrl_pm_select_sleep_state(dev);
+}
+
+static int __maybe_unused rkisp2_runtime_resume(struct device *dev)
+{
+ struct rkisp2_device *rkisp2 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(rkisp2->clk_size, rkisp2->clks);
+ if (ret)
+ return ret;
+
+ rkisp2->irqs_enabled = true;
+ /* Make sure the IRQ handler will see the above */
+ mb();
+
+ rkisp2_write(rkisp2, ISP3X_SWS_CFG, RKISP2_CIF_SWS_MIPI_DROP_FRM_DIS);
+
+ return 0;
+}
+
+static const struct dev_pm_ops rkisp2_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(rkisp2_runtime_suspend, rkisp2_runtime_resume, NULL)
+};
+
+/* ----------------------------------------------------------------------------
+ * Core
+ */
+
+static int rkisp2_create_links(struct rkisp2_device *rkisp2)
+{
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < 2; i++) {
+ struct media_entity *capture =
+ &rkisp2->capture_devs[i].vnode.vdev.entity;
+
+ ret = media_create_pad_link(&rkisp2->isp.sd.entity,
+ RKISP2_ISP_PAD_SOURCE_VIDEO,
+ capture, 0,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < rkisp2->dmarx.num_chans; i++) {
+ struct media_entity *source =
+ &rkisp2->dmarx.chan[i].vnode.vdev.entity;
+ if (i == RKISP2_RAWRD0) {
+ ret = media_create_pad_link(
+ source, 0, &rkisp2->isp.sd.entity,
+ RKISP2_ISP_PAD_SINK_VIDEO,
+ MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
+ } else {
+ ret = media_create_pad_link(source, 0,
+ &rkisp2->isp.sd.entity,
+ RKISP2_ISP_PAD_SINK_VIDEO,
+ 0);
+ }
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rkisp2_entities_unregister(struct rkisp2_device *rkisp2)
+{
+ rkisp2_dmarx_unregister(rkisp2);
+ rkisp2_capture_devs_unregister(rkisp2);
+ rkisp2_isp_unregister(rkisp2);
+}
+
+static int rkisp2_entities_register(struct rkisp2_device *rkisp2)
+{
+ int ret;
+
+ ret = rkisp2_isp_register(rkisp2);
+ if (ret)
+ goto error;
+
+ ret = rkisp2_capture_devs_register(rkisp2);
+ if (ret)
+ goto error;
+
+ ret = rkisp2_dmarx_register(rkisp2);
+ if (ret)
+ goto error;
+
+ ret = rkisp2_create_links(rkisp2);
+ if (ret)
+ goto error;
+
+ return 0;
+
+error:
+ rkisp2_entities_unregister(rkisp2);
+ return ret;
+}
+
+static const char * const rk3588_isp_clks[] = {
+ "aclk",
+ "hclk",
+ "clk_core",
+ "clk_core_marvin",
+ "clk_core_vicap",
+};
+
+static const struct rkisp2_isr_data rk3588_isp_isrs[] = {
+ { "isp_irq", rkisp2_isp_isr, BIT(RKISP2_IRQ_ISP) },
+ { "mi_irq", rkisp2_capture_isr, BIT(RKISP2_IRQ_MI) },
+};
+
+static const struct rkisp2_info rk3588_isp_info = {
+ .clks = rk3588_isp_clks,
+ .clk_size = ARRAY_SIZE(rk3588_isp_clks),
+ .isrs = rk3588_isp_isrs,
+ .isr_size = ARRAY_SIZE(rk3588_isp_isrs),
+ .isp_ver = RKISP3_V0,
+ .features = RKISP2_FEATURE_DUAL_CROP,
+ .max_width = 4672,
+ .max_height = 3504,
+};
+
+static const struct of_device_id rkisp2_of_match[] = {
+ {
+ .compatible = "rockchip,rk3588-isp",
+ .data = &rk3588_isp_info,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rkisp2_of_match);
+
+static int rkisp2_probe(struct platform_device *pdev)
+{
+ const struct rkisp2_info *info;
+ struct device *dev = &pdev->dev;
+ struct rkisp2_device *rkisp2;
+ struct v4l2_device *v4l2_dev;
+ unsigned int i;
+ int ret, irq;
+ u32 cif_id;
+
+ rkisp2 = devm_kzalloc(dev, sizeof(*rkisp2), GFP_KERNEL);
+ if (!rkisp2)
+ return -ENOMEM;
+
+ info = of_device_get_match_data(dev);
+ rkisp2->info = info;
+
+ dev_set_drvdata(dev, rkisp2);
+ rkisp2->dev = dev;
+
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+ if (ret)
+ return ret;
+
+ mutex_init(&rkisp2->stream_lock);
+
+ rkisp2->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rkisp2->base_addr))
+ return PTR_ERR(rkisp2->base_addr);
+
+ for (unsigned int il = 0; il < ARRAY_SIZE(rkisp2->irqs); ++il)
+ rkisp2->irqs[il] = -1;
+
+ for (i = 0; i < info->isr_size; i++) {
+ irq = info->isrs[i].name
+ ? platform_get_irq_byname(pdev, info->isrs[i].name)
+ : platform_get_irq(pdev, i);
+ if (irq < 0)
+ return irq;
+
+ for (unsigned int il = 0; il < ARRAY_SIZE(rkisp2->irqs); ++il) {
+ if (info->isrs[i].line_mask & BIT(il))
+ rkisp2->irqs[il] = irq;
+ }
+
+ ret = devm_request_irq(dev, irq, info->isrs[i].isr, IRQF_SHARED,
+ dev_driver_string(dev), dev);
+ if (ret) {
+ dev_err(dev, "request irq failed: %d\n", ret);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < info->clk_size; i++)
+ rkisp2->clks[i].id = info->clks[i];
+ ret = devm_clk_bulk_get(dev, info->clk_size, rkisp2->clks);
+ if (ret)
+ return ret;
+ rkisp2->clk_size = info->clk_size;
+
+ pm_runtime_enable(&pdev->dev);
+
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ goto err_pm_runtime_disable;
+
+ cif_id = rkisp2_read(rkisp2, RKISP2_CIF_VI_ID);
+ dev_dbg(rkisp2->dev, "CIF_ID 0x%08x\n", cif_id);
+
+ pm_runtime_put(&pdev->dev);
+
+ rkisp2->media_dev.hw_revision = info->isp_ver;
+ strscpy(rkisp2->media_dev.model, RKISP2_DRIVER_NAME,
+ sizeof(rkisp2->media_dev.model));
+ rkisp2->media_dev.dev = &pdev->dev;
+ strscpy(rkisp2->media_dev.bus_info, RKISP2_BUS_INFO,
+ sizeof(rkisp2->media_dev.bus_info));
+ media_device_init(&rkisp2->media_dev);
+
+ v4l2_dev = &rkisp2->v4l2_dev;
+ v4l2_dev->mdev = &rkisp2->media_dev;
+ strscpy(v4l2_dev->name, RKISP2_DRIVER_NAME, sizeof(v4l2_dev->name));
+
+ ret = v4l2_device_register(rkisp2->dev, &rkisp2->v4l2_dev);
+ if (ret)
+ goto err_media_dev_cleanup;
+
+ ret = media_device_register(&rkisp2->media_dev);
+ if (ret)
+ goto err_unreg_v4l2_dev;
+
+ ret = rkisp2_entities_register(rkisp2);
+ if (ret)
+ goto err_unreg_media_dev;
+
+ ret = v4l2_device_register_subdev_nodes(&rkisp2->v4l2_dev);
+ if (ret)
+ goto err_unreg_entities;
+
+ rkisp2_debug_init(rkisp2);
+
+ return 0;
+
+err_unreg_entities:
+ rkisp2_entities_unregister(rkisp2);
+err_unreg_media_dev:
+ media_device_unregister(&rkisp2->media_dev);
+err_unreg_v4l2_dev:
+ v4l2_device_unregister(&rkisp2->v4l2_dev);
+err_media_dev_cleanup:
+ media_device_cleanup(&rkisp2->media_dev);
+err_pm_runtime_disable:
+ pm_runtime_disable(&pdev->dev);
+ return ret;
+}
+
+static void rkisp2_remove(struct platform_device *pdev)
+{
+ struct rkisp2_device *rkisp2 = platform_get_drvdata(pdev);
+
+ v4l2_async_nf_unregister(&rkisp2->notifier);
+ v4l2_async_nf_cleanup(&rkisp2->notifier);
+
+ rkisp2_entities_unregister(rkisp2);
+ rkisp2_debug_cleanup(rkisp2);
+
+ media_device_unregister(&rkisp2->media_dev);
+ v4l2_device_unregister(&rkisp2->v4l2_dev);
+
+ media_device_cleanup(&rkisp2->media_dev);
+
+ pm_runtime_disable(&pdev->dev);
+}
+
+static struct platform_driver rkisp2_drv = {
+ .driver = {
+ .name = RKISP2_DRIVER_NAME,
+ .of_match_table = of_match_ptr(rkisp2_of_match),
+ .pm = &rkisp2_pm_ops,
+ },
+ .probe = rkisp2_probe,
+ .remove = rkisp2_remove,
+};
+
+module_platform_driver(rkisp2_drv);
+MODULE_DESCRIPTION("Rockchip ISP2 platform driver");
+MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-dmarx.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-dmarx.c
new file mode 100644
index 000000000000..5db032a88539
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-dmarx.c
@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2025 Rockchip Electronics Co., Ltd.
+ *
+ * Rockchip ISP2 Driver - RAWRD support (memory input to ISP)
+ */
+
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mc.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "rkisp2-common.h"
+
+#define RKISP2_RAWRD0_NAME RKISP2_DRIVER_NAME "_rawrd0"
+#define RKISP2_RAWRD1_NAME RKISP2_DRIVER_NAME "_rawrd1"
+#define RKISP2_RAWRD2_NAME RKISP2_DRIVER_NAME "_rawrd2"
+
+static const struct rkisp2_dmarx_fmt rkisp2_rawrd_formats[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB8,
+ .bpp = 8,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SBGGR8,
+ .bpp = 8,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .bpp = 8,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGBRG8,
+ .bpp = 8,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB10,
+ .bpp = 16,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SBGGR10,
+ .bpp = 16,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .bpp = 16,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGBRG10,
+ .bpp = 16,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB12,
+ .bpp = 12,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SBGGR12,
+ .bpp = 12,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .bpp = 12,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGBRG12,
+ .bpp = 12,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB16,
+ .bpp = 16,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SBGGR16,
+ .bpp = 16,
+ },
+};
+
+static const struct rkisp2_rawrd_cfg rkisp2_rawrd_cfgs[RKISP2_RAWRD_MAX] = {
+ [RKISP2_RAWRD0] = {
+ .name = RKISP2_RAWRD0_NAME,
+ .ready_mask = RKISP2_CIF_MI_MP_FE | RKISP2_CIF_MI_SP_FE,
+ .base_reg = MI_RAW2_RD_BASE,
+ .length_reg = MI_RAW2_RD_LENGTH,
+ .enable_mask = SW_CSI_RAW2_RD_EN_ORG,
+ .channel_sel = 0,
+ },
+ [RKISP2_RAWRD1] = {
+ .name = RKISP2_RAWRD1_NAME,
+ .ready_mask = RKISP2_CIF_MI_MP_FE | RKISP2_CIF_MI_SP_FE,
+ .base_reg = MI_RAW0_RD_BASE,
+ .length_reg = MI_RAW0_RD_LENGTH,
+ .enable_mask = SW_CSI_RAW0_RD_EN_ORG,
+ .channel_sel = 1,
+ },
+ [RKISP2_RAWRD2] = {
+ .name = RKISP2_RAWRD2_NAME,
+ .ready_mask = RKISP2_CIF_MI_MP_FE | RKISP2_CIF_MI_SP_FE,
+ .base_reg = MI_RAW1_RD_BASE,
+ .length_reg = MI_RAW1_RD_LENGTH,
+ .enable_mask = SW_CSI_RAW1_RD_EN_ORG,
+ .channel_sel = 2,
+ },
+};
+
+static inline struct rkisp2_vdev_node *
+rkisp2_rawrd_to_node(struct rkisp2_dmarx_chan *chan)
+{
+ return &chan->vnode;
+}
+
+static u32 rkisp2_rawrd_mipi_dt(u32 fourcc)
+{
+ switch (fourcc) {
+ case V4L2_PIX_FMT_SRGGB8:
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SGBRG8:
+ return RKISP2_CIF_CSI2_DT_RAW8;
+ case V4L2_PIX_FMT_SRGGB10:
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SGBRG10:
+ return RKISP2_CIF_CSI2_DT_RAW10;
+ case V4L2_PIX_FMT_SRGGB12:
+ case V4L2_PIX_FMT_SBGGR12:
+ case V4L2_PIX_FMT_SGRBG12:
+ case V4L2_PIX_FMT_SGBRG12:
+ return RKISP2_CIF_CSI2_DT_RAW12;
+ case V4L2_PIX_FMT_SRGGB16:
+ case V4L2_PIX_FMT_SBGGR16:
+ return RKISP2_CIF_CSI2_DT_RAW16;
+ default:
+ return RKISP2_CIF_CSI2_DT_RAW12;
+ }
+}
+
+static const struct rkisp2_dmarx_fmt *
+rkisp2_rawrd_find_fmt(const struct rkisp2_dmarx_chan *chan, u32 fourcc)
+{
+ unsigned int i;
+
+ for (i = 0; i < chan->fmt_cnt; i++)
+ if (chan->fmts[i].fourcc == fourcc)
+ return &chan->fmts[i];
+
+ return NULL;
+}
+
+static void rkisp2_rawrd_set_default_pix(struct rkisp2_dmarx_chan *chan)
+{
+ struct v4l2_pix_format_mplane *pix = &chan->pix;
+ const struct rkisp2_dmarx_fmt *fmt = chan->fmts;
+ u32 stride;
+
+ memset(pix, 0, sizeof(*pix));
+ pix->width = 1920;
+ pix->height = 1080;
+ pix->field = V4L2_FIELD_NONE;
+ pix->num_planes = 1;
+ pix->pixelformat = fmt->fourcc;
+ pix->colorspace = V4L2_COLORSPACE_RAW;
+ stride = DIV_ROUND_UP(pix->width * fmt->bpp, 8);
+ pix->plane_fmt[0].bytesperline = stride;
+ pix->plane_fmt[0].sizeimage = stride * pix->height;
+ chan->fmt = fmt;
+}
+
+static void rkisp2_rawrd_update_stride(struct rkisp2_dmarx_chan *chan)
+{
+ struct v4l2_pix_format_mplane *pix = &chan->pix;
+ u32 stride = DIV_ROUND_UP(pix->width * chan->fmt->bpp, 8);
+
+ pix->plane_fmt[0].bytesperline = stride;
+ pix->plane_fmt[0].sizeimage = stride * pix->height;
+}
+
+static int rkisp2_rawrd_try_fmt(struct rkisp2_dmarx_chan *chan,
+ struct v4l2_pix_format_mplane *pix)
+{
+ const struct rkisp2_dmarx_fmt *fmt;
+
+ fmt = rkisp2_rawrd_find_fmt(chan, pix->pixelformat);
+ if (!fmt)
+ fmt = chan->fmts;
+
+ pix->pixelformat = fmt->fourcc;
+ pix->field = V4L2_FIELD_NONE;
+ pix->num_planes = 1;
+ pix->colorspace = V4L2_COLORSPACE_RAW;
+ pix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ pix->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ pix->xfer_func = V4L2_XFER_FUNC_DEFAULT;
+
+ pix->width = clamp_t(u32, pix->width,
+ RKISP2_ISP_MIN_WIDTH,
+ chan->rkisp2->info->max_width);
+ pix->height = clamp_t(u32, pix->height,
+ RKISP2_ISP_MIN_HEIGHT,
+ chan->rkisp2->info->max_height);
+
+ pix->plane_fmt[0].bytesperline = DIV_ROUND_UP(pix->width * fmt->bpp, 8);
+ pix->plane_fmt[0].sizeimage = pix->plane_fmt[0].bytesperline * pix->height;
+
+ return 0;
+}
+
+static void rkisp2_rawrd_select(struct rkisp2_dmarx_chan *chan)
+{
+ struct rkisp2_device *rkisp2 = chan->rkisp2;
+ u32 val;
+
+ val = rkisp2_read(rkisp2, CSI2RX_RAW_RD_CTRL);
+ val &= ~SW_CSI_RAW_RD_CH_SEL(0x7);
+ // default is uncompressed and little endian
+ val |= SW_CSI_RAW_RD_CH_SEL(chan->cfg->channel_sel) |
+ RKISP2_CIF_ISP_CSI_RAW_RD_UNCOMPRESS | RKISP2_CIF_ISP_CSI_RAW_RD_LE_ALIGN;
+ rkisp2_write(rkisp2, CSI2RX_RAW_RD_CTRL, val);
+}
+
+static void rkisp2_rawrd_config_mi(struct rkisp2_dmarx_chan *chan)
+{
+ struct rkisp2_device *rkisp2 = chan->rkisp2;
+ const struct v4l2_pix_format_mplane *pix = &chan->pix;
+ u32 stride = pix->plane_fmt[0].bytesperline;
+ u32 dt, val;
+
+ rkisp2_rawrd_select(chan);
+ dt = rkisp2_rawrd_mipi_dt(chan->fmt->fourcc);
+
+ val = rkisp2_read(rkisp2, CSI2RX_DATA_IDS_1);
+ val &= ~SW_CSI_ID0(0xff);
+ val |= SW_CSI_ID0(dt);
+ rkisp2_write(rkisp2, CSI2RX_DATA_IDS_1, val);
+
+ rkisp2_write(rkisp2, CSI2RX_RAW_RD_PIC_SIZE,
+ (pix->height << 16) | pix->width);
+
+ if (chan->cfg->length_reg)
+ rkisp2_write(rkisp2, chan->cfg->length_reg, stride);
+
+ rkisp2_write(rkisp2, MI_RD_CTRL2, BIT(30));
+}
+
+static void rkisp2_rawrd_program_buffer(struct rkisp2_dmarx_chan *chan,
+ struct rkisp2_buffer *buf)
+{
+ rkisp2_rawrd_select(chan);
+ rkisp2_write(chan->rkisp2, chan->cfg->base_reg,
+ buf->buff_addr[0]);
+}
+
+static void rkisp2_rawrd_update_mi(struct rkisp2_dmarx_chan *chan,
+ struct rkisp2_buffer *buf)
+{
+ if (!buf)
+ return;
+
+ rkisp2_rawrd_program_buffer(chan, buf);
+
+ rkisp2_write(chan->rkisp2, RKISP2_CIF_MIPI_CTRL,
+ rkisp2_read(chan->rkisp2, RKISP2_CIF_MIPI_CTRL) |
+ RKISP2_CIF_MIPI_CTRL_OUTPUT_ENA);
+
+ dev_dbg(chan->rkisp2->dev, "%s: %s buffer %pad, output enabled\n",
+ __func__, chan->cfg->name, &buf->buff_addr[0]);
+}
+
+static void rkisp2_rawrd_return_all_buffers(struct rkisp2_dmarx_chan *chan,
+ enum vb2_buffer_state state)
+{
+ struct rkisp2_buffer *buf;
+
+ spin_lock_irq(&chan->buf_lock);
+ if (chan->curr_buf) {
+ vb2_buffer_done(&chan->curr_buf->vb.vb2_buf, state);
+ chan->curr_buf = NULL;
+ }
+ while (!list_empty(&chan->buf_queue)) {
+ buf = list_first_entry(&chan->buf_queue,
+ struct rkisp2_buffer, queue);
+ list_del(&buf->queue);
+ vb2_buffer_done(&buf->vb.vb2_buf, state);
+ }
+ spin_unlock_irq(&chan->buf_lock);
+}
+
+void rkisp2_dmarx_isr(struct rkisp2_device *rkisp2, u32 status)
+{
+ struct rkisp2_dmarx *dmarx = &rkisp2->dmarx;
+ unsigned int i;
+
+ dev_dbg(rkisp2->dev, "dmarx isr: status=0x%x\n", status);
+
+ for (i = 0; i < dmarx->num_chans; i++) {
+ struct rkisp2_dmarx_chan *chan = &dmarx->chan[i];
+ struct rkisp2_buffer *done = NULL;
+
+ if (!(status & chan->cfg->ready_mask))
+ continue;
+ if (!chan->streaming)
+ continue;
+
+ spin_lock(&chan->buf_lock);
+ done = chan->curr_buf;
+ chan->curr_buf = NULL;
+ if (!list_empty(&chan->buf_queue)) {
+ chan->curr_buf = list_first_entry(&chan->buf_queue,
+ struct rkisp2_buffer, queue);
+ list_del(&chan->curr_buf->queue);
+ }
+ spin_unlock(&chan->buf_lock);
+
+ if (chan->curr_buf)
+ rkisp2_rawrd_update_mi(chan, chan->curr_buf);
+
+ if (done)
+ vb2_buffer_done(&done->vb.vb2_buf, VB2_BUF_STATE_DONE);
+
+ dev_dbg(rkisp2->dev, "%s: %s buffer %pad done\n",
+ __func__, chan->cfg->name, &done->buff_addr[0]);
+ }
+}
+
+static int rkisp2_rawrd_queue_setup(struct vb2_queue *queue,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct rkisp2_dmarx_chan *chan = queue->drv_priv;
+ const struct v4l2_pix_format_mplane *pix = &chan->pix;
+
+ if (*num_planes && *num_planes != pix->num_planes)
+ return -EINVAL;
+
+ *num_planes = pix->num_planes;
+ sizes[0] = pix->plane_fmt[0].sizeimage;
+
+ return 0;
+}
+
+static int rkisp2_rawrd_buf_prepare(struct vb2_buffer *vb)
+{
+ struct rkisp2_dmarx_chan *chan = vb->vb2_queue->drv_priv;
+ const struct v4l2_pix_format_mplane *pix = &chan->pix;
+
+ if (vb2_plane_size(vb, 0) < pix->plane_fmt[0].sizeimage)
+ return -EINVAL;
+
+ vb2_set_plane_payload(vb, 0, pix->plane_fmt[0].sizeimage);
+ return 0;
+}
+
+static int rkisp2_rawrd_buf_init(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_buffer *buf = container_of(vbuf, struct rkisp2_buffer, vb);
+
+ buf->buff_addr[0] = vb2_dma_contig_plane_dma_addr(vb, 0);
+ INIT_LIST_HEAD(&buf->queue);
+
+ return 0;
+}
+
+static void rkisp2_rawrd_buf_queue(struct vb2_buffer *vb)
+{
+ struct rkisp2_dmarx_chan *chan = vb->vb2_queue->drv_priv;
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_buffer *buf = container_of(vbuf, struct rkisp2_buffer, vb);
+ bool start = false;
+
+ spin_lock_irq(&chan->buf_lock);
+ if (chan->streaming && !chan->curr_buf) {
+ chan->curr_buf = buf;
+ start = true;
+ } else {
+ list_add_tail(&buf->queue, &chan->buf_queue);
+ }
+ spin_unlock_irq(&chan->buf_lock);
+
+ if (start)
+ rkisp2_rawrd_update_mi(chan, buf);
+}
+
+static void rkisp2_rawrd_stop_streaming(struct vb2_queue *queue)
+{
+ struct rkisp2_dmarx_chan *chan = queue->drv_priv;
+ struct rkisp2_device *rkisp2 = chan->rkisp2;
+ struct media_entity *entity = &chan->vnode.vdev.entity;
+
+ mutex_lock(&rkisp2->stream_lock);
+ chan->streaming = false;
+ rkisp2_rawrd_return_all_buffers(chan, VB2_BUF_STATE_ERROR);
+ v4l2_pipeline_pm_put(entity);
+ pm_runtime_put(rkisp2->dev);
+ video_device_pipeline_stop(&chan->vnode.vdev);
+ mutex_unlock(&rkisp2->stream_lock);
+}
+
+static int rkisp2_rawrd_start_streaming(struct vb2_queue *queue,
+ unsigned int count)
+{
+ struct rkisp2_dmarx_chan *chan = queue->drv_priv;
+ struct rkisp2_device *rkisp2 = chan->rkisp2;
+ struct media_entity *entity = &chan->vnode.vdev.entity;
+ struct rkisp2_buffer *buf = NULL;
+ int ret;
+ u32 val;
+
+ mutex_lock(&rkisp2->stream_lock);
+
+ ret = video_device_pipeline_start(&chan->vnode.vdev, &rkisp2->pipe);
+ if (ret)
+ goto err_unlock;
+
+ ret = pm_runtime_resume_and_get(rkisp2->dev);
+ if (ret < 0)
+ goto err_pipeline_stop;
+
+ ret = v4l2_pipeline_pm_get(entity);
+ if (ret)
+ goto err_pm_put;
+
+ rkisp2_rawrd_config_mi(chan);
+ chan->streaming = true;
+
+ spin_lock_irq(&chan->buf_lock);
+ if (!list_empty(&chan->buf_queue)) {
+ buf = list_first_entry(&chan->buf_queue,
+ struct rkisp2_buffer, queue);
+ list_del(&buf->queue);
+ }
+ chan->curr_buf = buf;
+ spin_unlock_irq(&chan->buf_lock);
+
+ rkisp2_rawrd_update_mi(chan, buf);
+
+ // Enable CSI2 Receiver
+ val = rkisp2_read(rkisp2, CSI2RX_CTRL0);
+ val &= ~SW_IBUF_OP_MODE(0xf);
+ val |= SW_IBUF_OP_MODE(4) | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(0);
+ rkisp2_write(rkisp2, CSI2RX_CTRL0, val);
+
+ mutex_unlock(&rkisp2->stream_lock);
+ return 0;
+
+err_pm_put:
+ pm_runtime_put(rkisp2->dev);
+err_pipeline_stop:
+ video_device_pipeline_stop(&chan->vnode.vdev);
+err_unlock:
+ rkisp2_rawrd_return_all_buffers(chan, VB2_BUF_STATE_QUEUED);
+ mutex_unlock(&rkisp2->stream_lock);
+ return ret;
+}
+
+static const struct vb2_ops rkisp2_rawrd_vb2_ops = {
+ .queue_setup = rkisp2_rawrd_queue_setup,
+ .buf_prepare = rkisp2_rawrd_buf_prepare,
+ .buf_init = rkisp2_rawrd_buf_init,
+ .buf_queue = rkisp2_rawrd_buf_queue,
+ .start_streaming = rkisp2_rawrd_start_streaming,
+ .stop_streaming = rkisp2_rawrd_stop_streaming,
+};
+
+static int rkisp2_rawrd_querycap(struct file *file, void *fh,
+ struct v4l2_capability *cap)
+{
+ struct rkisp2_dmarx_chan *chan = video_drvdata(file);
+ struct rkisp2_device *rkisp2 = chan->rkisp2;
+ struct video_device *vdev = video_devdata(file);
+
+ strscpy(cap->driver, RKISP2_DRIVER_NAME, sizeof(cap->driver));
+ strscpy(cap->card, vdev->name, sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info),
+ "platform:%s", dev_name(rkisp2->dev));
+ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
+
+ return 0;
+}
+
+static int rkisp2_rawrd_enum_fmt(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ if (f->index >= ARRAY_SIZE(rkisp2_rawrd_formats))
+ return -EINVAL;
+
+ f->pixelformat = rkisp2_rawrd_formats[f->index].fourcc;
+ return 0;
+}
+
+static int rkisp2_rawrd_g_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp2_dmarx_chan *chan = video_drvdata(file);
+
+ f->fmt.pix_mp = chan->pix;
+ return 0;
+}
+
+static int rkisp2_rawrd_try_fmt_ioctl(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp2_dmarx_chan *chan = video_drvdata(file);
+
+ return rkisp2_rawrd_try_fmt(chan, &f->fmt.pix_mp);
+}
+
+static int rkisp2_rawrd_s_fmt(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp2_dmarx_chan *chan = video_drvdata(file);
+ int ret;
+
+ if (vb2_is_busy(&rkisp2_rawrd_to_node(chan)->buf_queue))
+ return -EBUSY;
+
+ ret = rkisp2_rawrd_try_fmt(chan, &f->fmt.pix_mp);
+ if (ret)
+ return ret;
+
+ chan->pix = f->fmt.pix_mp;
+ chan->fmt = rkisp2_rawrd_find_fmt(chan, chan->pix.pixelformat);
+ rkisp2_rawrd_update_stride(chan);
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops rkisp2_rawrd_ioctl_ops = {
+ .vidioc_querycap = rkisp2_rawrd_querycap,
+ .vidioc_enum_fmt_vid_out = rkisp2_rawrd_enum_fmt,
+ .vidioc_g_fmt_vid_out_mplane = rkisp2_rawrd_g_fmt,
+ .vidioc_try_fmt_vid_out_mplane = rkisp2_rawrd_try_fmt_ioctl,
+ .vidioc_s_fmt_vid_out_mplane = rkisp2_rawrd_s_fmt,
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+};
+
+static const struct v4l2_file_operations rkisp2_rawrd_fops = {
+ .owner = THIS_MODULE,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = vb2_fop_mmap,
+ .poll = vb2_fop_poll,
+};
+
+static int rkisp2_rawrd_link_validate(struct media_link *link)
+{
+ return 0;
+}
+
+static const struct media_entity_operations rkisp2_rawrd_media_ops = {
+ .link_validate = rkisp2_rawrd_link_validate,
+};
+
+static void rkisp2_rawrd_media_cleanup(struct rkisp2_dmarx_chan *chan)
+{
+ struct rkisp2_vdev_node *node = rkisp2_rawrd_to_node(chan);
+
+ if (video_is_registered(&node->vdev)) {
+ media_entity_cleanup(&node->vdev.entity);
+ vb2_video_unregister_device(&node->vdev);
+ } else {
+ vb2_queue_release(&node->buf_queue);
+ mutex_destroy(&node->vlock);
+ return;
+ }
+
+ mutex_destroy(&node->vlock);
+}
+
+static int rkisp2_rawrd_media_init(struct rkisp2_dmarx_chan *chan)
+{
+ struct rkisp2_device *rkisp2 = chan->rkisp2;
+ struct rkisp2_vdev_node *node = rkisp2_rawrd_to_node(chan);
+ struct video_device *vdev = &node->vdev;
+ struct vb2_queue *q = &node->buf_queue;
+ int ret;
+
+ mutex_init(&node->vlock);
+ strscpy(vdev->name, chan->cfg->name, sizeof(vdev->name));
+ vdev->ioctl_ops = &rkisp2_rawrd_ioctl_ops;
+ vdev->fops = &rkisp2_rawrd_fops;
+ vdev->release = video_device_release_empty;
+ vdev->vfl_dir = VFL_DIR_TX;
+ vdev->minor = -1;
+ vdev->v4l2_dev = &rkisp2->v4l2_dev;
+ vdev->lock = &node->vlock;
+ vdev->device_caps = V4L2_CAP_VIDEO_OUTPUT_MPLANE |
+ V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
+ vdev->entity.ops = &rkisp2_rawrd_media_ops;
+ video_set_drvdata(vdev, chan);
+
+ q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->drv_priv = chan;
+ q->ops = &rkisp2_rawrd_vb2_ops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->gfp_flags = GFP_DMA32;
+ q->buf_struct_size = sizeof(struct rkisp2_buffer);
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->min_queued_buffers = 1;
+ q->lock = &node->vlock;
+ q->dev = rkisp2->dev;
+
+ ret = vb2_queue_init(q);
+ if (ret) {
+ dev_err(rkisp2->dev, "rawrd vb2 init failed (%d)\n", ret);
+ return ret;
+ }
+
+ vdev->queue = q;
+ vdev->entity.function = MEDIA_ENT_F_IO_V4L;
+ node->pad.flags = MEDIA_PAD_FL_SOURCE;
+
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret)
+ return ret;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(rkisp2->dev, "failed to register %s (%d)\n",
+ vdev->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int rkisp2_dmarx_register(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_dmarx *dmarx = &rkisp2->dmarx;
+ unsigned int i;
+ int ret;
+
+ dmarx->num_chans = RKISP2_RAWRD_MAX;
+
+ for (i = 0; i < dmarx->num_chans; i++) {
+ struct rkisp2_dmarx_chan *chan = &dmarx->chan[i];
+
+ chan->rkisp2 = rkisp2;
+ chan->cfg = &rkisp2_rawrd_cfgs[i];
+ chan->fmts = rkisp2_rawrd_formats;
+ chan->fmt_cnt = ARRAY_SIZE(rkisp2_rawrd_formats);
+ chan->id = i;
+ spin_lock_init(&chan->buf_lock);
+ INIT_LIST_HEAD(&chan->buf_queue);
+ rkisp2_rawrd_set_default_pix(chan);
+
+ ret = rkisp2_rawrd_media_init(chan);
+ if (ret)
+ goto err_cleanup;
+ }
+
+ return 0;
+
+err_cleanup:
+ while (i--) {
+ struct rkisp2_dmarx_chan *chan = &dmarx->chan[i];
+
+ rkisp2_rawrd_media_cleanup(chan);
+ }
+ dmarx->num_chans = 0;
+ return ret;
+}
+
+void rkisp2_dmarx_unregister(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_dmarx *dmarx = &rkisp2->dmarx;
+ unsigned int i;
+
+ for (i = 0; i < dmarx->num_chans; i++)
+ rkisp2_rawrd_media_cleanup(&dmarx->chan[i]);
+
+ dmarx->num_chans = 0;
+}
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
new file mode 100644
index 000000000000..4140139da3c1
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
@@ -0,0 +1,902 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - ISP Subdevice
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/iopoll.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/videodev2.h>
+#include <linux/vmalloc.h>
+
+#include <media/v4l2-event.h>
+
+#include "rkisp2-common.h"
+
+#define RKISP2_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10
+#define RKISP2_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8
+
+#define RKISP2_ISP_DEV_NAME RKISP2_DRIVER_NAME "_isp"
+
+
+/* ----------------------------------------------------------------------------
+ * Camera Interface registers configurations
+ */
+
+/* Image stabilization */
+static void rkisp2_config_ism(struct rkisp2_isp *isp,
+ const struct v4l2_subdev_state *sd_state)
+{
+ const struct v4l2_rect *src_crop =
+ v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+ u32 val;
+
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_RECENTER, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_MAX_DX, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_MAX_DY, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_DISPLACE, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_H_OFFS, src_crop->left);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_V_OFFS, src_crop->top);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_H_SIZE, src_crop->width);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_V_SIZE, src_crop->height);
+
+ /* IS (Image Stabilization) is always on, working as output crop */
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IS_CTRL, 1);
+ val = rkisp2_read(rkisp2, RKISP2_CIF_ISP_CTRL);
+ val |= RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD;
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_CTRL, val);
+}
+
+/*
+ * configure ISP blocks with input format, size......
+ */
+static int rkisp2_config_isp(struct rkisp2_isp *isp,
+ const struct v4l2_subdev_state *sd_state)
+{
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+ u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, acq_prop = 0;
+ const struct rkisp2_mbus_info *sink_fmt;
+ const struct rkisp2_mbus_info *src_fmt;
+ const struct v4l2_mbus_framefmt *src_frm;
+ const struct v4l2_mbus_framefmt *sink_frm;
+ const struct v4l2_rect *sink_crop;
+
+ sink_frm = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ sink_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ src_frm = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+
+ sink_fmt = rkisp2_mbus_info_get_by_code(sink_frm->code);
+ src_fmt = rkisp2_mbus_info_get_by_code(src_frm->code);
+
+ if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ acq_mult = 1;
+ if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ isp_ctrl = RKISP2_CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
+ } else {
+ rkisp2_write(rkisp2, ISP_DEBAYER_CONTROL,
+ SW_DEBAYER_EN | SW_DEBAYER_FILTER_G_EN |
+ SW_DEBAYER_FILTER_C_EN);
+
+ isp_ctrl = RKISP2_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
+ }
+ } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) {
+ acq_mult = 2;
+ isp_ctrl = RKISP2_CIF_ISP_CTRL_ISP_MODE_ITU601;
+ irq_mask |= RKISP2_CIF_ISP_DATA_LOSS;
+ }
+
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_CTRL, isp_ctrl);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ACQ_PROP,
+ acq_prop | sink_fmt->yuv_seq |
+ RKISP2_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |
+ RKISP2_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ACQ_NR_FRAMES, 0);
+
+ /* Acquisition Size */
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ACQ_H_OFFS, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ACQ_V_OFFS, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ACQ_H_SIZE,
+ acq_mult * sink_frm->width);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ACQ_V_SIZE, sink_frm->height);
+
+ /* ISP Out Area */
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_OUT_H_OFFS, sink_crop->left);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_OUT_V_OFFS, sink_crop->top);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_OUT_H_SIZE, sink_crop->width);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_OUT_V_SIZE, sink_crop->height);
+
+ irq_mask |= RKISP2_CIF_ISP_FRAME | RKISP2_CIF_ISP_V_START |
+ RKISP2_CIF_ISP_PIC_SIZE_ERROR;
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IMSC, irq_mask);
+
+ isp->sink_fmt = sink_fmt;
+
+ return 0;
+}
+
+/* Configure MUX */
+static void rkisp2_config_path(struct rkisp2_isp *isp)
+{
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+ u32 dpcl = rkisp2_read(rkisp2, RKISP2_CIF_VI_DPCL);
+
+ dpcl |= RKISP2_CIF_VI_DPCL_IF_SEL_MIPI;
+ rkisp2_write(rkisp2, RKISP2_CIF_VI_DPCL, dpcl);
+}
+
+/* Hardware configure Entry */
+static int rkisp2_config_cif(struct rkisp2_isp *isp,
+ struct v4l2_subdev_state *sd_state)
+{
+ int ret;
+
+ ret = rkisp2_config_isp(isp, sd_state);
+ if (ret)
+ return ret;
+
+ rkisp2_config_ism(isp, sd_state);
+ rkisp2_config_path(isp);
+
+ return 0;
+}
+
+static void rkisp2_isp_stop(struct rkisp2_isp *isp)
+{
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+ u32 val;
+
+ /*
+ * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
+ * Stop ISP(isp) ->wait for ISP isp off
+ */
+
+ /* Mask MIPI, MI, ISP, and STATS3A interrupts */
+ rkisp2_write(rkisp2, RKISP2_CIF_MIPI_IMSC, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_IMSC, 0);
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_IMSC, 0);
+ rkisp2_write(rkisp2, ISP_ISP3A_IMSC, 0);
+
+ /* Flush posted writes */
+ rkisp2_read(rkisp2, RKISP2_CIF_MIPI_IMSC);
+ rkisp2_read(rkisp2, RKISP2_CIF_MI_IMSC);
+ rkisp2_read(rkisp2, ISP_ISP3A_IMSC);
+
+ /*
+ * Wait until the IRQ handlers have ended. The IRQ handler may still get
+ * invoked later (shared interrupt lines), but it will return immediately as
+ * the interrupts have now been masked.
+ */
+ for (unsigned int il = 0; il < ARRAY_SIZE(rkisp2->irqs); ++il) {
+ int irq = rkisp2->irqs[il];
+
+ if (irq < 0)
+ continue;
+ if (il > 0 && rkisp2->irqs[il - 1] == irq)
+ continue;
+
+ synchronize_irq(irq);
+ }
+
+ /* Clear MIPI, MI, ISP, and STATS3A interrupt status */
+ rkisp2_write(rkisp2, RKISP2_CIF_MIPI_ICR, ~0);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ICR, ~0);
+ rkisp2_write(rkisp2, RKISP2_CIF_MI_ICR, ~0);
+ rkisp2_write(rkisp2, ISP_ISP3A_ICR, ~0);
+
+ /* stop ISP */
+ val = rkisp2_read(rkisp2, RKISP2_CIF_ISP_CTRL);
+ val &= ~(RKISP2_CIF_ISP_CTRL_ISP_INFORM_ENABLE |
+ RKISP2_CIF_ISP_CTRL_ISP_ENABLE);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_CTRL, val);
+
+ val = rkisp2_read(rkisp2, RKISP2_CIF_ISP_CTRL);
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_CTRL,
+ val | RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD);
+
+ readx_poll_timeout(readl, rkisp2->base_addr + RKISP2_CIF_ISP_RIS,
+ val, val & RKISP2_CIF_ISP_OFF, 20, 100);
+ /* No need to reset stats3a, as the ISP soft reset covers it */
+ rkisp2_write(rkisp2, RKISP2_CIF_VI_IRCL,
+ RKISP2_CIF_VI_IRCL_MIPI_SW_RST |
+ RKISP2_CIF_VI_IRCL_ISP_SW_RST);
+ rkisp2_write(rkisp2, RKISP2_CIF_VI_IRCL, 0x0);
+}
+
+static void rkisp2_config_clk(struct rkisp2_isp *isp)
+{
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+
+ u32 val = (RKISP2_CIF_ICCL_ISP_CLK | RKISP2_CIF_ICCL_CP_CLK |
+ RKISP2_CIF_ICCL_MRSZ_CLK | RKISP2_CIF_ICCL_SRSZ_CLK |
+ RKISP2_CIF_ICCL_JPEG_CLK | RKISP2_CIF_ICCL_MI_CLK |
+ RKISP2_CIF_ICCL_IE_CLK | RKISP2_CIF_ICCL_MIPI_CLK |
+ RKISP2_CIF_ICCL_DCROP_CLK | ICCL_MPFBC_CLK);
+
+ rkisp2_write(rkisp2, RKISP2_CIF_VI_ICCL, val);
+
+ val = RKISP2_CIF_CLK_CTRL_ISP_3A | RKISP2_CIF_CLK_CTRL_ISP_RAW;
+ rkisp2_write(rkisp2, RKISP2_CIF_VI_ISP_CLK_CTRL_V12, val);
+
+ val = RKISP2_CIF_SWS_MIPI_DROP_FRM_DIS | RKISP2_CIF_SWS_ACK_FRM_PRO_DIS;
+ rkisp2_write(rkisp2, ISP3X_SWS_CFG, val);
+}
+
+static int rkisp2_isp_start(struct rkisp2_isp *isp,
+ const struct v4l2_subdev_state *sd_state,
+ struct media_pad *source)
+{
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+ u32 val;
+
+ rkisp2_config_clk(isp);
+
+ /* Activate ISP */
+ val = rkisp2_read(rkisp2, RKISP2_CIF_ISP_CTRL);
+ val |= RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD |
+ RKISP2_CIF_ISP_CTRL_ISP_ENABLE |
+ RKISP2_CIF_ISP_CTRL_ISP_INFORM_ENABLE | RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_CTRL, val);
+
+ return 0;
+}
+
+/* ----------------------------------------------------------------------------
+ * Subdev pad operations
+ */
+
+static inline struct rkisp2_isp *to_rkisp2_isp(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct rkisp2_isp, sd);
+}
+
+static int rkisp2_isp_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ unsigned int i, dir;
+ int pos = 0;
+
+ if (code->pad == RKISP2_ISP_PAD_SINK_VIDEO) {
+ dir = RKISP2_ISP_SD_SINK;
+ } else if (code->pad == RKISP2_ISP_PAD_SOURCE_VIDEO) {
+ dir = RKISP2_ISP_SD_SRC;
+ } else {
+ if (code->index > 0)
+ return -EINVAL;
+ code->code = MEDIA_BUS_FMT_METADATA_FIXED;
+ return 0;
+ }
+
+ for (i = 0; ; i++) {
+ const struct rkisp2_mbus_info *fmt =
+ rkisp2_mbus_info_get_by_index(i);
+
+ if (!fmt)
+ return -EINVAL;
+
+ if (fmt->direction & dir)
+ pos++;
+
+ if (code->index == pos - 1) {
+ code->code = fmt->mbus_code;
+ if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV &&
+ dir == RKISP2_ISP_SD_SRC)
+ code->flags =
+ V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int rkisp2_isp_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ struct rkisp2_isp *isp = to_rkisp2_isp(sd);
+ const struct rkisp2_mbus_info *mbus_info;
+
+ if (fse->index > 0)
+ return -EINVAL;
+
+ mbus_info = rkisp2_mbus_info_get_by_code(fse->code);
+ if (!mbus_info)
+ return -EINVAL;
+
+ if (!(mbus_info->direction & RKISP2_ISP_SD_SINK) &&
+ fse->pad == RKISP2_ISP_PAD_SINK_VIDEO)
+ return -EINVAL;
+
+ if (!(mbus_info->direction & RKISP2_ISP_SD_SRC) &&
+ fse->pad == RKISP2_ISP_PAD_SOURCE_VIDEO)
+ return -EINVAL;
+
+ fse->min_width = RKISP2_ISP_MIN_WIDTH;
+ fse->max_width = isp->rkisp2->info->max_width;
+ fse->min_height = RKISP2_ISP_MIN_HEIGHT;
+ fse->max_height = isp->rkisp2->info->max_height;
+
+ return 0;
+}
+
+static int rkisp2_isp_init_state(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state)
+{
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ struct v4l2_rect *sink_crop, *src_crop;
+
+ /* Video. */
+ sink_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ sink_fmt->width = RKISP2_DEFAULT_WIDTH;
+ sink_fmt->height = RKISP2_DEFAULT_HEIGHT;
+ sink_fmt->field = V4L2_FIELD_NONE;
+ sink_fmt->code = RKISP2_DEF_SINK_PAD_FMT;
+ sink_fmt->colorspace = V4L2_COLORSPACE_RAW;
+ sink_fmt->xfer_func = V4L2_XFER_FUNC_NONE;
+ sink_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
+ sink_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+
+ sink_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ sink_crop->width = RKISP2_DEFAULT_WIDTH;
+ sink_crop->height = RKISP2_DEFAULT_HEIGHT;
+ sink_crop->left = 0;
+ sink_crop->top = 0;
+
+ src_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ *src_fmt = *sink_fmt;
+ src_fmt->code = RKISP2_DEF_SRC_PAD_FMT;
+ src_fmt->colorspace = V4L2_COLORSPACE_SRGB;
+ src_fmt->xfer_func = V4L2_XFER_FUNC_SRGB;
+ src_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
+ src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
+
+ src_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ *src_crop = *sink_crop;
+
+ return 0;
+}
+
+static void rkisp2_isp_set_src_fmt(struct rkisp2_isp *isp,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *format)
+{
+ const struct rkisp2_mbus_info *sink_info;
+ const struct rkisp2_mbus_info *src_info;
+ struct v4l2_mbus_framefmt *sink_fmt;
+ struct v4l2_mbus_framefmt *src_fmt;
+ const struct v4l2_rect *src_crop;
+ bool set_csc;
+
+ sink_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ src_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ src_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+
+ /*
+ * Media bus code. The ISP can operate in pass-through mode (Bayer in,
+ * Bayer out or YUV in, YUV out) or process Bayer data to YUV, but
+ * can't convert from YUV to Bayer.
+ */
+ sink_info = rkisp2_mbus_info_get_by_code(sink_fmt->code);
+
+ src_fmt->code = format->code;
+ src_info = rkisp2_mbus_info_get_by_code(src_fmt->code);
+ if (!src_info || !(src_info->direction & RKISP2_ISP_SD_SRC)) {
+ src_fmt->code = RKISP2_DEF_SRC_PAD_FMT;
+ src_info = rkisp2_mbus_info_get_by_code(src_fmt->code);
+ }
+
+ if (sink_info->pixel_enc == V4L2_PIXEL_ENC_YUV &&
+ src_info->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ src_fmt->code = sink_fmt->code;
+ src_info = sink_info;
+ }
+
+ /*
+ * The source width and height must be identical to the source crop
+ * size.
+ */
+ src_fmt->width = src_crop->width;
+ src_fmt->height = src_crop->height;
+
+ /*
+ * Copy the color space for the sink pad. When converting from Bayer to
+ * YUV, default to a limited quantization range.
+ */
+ src_fmt->colorspace = sink_fmt->colorspace;
+ src_fmt->xfer_func = sink_fmt->xfer_func;
+ src_fmt->ycbcr_enc = sink_fmt->ycbcr_enc;
+
+ if (sink_info->pixel_enc == V4L2_PIXEL_ENC_BAYER &&
+ src_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
+ src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ else
+ src_fmt->quantization = sink_fmt->quantization;
+
+ /*
+ * Allow setting the source color space fields when the SET_CSC flag is
+ * set and the source format is YUV. If the sink format is YUV, don't
+ * set the color primaries, transfer function or YCbCr encoding as the
+ * ISP is bypassed in that case and passes YUV data through without
+ * modifications.
+ *
+ * The color primaries and transfer function are configured through the
+ * cross-talk matrix and tone curve respectively. Settings for those
+ * hardware blocks are conveyed through the ISP parameters buffer, as
+ * they need to combine color space information with other image tuning
+ * characteristics and can't thus be computed by the kernel based on the
+ * color space. The source pad colorspace and xfer_func fields are thus
+ * ignored by the driver, but can be set by userspace to propagate
+ * accurate color space information down the pipeline.
+ */
+ set_csc = format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC;
+
+ if (set_csc && src_info->pixel_enc == V4L2_PIXEL_ENC_YUV) {
+ if (sink_info->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ if (format->colorspace != V4L2_COLORSPACE_DEFAULT)
+ src_fmt->colorspace = format->colorspace;
+ if (format->xfer_func != V4L2_XFER_FUNC_DEFAULT)
+ src_fmt->xfer_func = format->xfer_func;
+ if (format->ycbcr_enc != V4L2_YCBCR_ENC_DEFAULT)
+ src_fmt->ycbcr_enc = format->ycbcr_enc;
+ }
+
+ if (format->quantization != V4L2_QUANTIZATION_DEFAULT)
+ src_fmt->quantization = format->quantization;
+ }
+
+ *format = *src_fmt;
+
+ /*
+ * Restore the SET_CSC flag if it was set to indicate support for the
+ * CSC setting API.
+ */
+ if (set_csc)
+ format->flags |= V4L2_MBUS_FRAMEFMT_SET_CSC;
+}
+
+static void rkisp2_isp_set_src_crop(struct rkisp2_isp *isp,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_rect *r)
+{
+ struct v4l2_mbus_framefmt *src_fmt;
+ const struct v4l2_rect *sink_crop;
+ struct v4l2_rect *src_crop;
+
+ src_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ sink_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+
+ src_crop->left = ALIGN(r->left, 2);
+ src_crop->width = ALIGN(r->width, 2);
+ src_crop->top = r->top;
+ src_crop->height = r->height;
+ rkisp2_sd_adjust_crop_rect(src_crop, sink_crop);
+
+ *r = *src_crop;
+
+ /* Propagate to out format */
+ src_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ rkisp2_isp_set_src_fmt(isp, sd_state, src_fmt);
+}
+
+static void rkisp2_isp_set_sink_crop(struct rkisp2_isp *isp,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_rect *r)
+{
+ struct v4l2_rect *sink_crop, *src_crop;
+ const struct v4l2_mbus_framefmt *sink_fmt;
+
+ sink_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ sink_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+
+ sink_crop->left = ALIGN(r->left, 2);
+ sink_crop->width = ALIGN(r->width, 2);
+ sink_crop->top = r->top;
+ sink_crop->height = r->height;
+ rkisp2_sd_adjust_crop(sink_crop, sink_fmt);
+
+ *r = *sink_crop;
+
+ /* Propagate to out crop */
+ src_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ rkisp2_isp_set_src_crop(isp, sd_state, src_crop);
+}
+
+static void rkisp2_isp_set_sink_fmt(struct rkisp2_isp *isp,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_mbus_framefmt *format)
+{
+ const struct rkisp2_mbus_info *mbus_info;
+ struct v4l2_mbus_framefmt *sink_fmt;
+ struct v4l2_rect *sink_crop;
+ bool is_yuv;
+
+ sink_fmt = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ sink_fmt->code = format->code;
+ mbus_info = rkisp2_mbus_info_get_by_code(sink_fmt->code);
+ if (!mbus_info || !(mbus_info->direction & RKISP2_ISP_SD_SINK)) {
+ sink_fmt->code = RKISP2_DEF_SINK_PAD_FMT;
+ mbus_info = rkisp2_mbus_info_get_by_code(sink_fmt->code);
+ }
+
+ sink_fmt->width = clamp_t(u32, format->width,
+ RKISP2_ISP_MIN_WIDTH,
+ isp->rkisp2->info->max_width);
+ sink_fmt->height = clamp_t(u32, format->height,
+ RKISP2_ISP_MIN_HEIGHT,
+ isp->rkisp2->info->max_height);
+
+ /*
+ * Adjust the color space fields. Accept any color primaries and
+ * transfer function for both YUV and Bayer. For YUV any YCbCr encoding
+ * and quantization range is also accepted. For Bayer formats, the YCbCr
+ * encoding isn't applicable, and the quantization range can only be
+ * full.
+ */
+ is_yuv = mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV;
+
+ sink_fmt->colorspace = format->colorspace ? :
+ (is_yuv ? V4L2_COLORSPACE_SRGB :
+ V4L2_COLORSPACE_RAW);
+ sink_fmt->xfer_func = format->xfer_func ? :
+ V4L2_MAP_XFER_FUNC_DEFAULT(sink_fmt->colorspace);
+ if (is_yuv) {
+ sink_fmt->ycbcr_enc = format->ycbcr_enc ? :
+ V4L2_MAP_YCBCR_ENC_DEFAULT(sink_fmt->colorspace);
+ sink_fmt->quantization = format->quantization ? :
+ V4L2_MAP_QUANTIZATION_DEFAULT(false, sink_fmt->colorspace,
+ sink_fmt->ycbcr_enc);
+ } else {
+ /*
+ * The YCbCr encoding isn't applicable for non-YUV formats, but
+ * V4L2 has no "no encoding" value. Hardcode it to Rec. 601, it
+ * should be ignored by userspace.
+ */
+ sink_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
+ sink_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ }
+
+ *format = *sink_fmt;
+
+ /* Propagate to in crop */
+ sink_crop = v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ rkisp2_isp_set_sink_crop(isp, sd_state, sink_crop);
+}
+
+static int rkisp2_isp_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct rkisp2_isp *isp = to_rkisp2_isp(sd);
+
+ if (fmt->pad == RKISP2_ISP_PAD_SINK_VIDEO)
+ rkisp2_isp_set_sink_fmt(isp, sd_state, &fmt->format);
+ else if (fmt->pad == RKISP2_ISP_PAD_SOURCE_VIDEO)
+ rkisp2_isp_set_src_fmt(isp, sd_state, &fmt->format);
+ else
+ fmt->format = *v4l2_subdev_state_get_format(sd_state,
+ fmt->pad);
+
+ return 0;
+}
+
+static int rkisp2_isp_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ int ret = 0;
+
+ if (sel->pad != RKISP2_ISP_PAD_SOURCE_VIDEO &&
+ sel->pad != RKISP2_ISP_PAD_SINK_VIDEO)
+ return -EINVAL;
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ if (sel->pad == RKISP2_ISP_PAD_SINK_VIDEO) {
+ struct v4l2_mbus_framefmt *fmt;
+
+ fmt = v4l2_subdev_state_get_format(sd_state, sel->pad);
+ sel->r.height = fmt->height;
+ sel->r.width = fmt->width;
+ sel->r.left = 0;
+ sel->r.top = 0;
+ } else {
+ sel->r = *v4l2_subdev_state_get_crop(sd_state,
+ RKISP2_ISP_PAD_SINK_VIDEO);
+ }
+ break;
+
+ case V4L2_SEL_TGT_CROP:
+ sel->r = *v4l2_subdev_state_get_crop(sd_state, sel->pad);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int rkisp2_isp_set_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct rkisp2_isp *isp = to_rkisp2_isp(sd);
+ int ret = 0;
+
+ if (sel->target != V4L2_SEL_TGT_CROP)
+ return -EINVAL;
+
+ dev_dbg(isp->rkisp2->dev, "%s: pad: %d sel(%d,%d)/%ux%u\n", __func__,
+ sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
+
+ if (sel->pad == RKISP2_ISP_PAD_SINK_VIDEO)
+ rkisp2_isp_set_sink_crop(isp, sd_state, &sel->r);
+ else if (sel->pad == RKISP2_ISP_PAD_SOURCE_VIDEO)
+ rkisp2_isp_set_src_crop(isp, sd_state, &sel->r);
+ else
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static int rkisp2_subdev_link_validate(struct media_link *link)
+{
+ return v4l2_subdev_link_validate(link);
+}
+
+static const struct v4l2_subdev_pad_ops rkisp2_isp_pad_ops = {
+ .enum_mbus_code = rkisp2_isp_enum_mbus_code,
+ .enum_frame_size = rkisp2_isp_enum_frame_size,
+ .get_selection = rkisp2_isp_get_selection,
+ .set_selection = rkisp2_isp_set_selection,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = rkisp2_isp_set_fmt,
+ .link_validate = v4l2_subdev_link_validate_default,
+};
+
+/* ----------------------------------------------------------------------------
+ * Stream operations
+ */
+
+static int rkisp2_isp_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct rkisp2_isp *isp = to_rkisp2_isp(sd);
+ struct rkisp2_device *rkisp2 = isp->rkisp2;
+ struct v4l2_subdev_state *sd_state;
+ struct media_pad *source_pad = NULL;
+ struct media_pad *sink_pad = NULL;
+ int ret;
+
+ if (!enable) {
+ if (rkisp2->source)
+ v4l2_subdev_call(rkisp2->source, video, s_stream,
+ false);
+ rkisp2_isp_stop(isp);
+ return 0;
+ }
+
+ sink_pad = &isp->pads[RKISP2_ISP_PAD_SINK_VIDEO];
+ source_pad = media_pad_remote_pad_unique(sink_pad);
+ if (IS_ERR(source_pad)) {
+ dev_dbg(rkisp2->dev, "Failed to get source for ISP: %ld\n",
+ PTR_ERR(source_pad));
+ return -EPIPE;
+ }
+
+ if (is_media_entity_v4l2_subdev(source_pad->entity)) {
+ rkisp2->source =
+ media_entity_to_v4l2_subdev(source_pad->entity);
+ if (!rkisp2->source) {
+ /* This should really not happen, so is not worth a message. */
+ return -EPIPE;
+ }
+ } else {
+ dev_dbg(rkisp2->dev, "ISP source is not a v4l2 subdev\n");
+ rkisp2->source = NULL;
+ }
+
+ isp->frame_sequence = -1;
+
+ sd_state = v4l2_subdev_lock_and_get_active_state(sd);
+
+ ret = rkisp2_config_cif(isp, sd_state);
+ if (ret)
+ goto out_unlock;
+
+ ret = rkisp2_isp_start(isp, sd_state, source_pad);
+ if (ret)
+ goto out_unlock;
+
+ if (rkisp2->source) {
+ ret = v4l2_subdev_call(rkisp2->source, video, s_stream, true);
+ if (ret) {
+ rkisp2_isp_stop(isp);
+ goto out_unlock;
+ }
+ }
+
+out_unlock:
+ v4l2_subdev_unlock_state(sd_state);
+ return ret;
+}
+
+static int rkisp2_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
+ struct v4l2_event_subscription *sub)
+{
+ if (sub->type != V4L2_EVENT_FRAME_SYNC)
+ return -EINVAL;
+
+ /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
+ if (sub->id != 0)
+ return -EINVAL;
+
+ return v4l2_event_subscribe(fh, sub, 0, NULL);
+}
+
+static const struct media_entity_operations rkisp2_isp_media_ops = {
+ .link_validate = rkisp2_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_video_ops rkisp2_isp_video_ops = {
+ .s_stream = rkisp2_isp_s_stream,
+};
+
+//TODO: add .s_power?
+static const struct v4l2_subdev_core_ops rkisp2_isp_core_ops = {
+ .subscribe_event = rkisp2_isp_subs_evt,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static const struct v4l2_subdev_ops rkisp2_isp_ops = {
+ .core = &rkisp2_isp_core_ops,
+ .video = &rkisp2_isp_video_ops,
+ .pad = &rkisp2_isp_pad_ops,
+};
+
+static const struct v4l2_subdev_internal_ops rkisp2_isp_internal_ops = {
+ .init_state = rkisp2_isp_init_state,
+};
+
+int rkisp2_isp_register(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_isp *isp = &rkisp2->isp;
+ struct media_pad *pads = isp->pads;
+ struct v4l2_subdev *sd = &isp->sd;
+ int ret;
+
+ isp->rkisp2 = rkisp2;
+
+ v4l2_subdev_init(sd, &rkisp2_isp_ops);
+ sd->internal_ops = &rkisp2_isp_internal_ops;
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+ sd->entity.ops = &rkisp2_isp_media_ops;
+ sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
+ sd->owner = THIS_MODULE;
+ strscpy(sd->name, RKISP2_ISP_DEV_NAME, sizeof(sd->name));
+
+ pads[RKISP2_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK |
+ MEDIA_PAD_FL_MUST_CONNECT;
+ pads[RKISP2_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
+
+ ret = media_entity_pads_init(&sd->entity, RKISP2_ISP_PAD_MAX, pads);
+ if (ret)
+ goto err_entity_cleanup;
+
+ ret = v4l2_subdev_init_finalize(sd);
+ if (ret)
+ goto err_subdev_cleanup;
+
+ ret = v4l2_device_register_subdev(&rkisp2->v4l2_dev, sd);
+ if (ret) {
+ dev_err(rkisp2->dev, "Failed to register isp subdev\n");
+ goto err_subdev_cleanup;
+ }
+
+ return 0;
+
+err_subdev_cleanup:
+ v4l2_subdev_cleanup(sd);
+err_entity_cleanup:
+ media_entity_cleanup(&sd->entity);
+ isp->sd.v4l2_dev = NULL;
+ return ret;
+}
+
+void rkisp2_isp_unregister(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_isp *isp = &rkisp2->isp;
+
+ if (!isp->sd.v4l2_dev)
+ return;
+
+ v4l2_device_unregister_subdev(&isp->sd);
+ v4l2_subdev_cleanup(&isp->sd);
+ media_entity_cleanup(&isp->sd.entity);
+}
+
+/* ----------------------------------------------------------------------------
+ * Interrupt handlers
+ */
+
+static void rkisp2_isp_queue_event_sof(struct rkisp2_isp *isp)
+{
+ struct v4l2_event event = {
+ .type = V4L2_EVENT_FRAME_SYNC,
+ };
+
+ event.u.frame_sync.frame_sequence = isp->frame_sequence;
+ v4l2_event_queue(isp->sd.devnode, &event);
+}
+
+irqreturn_t rkisp2_isp_isr(int irq, void *ctx)
+{
+ struct device *dev = ctx;
+ struct rkisp2_device *rkisp2 = dev_get_drvdata(dev);
+ u32 status, isp_err;
+
+ if (!rkisp2->irqs_enabled)
+ return IRQ_NONE;
+
+ status = rkisp2_read(rkisp2, RKISP2_CIF_ISP_MIS);
+ if (!status)
+ return IRQ_NONE;
+
+ /* Vertical sync signal, starting generating new frame */
+ if (status & RKISP2_CIF_ISP_V_START) {
+ rkisp2->isp.frame_sequence++;
+ rkisp2_isp_queue_event_sof(&rkisp2->isp);
+ if (status & RKISP2_CIF_ISP_FRAME) {
+ WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n");
+ rkisp2->debug.irq_delay++;
+ }
+ }
+ if (status & RKISP2_CIF_ISP_PIC_SIZE_ERROR) {
+ /* Clear pic_size_error */
+ isp_err = rkisp2_read(rkisp2, RKISP2_CIF_ISP_ERR);
+ if (isp_err & RKISP2_CIF_ISP_ERR_INFORM_SIZE)
+ rkisp2->debug.inform_size_error++;
+ if (isp_err & RKISP2_CIF_ISP_ERR_IS_SIZE)
+ rkisp2->debug.img_stabilization_size_error++;
+ if (isp_err & RKISP2_CIF_ISP_ERR_OUTFORM_SIZE)
+ rkisp2->debug.outform_size_error++;
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ERR_CLR, isp_err);
+ } else if (status & RKISP2_CIF_ISP_DATA_LOSS) {
+ /* keep track of data_loss in debugfs */
+ rkisp2->debug.data_loss++;
+ }
+
+ if (status & RKISP2_CIF_ISP_FRAME)
+ rkisp2->debug.complete_frames++;
+
+ rkisp2_write(rkisp2, RKISP2_CIF_ISP_ICR, status);
+
+ return IRQ_HANDLED;
+}
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
new file mode 100644
index 000000000000..883bdb7c2a61
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
@@ -0,0 +1,2588 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+ *
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _RKISP2_REGS_V2X_H
+#define _RKISP2_REGS_V2X_H
+
+#define CTRL_BASE 0x00000000
+#define CTRL_VI_ISP_EN (CTRL_BASE + 0x00000)
+#define CTRL_VI_ISP_PATH (CTRL_BASE + 0x00004)
+#define CTRL_VI_ID (CTRL_BASE + 0x00008)
+#define CTRL_VI_ISP_CLK_CTRL (CTRL_BASE + 0x0000c)
+#define CTRL_VI_ICCL (CTRL_BASE + 0x00010)
+#define CTRL_VI_IRCL (CTRL_BASE + 0x00014)
+#define CTRL_VI_DPCL (CTRL_BASE + 0x00018)
+#define CTRL_SWS_CFG (CTRL_BASE + 0x0001c)
+#define LVDS_CTRL (CTRL_BASE + 0x00020)
+#define LVDS_SAV_EAV_ACT (CTRL_BASE + 0x00024)
+#define LVDS_SAV_EAV_BLK (CTRL_BASE + 0x00028)
+
+#define IMG_EFF_BASE 0x00000200
+#define IMG_EFF_CTRL (IMG_EFF_BASE + 0x00000)
+#define IMG_EFF_COLOR_SEL (IMG_EFF_BASE + 0x00004)
+#define IMG_EFF_MAT_1 (IMG_EFF_BASE + 0x00008)
+#define IMG_EFF_MAT_2 (IMG_EFF_BASE + 0x0000c)
+#define IMG_EFF_MAT_3 (IMG_EFF_BASE + 0x00010)
+#define IMG_EFF_MAT_4 (IMG_EFF_BASE + 0x00014)
+#define IMG_EFF_MAT_5 (IMG_EFF_BASE + 0x00018)
+#define IMG_EFF_TINT (IMG_EFF_BASE + 0x0001c)
+#define IMG_EFF_CTRL_SHD (IMG_EFF_BASE + 0x00020)
+#define IMG_EFF_SHARPEN (IMG_EFF_BASE + 0x00024)
+#define IMG_EFF_RKSHARP_CTRL (IMG_EFF_BASE + 0x00030)
+#define IMG_EFF_RKSHARP_YAVG_THR (IMG_EFF_BASE + 0x00034)
+#define IMG_EFF_RKSHARP_DELTA_P0_P1 (IMG_EFF_BASE + 0x00038)
+#define IMG_EFF_RKSHARP_DELTA_P2_P3 (IMG_EFF_BASE + 0x0003c)
+#define IMG_EFF_RKSHARP_DELTA_P4 (IMG_EFF_BASE + 0x00040)
+#define IMG_EFF_RKSHARP_NPIXEL_P0_P1_P2_P3 (IMG_EFF_BASE + 0x00044)
+#define IMG_EFF_RKSHARP_NPIXEL_P4 (IMG_EFF_BASE + 0x00048)
+#define IMG_EFF_RKSHARP_GAUSS_FLAT_COE1 (IMG_EFF_BASE + 0x0004c)
+#define IMG_EFF_RKSHARP_GAUSS_FLAT_COE2 (IMG_EFF_BASE + 0x00050)
+#define IMG_EFF_RKSHARP_GAUSS_FLAT_COE3 (IMG_EFF_BASE + 0x00054)
+#define IMG_EFF_RKSHARP_GAUSS_NOISE_COE1 (IMG_EFF_BASE + 0x00058)
+#define IMG_EFF_RKSHARP_GAUSS_NOISE_COE2 (IMG_EFF_BASE + 0x0005c)
+#define IMG_EFF_RKSHARP_GAUSS_NOISE_COE3 (IMG_EFF_BASE + 0x00060)
+#define IMG_EFF_RKSHARP_GAUSS_OTHER_COE1 (IMG_EFF_BASE + 0x00064)
+#define IMG_EFF_RKSHARP_GAUSS_OTHER_COE2 (IMG_EFF_BASE + 0x00068)
+#define IMG_EFF_RKSHARP_GAUSS_OTHER_COE3 (IMG_EFF_BASE + 0x0006c)
+#define IMG_EFF_RKSHARP_LINE1_FILTER_COE1 (IMG_EFF_BASE + 0x00070)
+#define IMG_EFF_RKSHARP_LINE1_FILTER_COE2 (IMG_EFF_BASE + 0x00074)
+#define IMG_EFF_RKSHARP_LINE2_FILTER_COE1 (IMG_EFF_BASE + 0x00078)
+#define IMG_EFF_RKSHARP_LINE2_FILTER_COE2 (IMG_EFF_BASE + 0x0007c)
+#define IMG_EFF_RKSHARP_LINE2_FILTER_COE3 (IMG_EFF_BASE + 0x00080)
+#define IMG_EFF_RKSHARP_LINE3_FILTER_COE1 (IMG_EFF_BASE + 0x00084)
+#define IMG_EFF_RKSHARP_LINE3_FILTER_COE2 (IMG_EFF_BASE + 0x00088)
+#define IMG_EFF_RKSHARP_GRAD_SEQ_P0_P1 (IMG_EFF_BASE + 0x0008c)
+#define IMG_EFF_RKSHARP_GRAD_SEQ_P2_P3 (IMG_EFF_BASE + 0x00090)
+#define IMG_EFF_RKSHARP_SHARP_FACTOR_P0_P1_P2 (IMG_EFF_BASE + 0x00094)
+#define IMG_EFF_RKSHARP_SHARP_FACTOR_P3_P4 (IMG_EFF_BASE + 0x00098)
+#define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE11_COE14 (IMG_EFF_BASE + 0x0009c)
+#define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE15_COE23 (IMG_EFF_BASE + 0x000a0)
+#define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE24_COE32 (IMG_EFF_BASE + 0x000a4)
+#define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE33_COE35 (IMG_EFF_BASE + 0x000a8)
+#define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE11_COE14 (IMG_EFF_BASE + 0x000ac)
+#define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE15_COE23 (IMG_EFF_BASE + 0x000b0)
+#define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE24_COE32 (IMG_EFF_BASE + 0x000b4)
+#define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE33_COE35 (IMG_EFF_BASE + 0x000b8)
+#define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE11_COE14 (IMG_EFF_BASE + 0x000bc)
+#define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE15_COE23 (IMG_EFF_BASE + 0x000c0)
+#define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE24_COE32 (IMG_EFF_BASE + 0x000c4)
+#define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE33_COE35 (IMG_EFF_BASE + 0x000c8)
+
+#define SUPER_IMP_BASE 0x00000300
+#define SUPER_IMP_CTRL (SUPER_IMP_BASE + 0x00000)
+#define SUPER_IMP_OFFSET_X (SUPER_IMP_BASE + 0x00004)
+#define SUPER_IMP_OFFSET_Y (SUPER_IMP_BASE + 0x00008)
+#define SUPER_IMP_COLOR_Y (SUPER_IMP_BASE + 0x0000c)
+#define SUPER_IMP_COLOR_CB (SUPER_IMP_BASE + 0x00010)
+#define SUPER_IMP_COLOR_CR (SUPER_IMP_BASE + 0x00014)
+
+#define ISP_BASE 0x00000400
+#define ISP_CTRL (ISP_BASE + 0x00000)
+#define ISP_ACQ_PROP (ISP_BASE + 0x00004)
+#define ISP_CTRL1 (ISP_BASE + 0x00004)
+#define ISP_ACQ_H_OFFS (ISP_BASE + 0x00008)
+#define ISP_ACQ_V_OFFS (ISP_BASE + 0x0000c)
+#define ISP_ACQ_H_SIZE (ISP_BASE + 0x00010)
+#define ISP_ACQ_V_SIZE (ISP_BASE + 0x00014)
+#define ISP_ACQ_NR_FRAMES (ISP_BASE + 0x00018)
+#define ISP_GAMMA_DX_LO (ISP_BASE + 0x0001c)
+#define ISP_GAMMA_DX_HI (ISP_BASE + 0x00020)
+#define ISP_GAMMA_R_Y_0 (ISP_BASE + 0x00024)
+#define ISP_GAMMA_R_Y_1 (ISP_BASE + 0x00028)
+#define ISP_GAMMA_R_Y_2 (ISP_BASE + 0x0002c)
+#define ISP_GAMMA_R_Y_3 (ISP_BASE + 0x00030)
+#define ISP_GAMMA_R_Y_4 (ISP_BASE + 0x00034)
+#define ISP_GAMMA_R_Y_5 (ISP_BASE + 0x00038)
+#define ISP_GAMMA_R_Y_6 (ISP_BASE + 0x0003c)
+#define ISP_GAMMA_R_Y_7 (ISP_BASE + 0x00040)
+#define ISP_GAMMA_R_Y_8 (ISP_BASE + 0x00044)
+#define ISP_GAMMA_R_Y_9 (ISP_BASE + 0x00048)
+#define ISP_GAMMA_R_Y_10 (ISP_BASE + 0x0004c)
+#define ISP_GAMMA_R_Y_11 (ISP_BASE + 0x00050)
+#define ISP_GAMMA_R_Y_12 (ISP_BASE + 0x00054)
+#define ISP_GAMMA_R_Y_13 (ISP_BASE + 0x00058)
+#define ISP_GAMMA_R_Y_14 (ISP_BASE + 0x0005c)
+#define ISP_GAMMA_R_Y_15 (ISP_BASE + 0x00060)
+#define ISP_GAMMA_R_Y_16 (ISP_BASE + 0x00064)
+#define ISP_GAMMA_G_Y_0 (ISP_BASE + 0x00068)
+#define ISP_GAMMA_G_Y_1 (ISP_BASE + 0x0006c)
+#define ISP_GAMMA_G_Y_2 (ISP_BASE + 0x00070)
+#define ISP_GAMMA_G_Y_3 (ISP_BASE + 0x00074)
+#define ISP_GAMMA_G_Y_4 (ISP_BASE + 0x00078)
+#define ISP_GAMMA_G_Y_5 (ISP_BASE + 0x0007c)
+#define ISP_GAMMA_G_Y_6 (ISP_BASE + 0x00080)
+#define ISP_GAMMA_G_Y_7 (ISP_BASE + 0x00084)
+#define ISP_GAMMA_G_Y_8 (ISP_BASE + 0x00088)
+#define ISP_GAMMA_G_Y_9 (ISP_BASE + 0x0008c)
+#define ISP_GAMMA_G_Y_10 (ISP_BASE + 0x00090)
+#define ISP_GAMMA_G_Y_11 (ISP_BASE + 0x00094)
+#define ISP_GAMMA_G_Y_12 (ISP_BASE + 0x00098)
+#define ISP_GAMMA_G_Y_13 (ISP_BASE + 0x0009c)
+#define ISP_GAMMA_G_Y_14 (ISP_BASE + 0x000a0)
+#define ISP_GAMMA_G_Y_15 (ISP_BASE + 0x000a4)
+#define ISP_GAMMA_G_Y_16 (ISP_BASE + 0x000a8)
+#define ISP_GAMMA_B_Y_0 (ISP_BASE + 0x000ac)
+#define ISP_GAMMA_B_Y_1 (ISP_BASE + 0x000b0)
+#define ISP_GAMMA_B_Y_2 (ISP_BASE + 0x000b4)
+#define ISP_GAMMA_B_Y_3 (ISP_BASE + 0x000b8)
+#define ISP_GAMMA_B_Y_4 (ISP_BASE + 0x000bc)
+#define ISP_GAMMA_B_Y_5 (ISP_BASE + 0x000c0)
+#define ISP_GAMMA_B_Y_6 (ISP_BASE + 0x000c4)
+#define ISP_GAMMA_B_Y_7 (ISP_BASE + 0x000c8)
+#define ISP_GAMMA_B_Y_8 (ISP_BASE + 0x000cc)
+#define ISP_GAMMA_B_Y_9 (ISP_BASE + 0x000d0)
+#define ISP_GAMMA_B_Y_10 (ISP_BASE + 0x000d4)
+#define ISP_GAMMA_B_Y_11 (ISP_BASE + 0x000d8)
+#define ISP_GAMMA_B_Y_12 (ISP_BASE + 0x000dc)
+#define ISP_GAMMA_B_Y_13 (ISP_BASE + 0x000e0)
+#define ISP_GAMMA_B_Y_14 (ISP_BASE + 0x000e4)
+#define ISP_GAMMA_B_Y_15 (ISP_BASE + 0x000e8)
+#define ISP_GAMMA_B_Y_16 (ISP_BASE + 0x000ec)
+
+#define ISP_AWB_PROP (ISP_BASE + 0x00110)
+#define ISP_AWB_SIZE (ISP_BASE + 0x00114)
+#define ISP_AWB_OFFS (ISP_BASE + 0x00118)
+#define ISP_AWB_REF (ISP_BASE + 0x0011c)
+#define ISP_AWB_THRESH (ISP_BASE + 0x00120)
+#define ISP_X_COOR_12 (ISP_BASE + 0x00124)
+#define ISP_X_COOR_34 (ISP_BASE + 0x00128)
+#define ISP_AWB_WHITE_CNT (ISP_BASE + 0x0012c)
+#define ISP_AWB_MEAN (ISP_BASE + 0x00130)
+#define ISP_DEGAIN (ISP_BASE + 0x00134)
+#define ISP_AWB_GAIN_G (ISP_BASE + 0x00138)
+#define ISP_AWB_GAIN_RB (ISP_BASE + 0x0013c)
+#define ISP_REGION0_LINE0 (ISP_BASE + 0x00140)
+#define ISP_WP_CNT_REGION0 (ISP_BASE + 0x00160)
+#define ISP_WP_CNT_REGION1 (ISP_BASE + 0x00164)
+#define ISP_WP_CNT_REGION2 (ISP_BASE + 0x00168)
+#define ISP_WP_CNT_REGION3 (ISP_BASE + 0x0016c)
+
+#define ISP21_AWB_GAIN0_G (ISP_BASE + 0x00138)
+#define ISP21_AWB_GAIN0_RB (ISP_BASE + 0x0013c)
+#define ISP21_AWB_GAIN1_G (ISP_BASE + 0x00140)
+#define ISP21_AWB_GAIN1_RB (ISP_BASE + 0x00144)
+#define ISP21_AWB_GAIN2_G (ISP_BASE + 0x00148)
+#define ISP21_AWB_GAIN2_RB (ISP_BASE + 0x0014c)
+
+#define ISP_CC_COEFF_0 (ISP_BASE + 0x00170)
+#define ISP_CC_COEFF_1 (ISP_BASE + 0x00174)
+#define ISP_CC_COEFF_2 (ISP_BASE + 0x00178)
+#define ISP_CC_COEFF_3 (ISP_BASE + 0x0017c)
+#define ISP_CC_COEFF_4 (ISP_BASE + 0x00180)
+#define ISP_CC_COEFF_5 (ISP_BASE + 0x00184)
+#define ISP_CC_COEFF_6 (ISP_BASE + 0x00188)
+#define ISP_CC_COEFF_7 (ISP_BASE + 0x0018c)
+#define ISP_CC_COEFF_8 (ISP_BASE + 0x00190)
+#define ISP_OUT_H_OFFS (ISP_BASE + 0x00194)
+#define ISP_OUT_V_OFFS (ISP_BASE + 0x00198)
+#define ISP_OUT_H_SIZE (ISP_BASE + 0x0019c)
+#define ISP_OUT_V_SIZE (ISP_BASE + 0x001a0)
+#define ISP_DEMOSAIC (ISP_BASE + 0x001a4)
+#define ISP_FLAGS_SHD (ISP_BASE + 0x001a8)
+#define ISP_OUT_H_OFFS_SHD (ISP_BASE + 0x001ac)
+#define ISP_OUT_V_OFFS_SHD (ISP_BASE + 0x001b0)
+#define ISP_OUT_H_SIZE_SHD (ISP_BASE + 0x001b4)
+#define ISP_OUT_V_SIZE_SHD (ISP_BASE + 0x001b8)
+#define ISP_ISP_IMSC (ISP_BASE + 0x001bc)
+#define ISP_ISP_RIS (ISP_BASE + 0x001c0)
+#define ISP_ISP_MIS (ISP_BASE + 0x001c4)
+#define ISP_ISP_ICR (ISP_BASE + 0x001c8)
+#define ISP_ISP_ISR (ISP_BASE + 0x001cc)
+
+#define ISP_ISP3A_IMSC (ISP_BASE + 0x001d0)
+#define ISP_ISP3A_RIS (ISP_BASE + 0x001d4)
+#define ISP_ISP3A_MIS (ISP_BASE + 0x001d8)
+#define ISP_ISP3A_ICR (ISP_BASE + 0x001dc)
+
+#define ISP_ERR (ISP_BASE + 0x0023c)
+#define ISP_ERR_CLR (ISP_BASE + 0x00240)
+#define ISP_FRAME_COUNT (ISP_BASE + 0x00244)
+#define ISP_CT_OFFSET_R (ISP_BASE + 0x00248)
+#define ISP_CT_OFFSET_G (ISP_BASE + 0x0024c)
+#define ISP_CT_OFFSET_B (ISP_BASE + 0x00250)
+#define ISP_DEBUG1 (ISP_BASE + 0x00254)
+
+#define ISP_FLASH_BASE 0x00000660
+#define ISP_FLASH_CMD (ISP_FLASH_BASE + 0x00000)
+#define ISP_FLASH_CONFIG (ISP_FLASH_BASE + 0x00004)
+#define ISP_FLASH_PREDIV (ISP_FLASH_BASE + 0x00008)
+#define ISP_FLASH_DELAY (ISP_FLASH_BASE + 0x0000c)
+#define ISP_FLASH_TIME (ISP_FLASH_BASE + 0x00010)
+#define ISP_FLASH_MAXP (ISP_FLASH_BASE + 0x00014)
+
+#define ISP_SHUTTER_BASE 0x00000680
+#define ISP_SHUTTER_CTRL (ISP_SHUTTER_BASE + 0x00000)
+#define ISP_SHUTTER_PREDIV (ISP_SHUTTER_BASE + 0x00004)
+#define ISP_SHUTTER_DELAY (ISP_SHUTTER_BASE + 0x00008)
+#define ISP_SHUTTER_TIME (ISP_SHUTTER_BASE + 0x0000c)
+
+#define ISP_CCM_BASE 0x00000700
+#define ISP_CCM_CTRL (ISP_CCM_BASE + 0x00000)
+#define ISP_CCM_COEFF0_R (ISP_CCM_BASE + 0x00004)
+#define ISP_CCM_COEFF1_R (ISP_CCM_BASE + 0x00008)
+#define ISP_CCM_COEFF0_G (ISP_CCM_BASE + 0x0000c)
+#define ISP_CCM_COEFF1_G (ISP_CCM_BASE + 0x00010)
+#define ISP_CCM_COEFF0_B (ISP_CCM_BASE + 0x00014)
+#define ISP_CCM_COEFF1_B (ISP_CCM_BASE + 0x00018)
+#define ISP_CCM_COEFF0_Y (ISP_CCM_BASE + 0x0001c)
+#define ISP_CCM_COEFF1_Y (ISP_CCM_BASE + 0x00020)
+#define ISP_CCM_ALP_Y0 (ISP_CCM_BASE + 0x00024)
+#define ISP_CCM_ALP_Y1 (ISP_CCM_BASE + 0x00028)
+#define ISP_CCM_ALP_Y2 (ISP_CCM_BASE + 0x0002c)
+#define ISP_CCM_ALP_Y3 (ISP_CCM_BASE + 0x00030)
+#define ISP_CCM_ALP_Y4 (ISP_CCM_BASE + 0x00034)
+#define ISP_CCM_ALP_Y5 (ISP_CCM_BASE + 0x00038)
+#define ISP_CCM_ALP_Y6 (ISP_CCM_BASE + 0x0003c)
+#define ISP_CCM_ALP_Y7 (ISP_CCM_BASE + 0x00040)
+#define ISP_CCM_ALP_Y8 (ISP_CCM_BASE + 0x00044)
+#define ISP_CCM_BOUND_BIT (ISP_CCM_BASE + 0x00048)
+
+#define CPROC_BASE 0x00000800
+#define CPROC_CTRL (CPROC_BASE + 0x00000)
+#define CPROC_CONTRAST (CPROC_BASE + 0x00004)
+#define CPROC_BRIGHTNESS (CPROC_BASE + 0x00008)
+#define CPROC_SATURATION (CPROC_BASE + 0x0000c)
+#define CPROC_HUE (CPROC_BASE + 0x00010)
+
+#define DUAL_CROP_BASE 0x00000880
+#define DUAL_CROP_CTRL (DUAL_CROP_BASE + 0x00000)
+#define DUAL_CROP_M_H_OFFS (DUAL_CROP_BASE + 0x00004)
+#define DUAL_CROP_M_V_OFFS (DUAL_CROP_BASE + 0x00008)
+#define DUAL_CROP_M_H_SIZE (DUAL_CROP_BASE + 0x0000c)
+#define DUAL_CROP_M_V_SIZE (DUAL_CROP_BASE + 0x00010)
+#define DUAL_CROP_S_H_OFFS (DUAL_CROP_BASE + 0x00014)
+#define DUAL_CROP_S_V_OFFS (DUAL_CROP_BASE + 0x00018)
+#define DUAL_CROP_S_H_SIZE (DUAL_CROP_BASE + 0x0001c)
+#define DUAL_CROP_S_V_SIZE (DUAL_CROP_BASE + 0x00020)
+
+#define ISP_GAMMA_OUT_BASE 0x00000900
+#define ISP_GAMMA_OUT_CTRL (ISP_GAMMA_OUT_BASE + 0x00000)
+#define ISP_GAMMA_OUT_OFFSET (ISP_GAMMA_OUT_BASE + 0x00004)
+#define ISP_GAMMA_OUT_Y0 (ISP_GAMMA_OUT_BASE + 0x00010)
+#define ISP_GAMMA_OUT_Y1 (ISP_GAMMA_OUT_BASE + 0x00014)
+#define ISP_GAMMA_OUT_Y2 (ISP_GAMMA_OUT_BASE + 0x00018)
+#define ISP_GAMMA_OUT_Y3 (ISP_GAMMA_OUT_BASE + 0x0001c)
+#define ISP_GAMMA_OUT_Y4 (ISP_GAMMA_OUT_BASE + 0x00020)
+#define ISP_GAMMA_OUT_Y5 (ISP_GAMMA_OUT_BASE + 0x00024)
+#define ISP_GAMMA_OUT_Y6 (ISP_GAMMA_OUT_BASE + 0x00028)
+#define ISP_GAMMA_OUT_Y7 (ISP_GAMMA_OUT_BASE + 0x0002c)
+#define ISP_GAMMA_OUT_Y8 (ISP_GAMMA_OUT_BASE + 0x00030)
+#define ISP_GAMMA_OUT_Y9 (ISP_GAMMA_OUT_BASE + 0x00034)
+#define ISP_GAMMA_OUT_Y10 (ISP_GAMMA_OUT_BASE + 0x00038)
+#define ISP_GAMMA_OUT_Y11 (ISP_GAMMA_OUT_BASE + 0x0003c)
+#define ISP_GAMMA_OUT_Y12 (ISP_GAMMA_OUT_BASE + 0x00040)
+#define ISP_GAMMA_OUT_Y13 (ISP_GAMMA_OUT_BASE + 0x00044)
+#define ISP_GAMMA_OUT_Y14 (ISP_GAMMA_OUT_BASE + 0x00048)
+#define ISP_GAMMA_OUT_Y15 (ISP_GAMMA_OUT_BASE + 0x0004c)
+#define ISP_GAMMA_OUT_Y16 (ISP_GAMMA_OUT_BASE + 0x00050)
+#define ISP_GAMMA_OUT_Y17 (ISP_GAMMA_OUT_BASE + 0x00054)
+#define ISP_GAMMA_OUT_Y18 (ISP_GAMMA_OUT_BASE + 0x00058)
+#define ISP_GAMMA_OUT_Y19 (ISP_GAMMA_OUT_BASE + 0x0005c)
+#define ISP_GAMMA_OUT_Y20 (ISP_GAMMA_OUT_BASE + 0x00060)
+#define ISP_GAMMA_OUT_Y21 (ISP_GAMMA_OUT_BASE + 0x00064)
+#define ISP_GAMMA_OUT_Y22 (ISP_GAMMA_OUT_BASE + 0x00068)
+#define ISP_GAMMA_OUT_Y23 (ISP_GAMMA_OUT_BASE + 0x0006c)
+#define ISP_GAMMA_OUT_Y24 (ISP_GAMMA_OUT_BASE + 0x00070)
+#define ISP_GAMMA_OUT_Y25 (ISP_GAMMA_OUT_BASE + 0x00074)
+#define ISP_GAMMA_OUT_Y26 (ISP_GAMMA_OUT_BASE + 0x00078)
+#define ISP_GAMMA_OUT_Y27 (ISP_GAMMA_OUT_BASE + 0x0007c)
+#define ISP_GAMMA_OUT_Y28 (ISP_GAMMA_OUT_BASE + 0x00080)
+#define ISP_GAMMA_OUT_Y29 (ISP_GAMMA_OUT_BASE + 0x00084)
+#define ISP_GAMMA_OUT_Y30 (ISP_GAMMA_OUT_BASE + 0x00088)
+#define ISP_GAMMA_OUT_Y31 (ISP_GAMMA_OUT_BASE + 0x0008c)
+#define ISP_GAMMA_OUT_Y32 (ISP_GAMMA_OUT_BASE + 0x00090)
+#define ISP_GAMMA_OUT_Y33 (ISP_GAMMA_OUT_BASE + 0x00094)
+#define ISP_GAMMA_OUT_Y34 (ISP_GAMMA_OUT_BASE + 0x00098)
+#define ISP_GAMMA_OUT_Y35 (ISP_GAMMA_OUT_BASE + 0x0009c)
+#define ISP_GAMMA_OUT_Y36 (ISP_GAMMA_OUT_BASE + 0x000a0)
+#define ISP_GAMMA_OUT_Y37 (ISP_GAMMA_OUT_BASE + 0x000a4)
+#define ISP_GAMMA_OUT_Y38 (ISP_GAMMA_OUT_BASE + 0x000a8)
+#define ISP_GAMMA_OUT_Y39 (ISP_GAMMA_OUT_BASE + 0x000ac)
+#define ISP_GAMMA_OUT_Y40 (ISP_GAMMA_OUT_BASE + 0x000b0)
+
+#define MAIN_RESIZE_BASE 0x00000C00
+#define MAIN_RESIZE_CTRL (MAIN_RESIZE_BASE + 0x00000)
+#define MAIN_RESIZE_SCALE_HY (MAIN_RESIZE_BASE + 0x00004)
+#define MAIN_RESIZE_SCALE_HCB (MAIN_RESIZE_BASE + 0x00008)
+#define MAIN_RESIZE_SCALE_HCR (MAIN_RESIZE_BASE + 0x0000c)
+#define MAIN_RESIZE_SCALE_VY (MAIN_RESIZE_BASE + 0x00010)
+#define MAIN_RESIZE_SCALE_VC (MAIN_RESIZE_BASE + 0x00014)
+#define MAIN_RESIZE_PHASE_HY (MAIN_RESIZE_BASE + 0x00018)
+#define MAIN_RESIZE_PHASE_HC (MAIN_RESIZE_BASE + 0x0001c)
+#define MAIN_RESIZE_PHASE_VY (MAIN_RESIZE_BASE + 0x00020)
+#define MAIN_RESIZE_PHASE_VC (MAIN_RESIZE_BASE + 0x00024)
+#define MAIN_RESIZE_SCALE_LUT_ADDR (MAIN_RESIZE_BASE + 0x00028)
+#define MAIN_RESIZE_SCALE_LUT (MAIN_RESIZE_BASE + 0x0002c)
+#define MAIN_RESIZE_CTRL_SHD (MAIN_RESIZE_BASE + 0x00030)
+#define MAIN_RESIZE_SCALE_HY_SHD (MAIN_RESIZE_BASE + 0x00034)
+#define MAIN_RESIZE_SCALE_HCB_SHD (MAIN_RESIZE_BASE + 0x00038)
+#define MAIN_RESIZE_SCALE_HCR_SHD (MAIN_RESIZE_BASE + 0x0003c)
+#define MAIN_RESIZE_SCALE_VY_SHD (MAIN_RESIZE_BASE + 0x00040)
+#define MAIN_RESIZE_SCALE_VC_SHD (MAIN_RESIZE_BASE + 0x00044)
+#define MAIN_RESIZE_PHASE_HY_SHD (MAIN_RESIZE_BASE + 0x00048)
+#define MAIN_RESIZE_PHASE_HC_SHD (MAIN_RESIZE_BASE + 0x0004c)
+#define MAIN_RESIZE_PHASE_VY_SHD (MAIN_RESIZE_BASE + 0x00050)
+#define MAIN_RESIZE_PHASE_VC_SHD (MAIN_RESIZE_BASE + 0x00054)
+
+#define SELF_RESIZE_BASE 0x00001000
+#define SELF_RESIZE_CTRL (SELF_RESIZE_BASE + 0x00000)
+#define SELF_RESIZE_SCALE_HY (SELF_RESIZE_BASE + 0x00004)
+#define SELF_RESIZE_SCALE_HCB (SELF_RESIZE_BASE + 0x00008)
+#define SELF_RESIZE_SCALE_HCR (SELF_RESIZE_BASE + 0x0000c)
+#define SELF_RESIZE_SCALE_VY (SELF_RESIZE_BASE + 0x00010)
+#define SELF_RESIZE_SCALE_VC (SELF_RESIZE_BASE + 0x00014)
+#define SELF_RESIZE_PHASE_HY (SELF_RESIZE_BASE + 0x00018)
+#define SELF_RESIZE_PHASE_HC (SELF_RESIZE_BASE + 0x0001c)
+#define SELF_RESIZE_PHASE_VY (SELF_RESIZE_BASE + 0x00020)
+#define SELF_RESIZE_PHASE_VC (SELF_RESIZE_BASE + 0x00024)
+#define SELF_RESIZE_SCALE_LUT_ADDR (SELF_RESIZE_BASE + 0x00028)
+#define SELF_RESIZE_SCALE_LUT (SELF_RESIZE_BASE + 0x0002c)
+#define SELF_RESIZE_CTRL_SHD (SELF_RESIZE_BASE + 0x00030)
+#define SELF_RESIZE_SCALE_HY_SHD (SELF_RESIZE_BASE + 0x00034)
+#define SELF_RESIZE_SCALE_HCB_SHD (SELF_RESIZE_BASE + 0x00038)
+#define SELF_RESIZE_SCALE_HCR_SHD (SELF_RESIZE_BASE + 0x0003c)
+#define SELF_RESIZE_SCALE_VY_SHD (SELF_RESIZE_BASE + 0x00040)
+#define SELF_RESIZE_SCALE_VC_SHD (SELF_RESIZE_BASE + 0x00044)
+#define SELF_RESIZE_PHASE_HY_SHD (SELF_RESIZE_BASE + 0x00048)
+#define SELF_RESIZE_PHASE_HC_SHD (SELF_RESIZE_BASE + 0x0004c)
+#define SELF_RESIZE_PHASE_VY_SHD (SELF_RESIZE_BASE + 0x00050)
+#define SELF_RESIZE_PHASE_VC_SHD (SELF_RESIZE_BASE + 0x00054)
+
+#define MI_BASE 0x00001400
+#define MI_WR_CTRL (MI_BASE + 0x00000)
+#define MI_WR_INIT (MI_BASE + 0x00004)
+#define MI_MP_WR_Y_BASE (MI_BASE + 0x00008)
+#define MI_MP_WR_Y_SIZE (MI_BASE + 0x0000c)
+#define MI_MP_WR_Y_OFFS_CNT (MI_BASE + 0x00010)
+#define MI_MP_WR_Y_OFFS_CNT_START (MI_BASE + 0x00014)
+#define MI_MP_WR_Y_IRQ_OFFS (MI_BASE + 0x00018)
+#define MI_MP_WR_CB_BASE (MI_BASE + 0x0001c)
+#define MI_MP_WR_CB_SIZE (MI_BASE + 0x00020)
+#define MI_MP_WR_CB_OFFS_CNT (MI_BASE + 0x00024)
+#define MI_MP_WR_CB_OFFS_CNT_START (MI_BASE + 0x00028)
+#define MI_MP_WR_CR_BASE (MI_BASE + 0x0002c)
+#define MI_MP_WR_CR_SIZE (MI_BASE + 0x00030)
+#define MI_MP_WR_CR_OFFS_CNT (MI_BASE + 0x00034)
+#define MI_MP_WR_CR_OFFS_CNT_START (MI_BASE + 0x00038)
+#define MI_SP_WR_Y_BASE (MI_BASE + 0x0003c)
+#define MI_SP_WR_Y_SIZE (MI_BASE + 0x00040)
+#define MI_SP_WR_Y_OFFS_CNT (MI_BASE + 0x00044)
+#define MI_SP_WR_Y_OFFS_CNT_START (MI_BASE + 0x00048)
+#define MI_SP_WR_Y_LLENGTH (MI_BASE + 0x0004c)
+#define MI_SP_WR_CB_BASE (MI_BASE + 0x00050)
+#define MI_SP_WR_CB_SIZE (MI_BASE + 0x00054)
+#define MI_SP_WR_CB_OFFS_CNT (MI_BASE + 0x00058)
+#define MI_SP_WR_CB_OFFS_CNT_START (MI_BASE + 0x0005c)
+#define MI_SP_WR_CR_BASE (MI_BASE + 0x00060)
+#define MI_SP_WR_CR_SIZE (MI_BASE + 0x00064)
+#define MI_SP_WR_CR_OFFS_CNT (MI_BASE + 0x00068)
+#define MI_SP_WR_CR_OFFS_CNT_START (MI_BASE + 0x0006c)
+#define MI_WR_BYTE_CNT (MI_BASE + 0x00070)
+#define MI_WR_CTRL_SHD (MI_BASE + 0x00074)
+#define MI_MP_WR_Y_BASE_SHD (MI_BASE + 0x00078)
+#define MI_MP_WR_Y_SIZE_SHD (MI_BASE + 0x0007c)
+#define MI_MP_WR_Y_OFFS_CNT_SHD (MI_BASE + 0x00080)
+#define MI_MP_WR_Y_IRQ_OFFS_SHD (MI_BASE + 0x00084)
+#define MI_MP_WR_CB_BASE_SHD (MI_BASE + 0x00088)
+#define MI_MP_WR_CB_SIZE_SHD (MI_BASE + 0x0008c)
+#define MI_MP_WR_CB_OFFS_CNT_SHD (MI_BASE + 0x00090)
+#define MI_MP_WR_CR_BASE_SHD (MI_BASE + 0x00094)
+#define MI_MP_WR_CR_SIZE_SHD (MI_BASE + 0x00098)
+#define MI_MP_WR_CR_OFFS_CNT_SHD (MI_BASE + 0x0009c)
+#define MI_SP_WR_Y_BASE_SHD (MI_BASE + 0x000a0)
+#define MI_SP_WR_Y_SIZE_SHD (MI_BASE + 0x000a4)
+#define MI_SP_WR_Y_OFFS_CNT_SHD (MI_BASE + 0x000a8)
+#define MI_SP_WR_CB_BASE_AD_SHD (MI_BASE + 0x000b0)
+#define MI_SP_WR_CB_SIZE_SHD (MI_BASE + 0x000b4)
+#define MI_SP_WR_CB_OFFS_CNT_SHD (MI_BASE + 0x000b8)
+#define MI_SP_WR_CR_BASE_AD_SHD (MI_BASE + 0x000bc)
+#define MI_SP_WR_CR_SIZE_SHD (MI_BASE + 0x000c0)
+#define MI_SP_WR_CR_OFFS_CNT_SHD (MI_BASE + 0x000c4)
+#define MI_RD_Y_PIC_START_AD (MI_BASE + 0x000c8)
+#define MI_RD_Y_PIC_WIDTH (MI_BASE + 0x000cc)
+#define MI_RD_Y_LLENGTH (MI_BASE + 0x000d0)
+#define MI_RD_Y_PIC_SIZE (MI_BASE + 0x000d4)
+#define MI_RD_CB_PIC_START_AD (MI_BASE + 0x000d8)
+#define MI_RD_CR_PIC_START_AD (MI_BASE + 0x000e8)
+#define MI_IMSC (MI_BASE + 0x000f8)
+#define MI_RIS (MI_BASE + 0x000fc)
+#define MI_MIS (MI_BASE + 0x00100)
+#define MI_ICR (MI_BASE + 0x00104)
+#define MI_ISR (MI_BASE + 0x00108)
+#define MI_STATUS (MI_BASE + 0x0010c)
+#define MI_STATUS_CLR (MI_BASE + 0x00110)
+#define MI_SP_WR_Y_PIC_WIDTH (MI_BASE + 0x00114)
+#define MI_SP_WR_Y_PIC_HEIGHT (MI_BASE + 0x00118)
+#define MI_SP_WR_Y_PIC_SIZE (MI_BASE + 0x0011c)
+#define MI_RD_CTRL (MI_BASE + 0x00120)
+#define MI_RD_START (MI_BASE + 0x00124)
+#define MI_RD_STATUS (MI_BASE + 0x00128)
+#define MI_WR_PIXEL_CNT (MI_BASE + 0x0012c)
+#define MI_MP_WR_Y_BASE2 (MI_BASE + 0x00130)
+#define MI_MP_WR_CB_BASE2 (MI_BASE + 0x00134)
+#define MI_MP_WR_CR_BASE2 (MI_BASE + 0x00138)
+#define MI_WR_XTD_FORMAT_CTRL (MI_BASE + 0x00148)
+#define MI_WR_ID (MI_BASE + 0x00154)
+#define MI_MP_WR_Y_IRQ_OFFS2 (MI_BASE + 0x001e0)
+#define MI_MP_WR_Y_IRQ_OFFS2_SHD (MI_BASE + 0x001e4)
+#define MI_MP_WR_Y_LLENGTH (MI_BASE + 0x001e8)
+#define MI_WR_CTRL2 (MI_BASE + 0x00400)
+#define MI_WR_ID2 (MI_BASE + 0x00404)
+#define MI_RD_CTRL2 (MI_BASE + 0x00408)
+#define MI_RD_ID (MI_BASE + 0x0040c)
+#define MI_RD_FIFO_LEVEL (MI_BASE + 0x0041c)
+#define MI_RAW0_WR_BASE (MI_BASE + 0x00420)
+#define MI_RAW0_WR_SIZE (MI_BASE + 0x00424)
+#define MI_RAW0_WR_LENGTH (MI_BASE + 0x00428)
+#define MI_RAW0_WR_BASE_SHD (MI_BASE + 0x0042c)
+#define MI_RAW1_WR_BASE (MI_BASE + 0x00430)
+#define MI_RAW1_WR_SIZE (MI_BASE + 0x00434)
+#define MI_RAW1_WR_LENGTH (MI_BASE + 0x00438)
+#define MI_RAW1_WR_BASE_SHD (MI_BASE + 0x0043c)
+#define MI_RAW2_WR_BASE (MI_BASE + 0x00440)
+#define MI_RAW2_WR_SIZE (MI_BASE + 0x00444)
+#define MI_RAW2_WR_LENGTH (MI_BASE + 0x00448)
+#define MI_RAW2_WR_BASE_SHD (MI_BASE + 0x0044c)
+#define MI_RAW3_WR_BASE (MI_BASE + 0x00450)
+#define MI_RAW3_WR_SIZE (MI_BASE + 0x00454)
+#define MI_RAW3_WR_LENGTH (MI_BASE + 0x00458)
+#define MI_RAW3_WR_BASE_SHD (MI_BASE + 0x0045c)
+#define MI_RW0_WR_LAST_FRAME_ADDR (MI_BASE + 0x00460)
+#define MI_RW1_WR_LAST_FRAME_ADDR (MI_BASE + 0x00464)
+#define MI_RW2_WR_LAST_FRAME_ADDR (MI_BASE + 0x00468)
+#define MI_RW3_WR_LAST_FRAME_ADDR (MI_BASE + 0x0046c)
+#define MI_RAW0_RD_BASE (MI_BASE + 0x00470)
+#define MI_RAW0_RD_LENGTH (MI_BASE + 0x00474)
+#define MI_RAW0_RD_BASE_SHD (MI_BASE + 0x00478)
+#define MI_RAW1_RD_BASE (MI_BASE + 0x00480)
+#define MI_RAW1_RD_LENGTH (MI_BASE + 0x00484)
+#define MI_RAW1_RD_BASE_SHD (MI_BASE + 0x00488)
+#define MI_RAW2_RD_BASE (MI_BASE + 0x00490)
+#define MI_RAW2_RD_LENGTH (MI_BASE + 0x00494)
+#define MI_RAW2_RD_BASE_SHD (MI_BASE + 0x00498)
+#define MI_RAWFBC_WR_BURST_LEN (MI_BASE + 0x00500)
+#define MI_RAWFBC_RD_BURST_LEN (MI_BASE + 0x00504)
+#define MI_RAW0FBC_WR_BASE (MI_BASE + 0x00510)
+#define MI_RAW1FBC_WR_BASE (MI_BASE + 0x00514)
+#define MI_RAW0FBC_RD_BASE (MI_BASE + 0x00518)
+#define MI_RAW1FBC_RD_BASE (MI_BASE + 0x0051c)
+#define MI_RAW0FBC_WR_BASE_SHD (MI_BASE + 0x00520)
+#define MI_RAW1FBC_WR_BASE_SHD (MI_BASE + 0x00524)
+#define MI_RAW0FBC_RD_BASE_SHD (MI_BASE + 0x00528)
+#define MI_RAW1FBC_RD_BASE_SHD (MI_BASE + 0x0052c)
+#define MI_LUT_3D_RD_BASE (MI_BASE + 0x00540)
+#define MI_LUT_LSC_RD_BASE (MI_BASE + 0x00544)
+#define MI_LUT_LDCH_RD_BASE (MI_BASE + 0x00548)
+#define MI_LUT_3D_RD_WSIZE (MI_BASE + 0x00550)
+#define MI_LUT_LSC_RD_WSIZE (MI_BASE + 0x00554)
+#define MI_LUT_LDCH_RD_H_WSIZE (MI_BASE + 0x00558)
+#define MI_LUT_LDCH_RD_V_SIZE (MI_BASE + 0x0055c)
+#define MI_DBR_WR_BASE (MI_BASE + 0x00560)
+#define MI_DBR_WR_SIZE (MI_BASE + 0x00564)
+#define MI_DBR_WR_LENGTH (MI_BASE + 0x00568)
+#define MI_DBR_WR_BASE_SHD (MI_BASE + 0x0056c)
+#define MI_DBR_RD_BASE (MI_BASE + 0x00570)
+#define MI_DBR_RD_LENGTH (MI_BASE + 0x00574)
+#define MI_DBR_RD_BASE_SHD (MI_BASE + 0x00578)
+#define MI_SWS_3A_WR_BASE (MI_BASE + 0x0057c)
+#define MI_GAIN_WR_BASE (MI_BASE + 0x00580)
+#define MI_GAIN_WR_SIZE (MI_BASE + 0x00584)
+#define MI_GAIN_WR_LENGTH (MI_BASE + 0x00588)
+#define MI_GAIN_WR_BASE2 (MI_BASE + 0x0058c)
+#define MI_GAIN_WR_BASE_SHD (MI_BASE + 0x00590)
+
+#define ISP21_MI_BAY3D_WR_BASE (MI_BASE + 0x005a0)
+#define ISP21_MI_BAY3D_WR_SIZE (MI_BASE + 0x005a4)
+#define ISP21_MI_BAY3D_WR_LENGTH (MI_BASE + 0x005a8)
+#define ISP21_MI_BAY3D_WR_BASE_SHD (MI_BASE + 0x005ac)
+#define ISP21_MI_BAY3D_RD_BASE (MI_BASE + 0x005b0)
+#define ISP21_MI_BAY3D_RD_LENGTH (MI_BASE + 0x005b4)
+#define ISP21_MI_BAY3D_RD_BASE_SHD (MI_BASE + 0x005b8)
+
+#define ISP_MPFBC_BASE 0x000018C0
+#define ISP_MPFBC_CTRL (ISP_MPFBC_BASE + 0x00000)
+#define ISP_MPFBC_VIR_WIDTH (ISP_MPFBC_BASE + 0x00004)
+#define ISP_MPFBC_VIR_HEIGHT (ISP_MPFBC_BASE + 0x00008)
+#define ISP_MPFBC_HEAD_PTR (ISP_MPFBC_BASE + 0x0000c)
+#define ISP_MPFBC_PAYL_PTR (ISP_MPFBC_BASE + 0x00010)
+#define ISP_MPFBC_HEAD_PTR2 (ISP_MPFBC_BASE + 0x00014)
+#define ISP_MPFBC_PAYL_PTR2 (ISP_MPFBC_BASE + 0x00018)
+#define ISP_MPFBC_ENC_POS (ISP_MPFBC_BASE + 0x00030)
+
+#define CSI2RX_BASE 0x00001C00
+#define CSI2RX_CTRL0 (CSI2RX_BASE + 0x00000)
+#define CSI2RX_CTRL1 (CSI2RX_BASE + 0x00004)
+#define CSI2RX_CTRL2 (CSI2RX_BASE + 0x00008)
+#define CSI2RX_CSI2_RESETN (CSI2RX_BASE + 0x00010)
+#define CSI2RX_PHY_STATE_RO (CSI2RX_BASE + 0x00014)
+#define CSI2RX_DATA_IDS_1 (CSI2RX_BASE + 0x00018)
+#define CSI2RX_DATA_IDS_2 (CSI2RX_BASE + 0x0001c)
+#define CSI2RX_ERR_PHY (CSI2RX_BASE + 0x00020)
+#define CSI2RX_ERR_PACKET (CSI2RX_BASE + 0x00024)
+#define CSI2RX_ERR_OVERFLOW (CSI2RX_BASE + 0x00028)
+#define CSI2RX_ERR_STAT (CSI2RX_BASE + 0x0002c)
+#define CSI2RX_MASK_PHY (CSI2RX_BASE + 0x00030)
+#define CSI2RX_MASK_PACKET (CSI2RX_BASE + 0x00034)
+#define CSI2RX_MASK_OVERFLOW (CSI2RX_BASE + 0x00038)
+#define CSI2RX_MASK_STAT (CSI2RX_BASE + 0x0003c)
+#define CSI2RX_RAW0_WR_CTRL (CSI2RX_BASE + 0x00040)
+#define CSI2RX_RAW0_WR_LINECNT_RO (CSI2RX_BASE + 0x00044)
+#define CSI2RX_RAW0_WR_PIC_SIZE (CSI2RX_BASE + 0x00048)
+#define CSI2RX_RAW0_WR_PIC_OFF (CSI2RX_BASE + 0x0004c)
+#define CSI2RX_RAW1_WR_CTRL (CSI2RX_BASE + 0x00050)
+#define CSI2RX_RAW1_WR_LINECNT_RO (CSI2RX_BASE + 0x00054)
+#define CSI2RX_RAW1_WR_PIC_SIZE (CSI2RX_BASE + 0x00058)
+#define CSI2RX_RAW1_WR_PIC_OFF (CSI2RX_BASE + 0x0005c)
+#define CSI2RX_RAW2_WR_CTRL (CSI2RX_BASE + 0x00060)
+#define CSI2RX_RAW2_WR_LINECNT_RO (CSI2RX_BASE + 0x00064)
+#define CSI2RX_RAW2_WR_PIC_SIZE (CSI2RX_BASE + 0x00068)
+#define CSI2RX_RAW2_WR_PIC_OFF (CSI2RX_BASE + 0x0006c)
+#define CSI2RX_RAW3_WR_CTRL (CSI2RX_BASE + 0x00070)
+#define CSI2RX_RAW3_WR_LINECNT_RO (CSI2RX_BASE + 0x00074)
+#define CSI2RX_RAW3_WR_PIC_SIZE (CSI2RX_BASE + 0x00078)
+#define CSI2RX_RAW3_WR_PIC_OFF (CSI2RX_BASE + 0x0007c)
+#define CSI2RX_RAW_RD_CTRL (CSI2RX_BASE + 0x00080)
+#define CSI2RX_RAW_RD_LINECNT_RO (CSI2RX_BASE + 0x00084)
+#define CSI2RX_RAW_RD_PIC_SIZE (CSI2RX_BASE + 0x00088)
+#define CSI2RX_RAW2_RD_LINECNT_RO (CSI2RX_BASE + 0x0008c)
+#define CSI2RX_RAWFBC_CTRL (CSI2RX_BASE + 0x00090)
+#define CSI2RX_ESPHDR_LCNT (CSI2RX_BASE + 0x00094)
+#define CSI2RX_ESPHDR_IDCD (CSI2RX_BASE + 0x00098)
+#define CSI2RX_VC0_FRAME_NUM_RO (CSI2RX_BASE + 0x000a0)
+#define CSI2RX_VC1_FRAME_NUM_RO (CSI2RX_BASE + 0x000a4)
+#define CSI2RX_VC2_FRAME_NUM_RO (CSI2RX_BASE + 0x000a8)
+#define CSI2RX_VC3_FRAME_NUM_RO (CSI2RX_BASE + 0x000ac)
+#define CSI2RX_ISP_LINECNT_RO (CSI2RX_BASE + 0x000b0)
+#define CSI2RX_RAW_WR_IBUF_STATUS_RO (CSI2RX_BASE + 0x000b4)
+#define CSI2RX_RAW_WR_IBUF3_STATUS_RO (CSI2RX_BASE + 0x000b8)
+#define CSI2RX_CUR_HEADER_RO (CSI2RX_BASE + 0x000c4)
+#define CSI2RX_RAWFBC_EN_SHD (CSI2RX_BASE + 0x000c8)
+#define CSI2RX_FPN_CTRL (CSI2RX_BASE + 0x000d0)
+#define CSI2RX_FPN_TABLE_CTRL (CSI2RX_BASE + 0x000d4)
+#define CSI2RX_FPN_TABLE_DATA0 (CSI2RX_BASE + 0x000d8)
+#define CSI2RX_FPN_TABLE_DATA1 (CSI2RX_BASE + 0x000dc)
+#define CSI2RX_Y_STAT_CTRL (CSI2RX_BASE + 0x000f0)
+#define CSI2RX_Y_STAT_RO (CSI2RX_BASE + 0x000f4)
+#define CSI2RX_VERSION (CSI2RX_BASE + 0x000fc)
+
+#define ISP_LSC_BASE 0x00002200
+#define ISP_LSC_CTRL (ISP_LSC_BASE + 0x00000)
+#define ISP_LSC_R_TABLE_ADDR (ISP_LSC_BASE + 0x00004)
+#define ISP_LSC_GR_TABLE_ADDR (ISP_LSC_BASE + 0x00008)
+#define ISP_LSC_B_TABLE_ADDR (ISP_LSC_BASE + 0x0000c)
+#define ISP_LSC_GB_TABLE_ADDR (ISP_LSC_BASE + 0x00010)
+#define ISP_LSC_R_TABLE_DATA (ISP_LSC_BASE + 0x00014)
+#define ISP_LSC_GR_TABLE_DATA (ISP_LSC_BASE + 0x00018)
+#define ISP_LSC_B_TABLE_DATA (ISP_LSC_BASE + 0x0001c)
+#define ISP_LSC_GB_TABLE_DATA (ISP_LSC_BASE + 0x00020)
+#define ISP_LSC_XGRAD_01 (ISP_LSC_BASE + 0x00024)
+#define ISP_LSC_XGRAD_23 (ISP_LSC_BASE + 0x00028)
+#define ISP_LSC_XGRAD_45 (ISP_LSC_BASE + 0x0002c)
+#define ISP_LSC_XGRAD_67 (ISP_LSC_BASE + 0x00030)
+#define ISP_LSC_YGRAD_01 (ISP_LSC_BASE + 0x00034)
+#define ISP_LSC_YGRAD_23 (ISP_LSC_BASE + 0x00038)
+#define ISP_LSC_YGRAD_45 (ISP_LSC_BASE + 0x0003c)
+#define ISP_LSC_YGRAD_67 (ISP_LSC_BASE + 0x00040)
+#define ISP_LSC_XSIZE_01 (ISP_LSC_BASE + 0x00044)
+#define ISP_LSC_XSIZE_23 (ISP_LSC_BASE + 0x00048)
+#define ISP_LSC_XSIZE_45 (ISP_LSC_BASE + 0x0004c)
+#define ISP_LSC_XSIZE_67 (ISP_LSC_BASE + 0x00050)
+#define ISP_LSC_YSIZE_01 (ISP_LSC_BASE + 0x00054)
+#define ISP_LSC_YSIZE_23 (ISP_LSC_BASE + 0x00058)
+#define ISP_LSC_YSIZE_45 (ISP_LSC_BASE + 0x0005c)
+#define ISP_LSC_YSIZE_67 (ISP_LSC_BASE + 0x00060)
+#define ISP_LSC_TABLE_SEL (ISP_LSC_BASE + 0x00064)
+#define ISP_LSC_STATUS (ISP_LSC_BASE + 0x00068)
+
+#define ISP_DEBAYER_BASE 0x00002500
+#define ISP_DEBAYER_CONTROL (ISP_DEBAYER_BASE + 0x00000)
+#define ISP_DEBAYER_G_INTERP (ISP_DEBAYER_BASE + 0x00004)
+#define ISP_DEBAYER_G_INTERP_FILTER1 (ISP_DEBAYER_BASE + 0x00008)
+#define ISP_DEBAYER_G_INTERP_FILTER2 (ISP_DEBAYER_BASE + 0x0000c)
+#define ISP_DEBAYER_G_FILTER (ISP_DEBAYER_BASE + 0x00010)
+#define ISP_DEBAYER_C_FILTER (ISP_DEBAYER_BASE + 0x00014)
+
+#define ISP21_YNR_BASE 0x00002700
+#define ISP21_YNR_GLOBAL_CTRL (ISP21_YNR_BASE + 0x00000)
+#define ISP21_YNR_RNR_MAX_R (ISP21_YNR_BASE + 0x00004)
+#define ISP21_YNR_LOWNR_CTRL0 (ISP21_YNR_BASE + 0x00010)
+#define ISP21_YNR_LOWNR_CTRL1 (ISP21_YNR_BASE + 0x00014)
+#define ISP21_YNR_LOWNR_CTRL2 (ISP21_YNR_BASE + 0x00018)
+#define ISP21_YNR_LOWNR_CTRL3 (ISP21_YNR_BASE + 0x0001c)
+#define ISP21_YNR_HIGHNR_CTRL0 (ISP21_YNR_BASE + 0x00020)
+#define ISP21_YNR_HIGHNR_CTRL1 (ISP21_YNR_BASE + 0x00024)
+#define ISP21_YNR_HIGHNR_BASE_FILTER_WEIGHT (ISP21_YNR_BASE + 0x00028)
+#define ISP21_YNR_GAUSS1_COEFF (ISP21_YNR_BASE + 0x00030)
+#define ISP21_YNR_GAUSS2_COEFF (ISP21_YNR_BASE + 0x00034)
+#define ISP21_YNR_DIRECTION_W_0_3 (ISP21_YNR_BASE + 0x00038)
+#define ISP21_YNR_DIRECTION_W_4_7 (ISP21_YNR_BASE + 0x0003c)
+#define ISP21_YNR_SGM_DX_0_1 (ISP21_YNR_BASE + 0x00040)
+#define ISP21_YNR_SGM_DX_2_3 (ISP21_YNR_BASE + 0x00044)
+#define ISP21_YNR_SGM_DX_4_5 (ISP21_YNR_BASE + 0x00048)
+#define ISP21_YNR_SGM_DX_6_7 (ISP21_YNR_BASE + 0x0004c)
+#define ISP21_YNR_SGM_DX_8_9 (ISP21_YNR_BASE + 0x00050)
+#define ISP21_YNR_SGM_DX_10_11 (ISP21_YNR_BASE + 0x00055)
+#define ISP21_YNR_SGM_DX_12_13 (ISP21_YNR_BASE + 0x00058)
+#define ISP21_YNR_SGM_DX_14_15 (ISP21_YNR_BASE + 0x0005c)
+#define ISP21_YNR_SGM_DX_16 (ISP21_YNR_BASE + 0x00060)
+#define ISP21_YNR_LSGM_Y_0_1 (ISP21_YNR_BASE + 0x00070)
+#define ISP21_YNR_LSGM_Y_2_3 (ISP21_YNR_BASE + 0x00074)
+#define ISP21_YNR_LSGM_Y_4_5 (ISP21_YNR_BASE + 0x00078)
+#define ISP21_YNR_LSGM_Y_6_7 (ISP21_YNR_BASE + 0x0007c)
+#define ISP21_YNR_LSGM_Y_8_9 (ISP21_YNR_BASE + 0x00080)
+#define ISP21_YNR_LSGM_Y_10_11 (ISP21_YNR_BASE + 0x00084)
+#define ISP21_YNR_LSGM_Y_12_13 (ISP21_YNR_BASE + 0x00088)
+#define ISP21_YNR_LSGM_Y_14_15 (ISP21_YNR_BASE + 0x0008c)
+#define ISP21_YNR_LSGM_Y_16 (ISP21_YNR_BASE + 0x00090)
+#define ISP21_YNR_HSGM_Y_0_1 (ISP21_YNR_BASE + 0x000a0)
+#define ISP21_YNR_HSGM_Y_2_3 (ISP21_YNR_BASE + 0x000a4)
+#define ISP21_YNR_HSGM_Y_4_5 (ISP21_YNR_BASE + 0x000a8)
+#define ISP21_YNR_HSGM_Y_6_7 (ISP21_YNR_BASE + 0x000ac)
+#define ISP21_YNR_HSGM_Y_8_9 (ISP21_YNR_BASE + 0x000b0)
+#define ISP21_YNR_HSGM_Y_10_11 (ISP21_YNR_BASE + 0x000b4)
+#define ISP21_YNR_HSGM_Y_12_13 (ISP21_YNR_BASE + 0x000b8)
+#define ISP21_YNR_HSGM_Y_14_15 (ISP21_YNR_BASE + 0x000bc)
+#define ISP21_YNR_HSGM_Y_16 (ISP21_YNR_BASE + 0x000c0)
+#define ISP21_YNR_RNR_STRENGTH03 (ISP21_YNR_BASE + 0x000d0)
+#define ISP21_YNR_RNR_STRENGTH47 (ISP21_YNR_BASE + 0x000d4)
+#define ISP21_YNR_RNR_STRENGTH8B (ISP21_YNR_BASE + 0x000d8)
+#define ISP21_YNR_RNR_STRENGTHCF (ISP21_YNR_BASE + 0x000dc)
+#define ISP21_YNR_RNR_STRENGTH16 (ISP21_YNR_BASE + 0x000e0)
+
+#define ISP21_CNR_BASE 0x00002800
+#define ISP21_CNR_CTRL (ISP21_CNR_BASE + 0x00000)
+#define ISP21_CNR_EXGAIN (ISP21_CNR_BASE + 0x00004)
+#define ISP21_CNR_GAIN_PARA (ISP21_CNR_BASE + 0x00008)
+#define ISP21_CNR_GAIN_UV_PARA (ISP21_CNR_BASE + 0x0000c)
+#define ISP21_CNR_LMED3 (ISP21_CNR_BASE + 0x00010)
+#define ISP21_CNR_LBF5_GAIN (ISP21_CNR_BASE + 0x00014)
+#define ISP21_CNR_LBF5_WEITD0_3 (ISP21_CNR_BASE + 0x00018)
+#define ISP21_CNR_LBF5_WEITD4 (ISP21_CNR_BASE + 0x0001c)
+#define ISP21_CNR_HMED3 (ISP21_CNR_BASE + 0x00020)
+#define ISP21_CNR_HBF5 (ISP21_CNR_BASE + 0x00024)
+#define ISP21_CNR_LBF3 (ISP21_CNR_BASE + 0x00028)
+
+#define ISP21_SHARP_BASE 0x00002900
+#define ISP21_SHARP_SHARP_EN (ISP21_SHARP_BASE + 0x00000)
+#define ISP21_SHARP_SHARP_RATIO (ISP21_SHARP_BASE + 0x00004)
+#define ISP21_SHARP_SHARP_LUMA_DX (ISP21_SHARP_BASE + 0x00008)
+#define ISP21_SHARP_SHARP_PBF_SIGMA_INV_0 (ISP21_SHARP_BASE + 0x0000c)
+#define ISP21_SHARP_SHARP_PBF_SIGMA_INV_1 (ISP21_SHARP_BASE + 0x00010)
+#define ISP21_SHARP_SHARP_PBF_SIGMA_INV_2 (ISP21_SHARP_BASE + 0x00014)
+#define ISP21_SHARP_SHARP_BF_SIGMA_INV_0 (ISP21_SHARP_BASE + 0x00018)
+#define ISP21_SHARP_SHARP_BF_SIGMA_INV_1 (ISP21_SHARP_BASE + 0x0001c)
+#define ISP21_SHARP_SHARP_BF_SIGMA_INV_2 (ISP21_SHARP_BASE + 0x00020)
+#define ISP21_SHARP_SHARP_SIGMA_SHIFT (ISP21_SHARP_BASE + 0x00024)
+#define ISP21_SHARP_SHARP_EHF_TH_0 (ISP21_SHARP_BASE + 0x00028)
+#define ISP21_SHARP_SHARP_EHF_TH_1 (ISP21_SHARP_BASE + 0x0002c)
+#define ISP21_SHARP_SHARP_EHF_TH_2 (ISP21_SHARP_BASE + 0x00030)
+#define ISP21_SHARP_SHARP_CLIP_HF_0 (ISP21_SHARP_BASE + 0x00034)
+#define ISP21_SHARP_SHARP_CLIP_HF_1 (ISP21_SHARP_BASE + 0x00038)
+#define ISP21_SHARP_SHARP_CLIP_HF_2 (ISP21_SHARP_BASE + 0x0003c)
+#define ISP21_SHARP_SHARP_PBF_COEF (ISP21_SHARP_BASE + 0x00040)
+#define ISP21_SHARP_SHARP_BF_COEF (ISP21_SHARP_BASE + 0x00044)
+#define ISP21_SHARP_SHARP_GAUS_COEF (ISP21_SHARP_BASE + 0x00048)
+
+#define ISP_WDR_BASE 0x00002A00
+#define ISP_WDR_CTRL (ISP_WDR_BASE + 0x00000)
+#define ISP_WDR_WDR_TONECURVE_DYN1 (ISP_WDR_BASE + 0x00004)
+#define ISP_WDR_WDR_TONECURVE_DYN2 (ISP_WDR_BASE + 0x00008)
+#define ISP_WDR_WDR_TONECURVE_DYN3 (ISP_WDR_BASE + 0x0000c)
+#define ISP_WDR_WDR_TONECURVE_DYN4 (ISP_WDR_BASE + 0x00010)
+#define ISP_WDR_TONECURVE_YM_0 (ISP_WDR_BASE + 0x00014)
+#define ISP_WDR_TONECURVE_YM_1 (ISP_WDR_BASE + 0x00018)
+#define ISP_WDR_TONECURVE_YM_2 (ISP_WDR_BASE + 0x0001c)
+#define ISP_WDR_TONECURVE_YM_3 (ISP_WDR_BASE + 0x00020)
+#define ISP_WDR_TONECURVE_YM_4 (ISP_WDR_BASE + 0x00024)
+#define ISP_WDR_TONECURVE_YM_5 (ISP_WDR_BASE + 0x00028)
+#define ISP_WDR_TONECURVE_YM_6 (ISP_WDR_BASE + 0x0002c)
+#define ISP_WDR_TONECURVE_YM_7 (ISP_WDR_BASE + 0x00030)
+#define ISP_WDR_TONECURVE_YM_8 (ISP_WDR_BASE + 0x00034)
+#define ISP_WDR_TONECURVE_YM_9 (ISP_WDR_BASE + 0x00038)
+#define ISP_WDR_TONECURVE_YM_10 (ISP_WDR_BASE + 0x0003c)
+#define ISP_WDR_TONECURVE_YM_11 (ISP_WDR_BASE + 0x00040)
+#define ISP_WDR_TONECURVE_YM_12 (ISP_WDR_BASE + 0x00044)
+#define ISP_WDR_TONECURVE_YM_13 (ISP_WDR_BASE + 0x00048)
+#define ISP_WDR_TONECURVE_YM_14 (ISP_WDR_BASE + 0x0004c)
+#define ISP_WDR_TONECURVE_YM_15 (ISP_WDR_BASE + 0x00050)
+#define ISP_WDR_TONECURVE_YM_16 (ISP_WDR_BASE + 0x00054)
+#define ISP_WDR_TONECURVE_YM_17 (ISP_WDR_BASE + 0x00058)
+#define ISP_WDR_TONECURVE_YM_18 (ISP_WDR_BASE + 0x0005c)
+#define ISP_WDR_TONECURVE_YM_19 (ISP_WDR_BASE + 0x00060)
+#define ISP_WDR_TONECURVE_YM_20 (ISP_WDR_BASE + 0x00064)
+#define ISP_WDR_TONECURVE_YM_21 (ISP_WDR_BASE + 0x00068)
+#define ISP_WDR_TONECURVE_YM_22 (ISP_WDR_BASE + 0x0006c)
+#define ISP_WDR_TONECURVE_YM_23 (ISP_WDR_BASE + 0x00070)
+#define ISP_WDR_TONECURVE_YM_24 (ISP_WDR_BASE + 0x00074)
+#define ISP_WDR_TONECURVE_YM_25 (ISP_WDR_BASE + 0x00078)
+#define ISP_WDR_TONECURVE_YM_26 (ISP_WDR_BASE + 0x0007c)
+#define ISP_WDR_TONECURVE_YM_27 (ISP_WDR_BASE + 0x00080)
+#define ISP_WDR_TONECURVE_YM_28 (ISP_WDR_BASE + 0x00084)
+#define ISP_WDR_TONECURVE_YM_29 (ISP_WDR_BASE + 0x00088)
+#define ISP_WDR_TONECURVE_YM_30 (ISP_WDR_BASE + 0x0008c)
+#define ISP_WDR_TONECURVE_YM_31 (ISP_WDR_BASE + 0x00090)
+#define ISP_WDR_TONECURVE_YM_32 (ISP_WDR_BASE + 0x00094)
+#define ISP_WDR_OFFSET (ISP_WDR_BASE + 0x00098)
+#define ISP_WDR_CTRL0 (ISP_WDR_BASE + 0x00150)
+#define ISP_WDR_CTRL1 (ISP_WDR_BASE + 0x00154)
+#define ISP_WDR_BLKOFF0 (ISP_WDR_BASE + 0x00158)
+#define ISP_WDR_AVGCLIP (ISP_WDR_BASE + 0x0015c)
+#define ISP_WDR_COE_0 (ISP_WDR_BASE + 0x00160)
+#define ISP_WDR_COE_1 (ISP_WDR_BASE + 0x00164)
+#define ISP_WDR_COE_2 (ISP_WDR_BASE + 0x00168)
+#define ISP_WDR_COE_OFF (ISP_WDR_BASE + 0x0016c)
+#define ISP_WDR_BLKOFF1 (ISP_WDR_BASE + 0x00174)
+#define ISP_WDR_BLKMEAN8_ROW0_0TO3 (ISP_WDR_BASE + 0x00180)
+#define ISP_WDR_BLKMEAN8_ROW0_4TO7 (ISP_WDR_BASE + 0x00184)
+#define ISP_WDR_BLKMEAN8_ROW1_0TO3 (ISP_WDR_BASE + 0x00188)
+#define ISP_WDR_BLKMEAN8_ROW1_4TO7 (ISP_WDR_BASE + 0x0018c)
+#define ISP_WDR_BLKMEAN8_ROW2_0TO3 (ISP_WDR_BASE + 0x00190)
+#define ISP_WDR_BLKMEAN8_ROW2_4TO7 (ISP_WDR_BASE + 0x00194)
+#define ISP_WDR_BLKMEAN8_ROW3_0TO3 (ISP_WDR_BASE + 0x00198)
+#define ISP_WDR_BLKMEAN8_ROW3_4TO7 (ISP_WDR_BASE + 0x0019c)
+#define ISP_WDR_BLKMEAN8_ROW4_0TO3 (ISP_WDR_BASE + 0x001a0)
+#define ISP_WDR_BLKMEAN8_ROW4_4TO7 (ISP_WDR_BASE + 0x001a4)
+#define ISP_WDR_BLKMEAN8_ROW5_0TO3 (ISP_WDR_BASE + 0x001a8)
+#define ISP_WDR_BLKMEAN8_ROW5_4TO7 (ISP_WDR_BASE + 0x001ac)
+#define ISP_WDR_BLKMEAN8_ROW6_0TO3 (ISP_WDR_BASE + 0x001b0)
+#define ISP_WDR_BLKMEAN8_ROW6_4TO7 (ISP_WDR_BASE + 0x001b4)
+#define ISP_WDR_BLKMEAN8_ROW7_0TO3 (ISP_WDR_BASE + 0x001b8)
+#define ISP_WDR_BLKMEAN8_ROW7_4TO7 (ISP_WDR_BASE + 0x001bc)
+#define ISP_WDR_BLKMEAN8_ROW8_0TO3 (ISP_WDR_BASE + 0x001c0)
+#define ISP_WDR_BLKMEAN8_ROW8_4TO7 (ISP_WDR_BASE + 0x001c4)
+#define ISP_WDR_BLKMEAN8_ROW9_0TO3 (ISP_WDR_BASE + 0x001c8)
+#define ISP_WDR_BLKMEAN8_ROW9_4TO7 (ISP_WDR_BASE + 0x001cc)
+
+#define ISP_GIC_BASE 0x00002F00
+#define ISP_GIC_CONTROL (ISP_GIC_BASE + 0x00000)
+#define ISP_GIC_DIFF_PARA1 (ISP_GIC_BASE + 0x00004)
+#define ISP_GIC_DIFF_PARA2 (ISP_GIC_BASE + 0x00008)
+#define ISP_GIC_DIFF_PARA3 (ISP_GIC_BASE + 0x0000c)
+#define ISP_GIC_DIFF_PARA4 (ISP_GIC_BASE + 0x00010)
+#define ISP_GIC_NOISE_PARA1 (ISP_GIC_BASE + 0x00014)
+#define ISP_GIC_NOISE_PARA2 (ISP_GIC_BASE + 0x00018)
+#define ISP_GIC_NOISE_PARA3 (ISP_GIC_BASE + 0x0001c)
+#define ISP_GIC_SIGMA_VALUE0 (ISP_GIC_BASE + 0x00020)
+#define ISP_GIC_SIGMA_VALUE1 (ISP_GIC_BASE + 0x00024)
+#define ISP_GIC_SIGMA_VALUE2 (ISP_GIC_BASE + 0x00028)
+#define ISP_GIC_SIGMA_VALUE3 (ISP_GIC_BASE + 0x0002c)
+#define ISP_GIC_SIGMA_VALUE4 (ISP_GIC_BASE + 0x00030)
+#define ISP_GIC_SIGMA_VALUE5 (ISP_GIC_BASE + 0x00034)
+#define ISP_GIC_SIGMA_VALUE6 (ISP_GIC_BASE + 0x00038)
+#define ISP_GIC_SIGMA_VALUE7 (ISP_GIC_BASE + 0x0003c)
+#define ISP_GIC_NOISE_CTRL0 (ISP_GIC_BASE + 0x00040)
+#define ISP_GIC_NOISE_CTRL1 (ISP_GIC_BASE + 0x00044)
+
+#define ISP_BLS_BASE 0x00003000
+#define ISP_BLS_CTRL (ISP_BLS_BASE + 0x00000)
+#define ISP_BLS_SAMPLES (ISP_BLS_BASE + 0x00004)
+#define ISP_BLS_H1_START (ISP_BLS_BASE + 0x00008)
+#define ISP_BLS_H1_STOP (ISP_BLS_BASE + 0x0000c)
+#define ISP_BLS_V1_START (ISP_BLS_BASE + 0x00010)
+#define ISP_BLS_V1_STOP (ISP_BLS_BASE + 0x00014)
+#define ISP_BLS_H2_START (ISP_BLS_BASE + 0x00018)
+#define ISP_BLS_H2_STOP (ISP_BLS_BASE + 0x0001c)
+#define ISP_BLS_V2_START (ISP_BLS_BASE + 0x00020)
+#define ISP_BLS_V2_STOP (ISP_BLS_BASE + 0x00024)
+#define ISP_BLS_A_FIXED (ISP_BLS_BASE + 0x00028)
+#define ISP_BLS_B_FIXED (ISP_BLS_BASE + 0x0002c)
+#define ISP_BLS_C_FIXED (ISP_BLS_BASE + 0x00030)
+#define ISP_BLS_D_FIXED (ISP_BLS_BASE + 0x00034)
+#define ISP_BLS_A_MEASURED (ISP_BLS_BASE + 0x00038)
+#define ISP_BLS_B_MEASURED (ISP_BLS_BASE + 0x0003c)
+#define ISP_BLS_C_MEASURED (ISP_BLS_BASE + 0x00040)
+#define ISP_BLS_D_MEASURED (ISP_BLS_BASE + 0x00044)
+#define ISP_BLS1_A_FIXED (ISP_BLS_BASE + 0x00048)
+#define ISP_BLS1_B_FIXED (ISP_BLS_BASE + 0x0004c)
+#define ISP_BLS1_C_FIXED (ISP_BLS_BASE + 0x00050)
+#define ISP_BLS1_D_FIXED (ISP_BLS_BASE + 0x00054)
+
+#define ISP_DPCC0_BASE 0x00003400
+#define ISP_DPCC1_BASE 0x00003500
+#define ISP_DPCC2_BASE 0x00003600
+#define ISP_DPCC0_MODE (ISP_DPCC0_BASE + 0x00000)
+#define ISP_DPCC0_OUTPUT_MODE (ISP_DPCC0_BASE + 0x00004)
+#define ISP_DPCC0_SET_USE (ISP_DPCC0_BASE + 0x00008)
+#define ISP_DPCC0_METHODS_SET_1 (ISP_DPCC0_BASE + 0x0000c)
+#define ISP_DPCC0_METHODS_SET_2 (ISP_DPCC0_BASE + 0x00010)
+#define ISP_DPCC0_METHODS_SET_3 (ISP_DPCC0_BASE + 0x00014)
+#define ISP_DPCC0_LINE_THRESH_1 (ISP_DPCC0_BASE + 0x00018)
+#define ISP_DPCC0_LINE_MAD_FAC_1 (ISP_DPCC0_BASE + 0x0001c)
+#define ISP_DPCC0_PG_FAC_1 (ISP_DPCC0_BASE + 0x00020)
+#define ISP_DPCC0_RND_THRESH_1 (ISP_DPCC0_BASE + 0x00024)
+#define ISP_DPCC0_RG_FAC_1 (ISP_DPCC0_BASE + 0x00028)
+#define ISP_DPCC0_LINE_THRESH_2 (ISP_DPCC0_BASE + 0x0002c)
+#define ISP_DPCC0_LINE_MAD_FAC_2 (ISP_DPCC0_BASE + 0x00030)
+#define ISP_DPCC0_PG_FAC_2 (ISP_DPCC0_BASE + 0x00034)
+#define ISP_DPCC0_RND_THRESH_2 (ISP_DPCC0_BASE + 0x00038)
+#define ISP_DPCC0_RG_FAC_2 (ISP_DPCC0_BASE + 0x0003c)
+#define ISP_DPCC0_LINE_THRESH_3 (ISP_DPCC0_BASE + 0x00040)
+#define ISP_DPCC0_LINE_MAD_FAC_3 (ISP_DPCC0_BASE + 0x00044)
+#define ISP_DPCC0_PG_FAC_3 (ISP_DPCC0_BASE + 0x00048)
+#define ISP_DPCC0_RND_THRESH_3 (ISP_DPCC0_BASE + 0x0004c)
+#define ISP_DPCC0_RG_FAC_3 (ISP_DPCC0_BASE + 0x00050)
+#define ISP_DPCC0_RO_LIMITS (ISP_DPCC0_BASE + 0x00054)
+#define ISP_DPCC0_RND_OFFS (ISP_DPCC0_BASE + 0x00058)
+#define ISP_DPCC0_BPT_CTRL (ISP_DPCC0_BASE + 0x0005c)
+#define ISP_DPCC0_BPT_NUMBER (ISP_DPCC0_BASE + 0x00060)
+#define ISP_DPCC0_BPT_ADDR (ISP_DPCC0_BASE + 0x00064)
+#define ISP_DPCC0_BPT_DATA (ISP_DPCC0_BASE + 0x00068)
+#define ISP_DPCC0_BP_CNT (ISP_DPCC0_BASE + 0x0006c)
+#define ISP_DPCC0_PDAF_EN (ISP_DPCC0_BASE + 0x00070)
+#define ISP_DPCC0_PDAF_POINT_EN (ISP_DPCC0_BASE + 0x00074)
+#define ISP_DPCC0_PDAF_OFFSET (ISP_DPCC0_BASE + 0x00078)
+#define ISP_DPCC0_PDAF_WRAP (ISP_DPCC0_BASE + 0x0007c)
+#define ISP_DPCC0_PDAF_SCOPE (ISP_DPCC0_BASE + 0x00080)
+#define ISP_DPCC0_PDAF_POINT_0 (ISP_DPCC0_BASE + 0x00084)
+#define ISP_DPCC0_PDAF_POINT_1 (ISP_DPCC0_BASE + 0x00088)
+#define ISP_DPCC0_PDAF_POINT_2 (ISP_DPCC0_BASE + 0x0008c)
+#define ISP_DPCC0_PDAF_POINT_3 (ISP_DPCC0_BASE + 0x00090)
+#define ISP_DPCC0_PDAF_POINT_4 (ISP_DPCC0_BASE + 0x00094)
+#define ISP_DPCC0_PDAF_POINT_5 (ISP_DPCC0_BASE + 0x00098)
+#define ISP_DPCC0_PDAF_POINT_6 (ISP_DPCC0_BASE + 0x0009c)
+#define ISP_DPCC0_PDAF_POINT_7 (ISP_DPCC0_BASE + 0x000a0)
+#define ISP_DPCC0_PDAF_FORWARD_MED (ISP_DPCC0_BASE + 0x000a4)
+
+#define ISP_DPCC1_MODE (ISP_DPCC1_BASE + 0x00000)
+#define ISP_DPCC1_OUTPUT_MODE (ISP_DPCC1_BASE + 0x00004)
+#define ISP_DPCC1_SET_USE (ISP_DPCC1_BASE + 0x00008)
+#define ISP_DPCC1_METHODS_SET_1 (ISP_DPCC1_BASE + 0x0000c)
+#define ISP_DPCC1_METHODS_SET_2 (ISP_DPCC1_BASE + 0x00010)
+#define ISP_DPCC1_METHODS_SET_3 (ISP_DPCC1_BASE + 0x00014)
+#define ISP_DPCC1_LINE_THRESH_1 (ISP_DPCC1_BASE + 0x00018)
+#define ISP_DPCC1_LINE_MAD_FAC_1 (ISP_DPCC1_BASE + 0x0001c)
+#define ISP_DPCC1_PG_FAC_1 (ISP_DPCC1_BASE + 0x00020)
+#define ISP_DPCC1_RND_THRESH_1 (ISP_DPCC1_BASE + 0x00024)
+#define ISP_DPCC1_RG_FAC_1 (ISP_DPCC1_BASE + 0x00028)
+#define ISP_DPCC1_LINE_THRESH_2 (ISP_DPCC1_BASE + 0x0002c)
+#define ISP_DPCC1_LINE_MAD_FAC_2 (ISP_DPCC1_BASE + 0x00030)
+#define ISP_DPCC1_PG_FAC_2 (ISP_DPCC1_BASE + 0x00034)
+#define ISP_DPCC1_RND_THRESH_2 (ISP_DPCC1_BASE + 0x00038)
+#define ISP_DPCC1_RG_FAC_2 (ISP_DPCC1_BASE + 0x0003c)
+#define ISP_DPCC1_LINE_THRESH_3 (ISP_DPCC1_BASE + 0x00040)
+#define ISP_DPCC1_LINE_MAD_FAC_3 (ISP_DPCC1_BASE + 0x00044)
+#define ISP_DPCC1_PG_FAC_3 (ISP_DPCC1_BASE + 0x00048)
+#define ISP_DPCC1_RND_THRESH_3 (ISP_DPCC1_BASE + 0x0004c)
+#define ISP_DPCC1_RG_FAC_3 (ISP_DPCC1_BASE + 0x00050)
+#define ISP_DPCC1_RO_LIMITS (ISP_DPCC1_BASE + 0x00054)
+#define ISP_DPCC1_RND_OFFS (ISP_DPCC1_BASE + 0x00058)
+#define ISP_DPCC1_BPT_CTRL (ISP_DPCC1_BASE + 0x0005c)
+#define ISP_DPCC1_BPT_NUMBER (ISP_DPCC1_BASE + 0x00060)
+#define ISP_DPCC1_BPT_ADDR (ISP_DPCC1_BASE + 0x00064)
+#define ISP_DPCC1_BPT_DATA (ISP_DPCC1_BASE + 0x00068)
+#define ISP_DPCC1_BP_CNT (ISP_DPCC1_BASE + 0x0006c)
+#define ISP_DPCC1_PDAF_EN (ISP_DPCC1_BASE + 0x00070)
+#define ISP_DPCC1_PDAF_POINT_EN (ISP_DPCC1_BASE + 0x00074)
+#define ISP_DPCC1_PDAF_OFFSET (ISP_DPCC1_BASE + 0x00078)
+#define ISP_DPCC1_PDAF_WRAP (ISP_DPCC1_BASE + 0x0007c)
+#define ISP_DPCC1_PDAF_SCOPE (ISP_DPCC1_BASE + 0x00080)
+#define ISP_DPCC1_PDAF_POINT_0 (ISP_DPCC1_BASE + 0x00084)
+#define ISP_DPCC1_PDAF_POINT_1 (ISP_DPCC1_BASE + 0x00088)
+#define ISP_DPCC1_PDAF_POINT_2 (ISP_DPCC1_BASE + 0x0008c)
+#define ISP_DPCC1_PDAF_POINT_3 (ISP_DPCC1_BASE + 0x00090)
+#define ISP_DPCC1_PDAF_POINT_4 (ISP_DPCC1_BASE + 0x00094)
+#define ISP_DPCC1_PDAF_POINT_5 (ISP_DPCC1_BASE + 0x00098)
+#define ISP_DPCC1_PDAF_POINT_6 (ISP_DPCC1_BASE + 0x0009c)
+#define ISP_DPCC1_PDAF_POINT_7 (ISP_DPCC1_BASE + 0x000a0)
+#define ISP_DPCC1_PDAF_FORWARD_MED (ISP_DPCC1_BASE + 0x000a4)
+
+#define ISP_DPCC2_MODE (ISP_DPCC2_BASE + 0x00000)
+#define ISP_DPCC2_OUTPUT_MODE (ISP_DPCC2_BASE + 0x00004)
+#define ISP_DPCC2_SET_USE (ISP_DPCC2_BASE + 0x00008)
+#define ISP_DPCC2_METHODS_SET_1 (ISP_DPCC2_BASE + 0x0000c)
+#define ISP_DPCC2_METHODS_SET_2 (ISP_DPCC2_BASE + 0x00010)
+#define ISP_DPCC2_METHODS_SET_3 (ISP_DPCC2_BASE + 0x00014)
+#define ISP_DPCC2_LINE_THRESH_1 (ISP_DPCC2_BASE + 0x00018)
+#define ISP_DPCC2_LINE_MAD_FAC_1 (ISP_DPCC2_BASE + 0x0001c)
+#define ISP_DPCC2_PG_FAC_1 (ISP_DPCC2_BASE + 0x00020)
+#define ISP_DPCC2_RND_THRESH_1 (ISP_DPCC2_BASE + 0x00024)
+#define ISP_DPCC2_RG_FAC_1 (ISP_DPCC2_BASE + 0x00028)
+#define ISP_DPCC2_LINE_THRESH_2 (ISP_DPCC2_BASE + 0x0002c)
+#define ISP_DPCC2_LINE_MAD_FAC_2 (ISP_DPCC2_BASE + 0x00030)
+#define ISP_DPCC2_PG_FAC_2 (ISP_DPCC2_BASE + 0x00034)
+#define ISP_DPCC2_RND_THRESH_2 (ISP_DPCC2_BASE + 0x00038)
+#define ISP_DPCC2_RG_FAC_2 (ISP_DPCC2_BASE + 0x0003c)
+#define ISP_DPCC2_LINE_THRESH_3 (ISP_DPCC2_BASE + 0x00040)
+#define ISP_DPCC2_LINE_MAD_FAC_3 (ISP_DPCC2_BASE + 0x00044)
+#define ISP_DPCC2_PG_FAC_3 (ISP_DPCC2_BASE + 0x00048)
+#define ISP_DPCC2_RND_THRESH_3 (ISP_DPCC2_BASE + 0x0004c)
+#define ISP_DPCC2_RG_FAC_3 (ISP_DPCC2_BASE + 0x00050)
+#define ISP_DPCC2_RO_LIMITS (ISP_DPCC2_BASE + 0x00054)
+#define ISP_DPCC2_RND_OFFS (ISP_DPCC2_BASE + 0x00058)
+#define ISP_DPCC2_BPT_CTRL (ISP_DPCC2_BASE + 0x0005c)
+#define ISP_DPCC2_BPT_NUMBER (ISP_DPCC2_BASE + 0x00060)
+#define ISP_DPCC2_BPT_ADDR (ISP_DPCC2_BASE + 0x00064)
+#define ISP_DPCC2_BPT_DATA (ISP_DPCC2_BASE + 0x00068)
+#define ISP_DPCC2_BP_CNT (ISP_DPCC2_BASE + 0x0006c)
+#define ISP_DPCC2_PDAF_EN (ISP_DPCC2_BASE + 0x00070)
+#define ISP_DPCC2_PDAF_POINT_EN (ISP_DPCC2_BASE + 0x00074)
+#define ISP_DPCC2_PDAF_OFFSET (ISP_DPCC2_BASE + 0x00078)
+#define ISP_DPCC2_PDAF_WRAP (ISP_DPCC2_BASE + 0x0007c)
+#define ISP_DPCC2_PDAF_SCOPE (ISP_DPCC2_BASE + 0x00080)
+#define ISP_DPCC2_PDAF_POINT_0 (ISP_DPCC2_BASE + 0x00084)
+#define ISP_DPCC2_PDAF_POINT_1 (ISP_DPCC2_BASE + 0x00088)
+#define ISP_DPCC2_PDAF_POINT_2 (ISP_DPCC2_BASE + 0x0008c)
+#define ISP_DPCC2_PDAF_POINT_3 (ISP_DPCC2_BASE + 0x00090)
+#define ISP_DPCC2_PDAF_POINT_4 (ISP_DPCC2_BASE + 0x00094)
+#define ISP_DPCC2_PDAF_POINT_5 (ISP_DPCC2_BASE + 0x00098)
+#define ISP_DPCC2_PDAF_POINT_6 (ISP_DPCC2_BASE + 0x0009c)
+#define ISP_DPCC2_PDAF_POINT_7 (ISP_DPCC2_BASE + 0x000a0)
+#define ISP_DPCC2_PDAF_FORWARD_MED (ISP_DPCC2_BASE + 0x000a4)
+
+#define ISP_HDRMGE_BASE 0x00003800
+#define ISP_HDRMGE_CTRL (ISP_HDRMGE_BASE + 0x00000)
+#define ISP_HDRMGE_GAIN0 (ISP_HDRMGE_BASE + 0x00008)
+#define ISP_HDRMGE_GAIN1 (ISP_HDRMGE_BASE + 0x0000c)
+#define ISP_HDRMGE_GAIN2 (ISP_HDRMGE_BASE + 0x00010)
+#define ISP_HDRMGE_CONS_DIFF (ISP_HDRMGE_BASE + 0x00014)
+#define ISP_HDRMGE_DIFF_Y0 (ISP_HDRMGE_BASE + 0x00020)
+#define ISP_HDRMGE_DIFF_Y1 (ISP_HDRMGE_BASE + 0x00024)
+#define ISP_HDRMGE_DIFF_Y2 (ISP_HDRMGE_BASE + 0x00028)
+#define ISP_HDRMGE_DIFF_Y3 (ISP_HDRMGE_BASE + 0x0002c)
+#define ISP_HDRMGE_DIFF_Y4 (ISP_HDRMGE_BASE + 0x00030)
+#define ISP_HDRMGE_DIFF_Y5 (ISP_HDRMGE_BASE + 0x00034)
+#define ISP_HDRMGE_DIFF_Y6 (ISP_HDRMGE_BASE + 0x00038)
+#define ISP_HDRMGE_DIFF_Y7 (ISP_HDRMGE_BASE + 0x0003c)
+#define ISP_HDRMGE_DIFF_Y8 (ISP_HDRMGE_BASE + 0x00040)
+#define ISP_HDRMGE_DIFF_Y9 (ISP_HDRMGE_BASE + 0x00044)
+#define ISP_HDRMGE_DIFF_Y10 (ISP_HDRMGE_BASE + 0x00048)
+#define ISP_HDRMGE_DIFF_Y11 (ISP_HDRMGE_BASE + 0x0004c)
+#define ISP_HDRMGE_DIFF_Y12 (ISP_HDRMGE_BASE + 0x00050)
+#define ISP_HDRMGE_DIFF_Y13 (ISP_HDRMGE_BASE + 0x00054)
+#define ISP_HDRMGE_DIFF_Y14 (ISP_HDRMGE_BASE + 0x00058)
+#define ISP_HDRMGE_DIFF_Y15 (ISP_HDRMGE_BASE + 0x0005c)
+#define ISP_HDRMGE_DIFF_Y16 (ISP_HDRMGE_BASE + 0x00060)
+#define ISP_HDRMGE_OVER_Y0 (ISP_HDRMGE_BASE + 0x00070)
+#define ISP_HDRMGE_OVER_Y1 (ISP_HDRMGE_BASE + 0x00074)
+#define ISP_HDRMGE_OVER_Y2 (ISP_HDRMGE_BASE + 0x00078)
+#define ISP_HDRMGE_OVER_Y3 (ISP_HDRMGE_BASE + 0x0007c)
+#define ISP_HDRMGE_OVER_Y4 (ISP_HDRMGE_BASE + 0x00080)
+#define ISP_HDRMGE_OVER_Y5 (ISP_HDRMGE_BASE + 0x00084)
+#define ISP_HDRMGE_OVER_Y6 (ISP_HDRMGE_BASE + 0x00088)
+#define ISP_HDRMGE_OVER_Y7 (ISP_HDRMGE_BASE + 0x0008c)
+#define ISP_HDRMGE_OVER_Y8 (ISP_HDRMGE_BASE + 0x00090)
+#define ISP_HDRMGE_OVER_Y9 (ISP_HDRMGE_BASE + 0x00094)
+#define ISP_HDRMGE_OVER_Y10 (ISP_HDRMGE_BASE + 0x00098)
+#define ISP_HDRMGE_OVER_Y11 (ISP_HDRMGE_BASE + 0x0009c)
+#define ISP_HDRMGE_OVER_Y12 (ISP_HDRMGE_BASE + 0x000a0)
+#define ISP_HDRMGE_OVER_Y13 (ISP_HDRMGE_BASE + 0x000a4)
+#define ISP_HDRMGE_OVER_Y14 (ISP_HDRMGE_BASE + 0x000a8)
+#define ISP_HDRMGE_OVER_Y15 (ISP_HDRMGE_BASE + 0x000ac)
+#define ISP_HDRMGE_OVER_Y16 (ISP_HDRMGE_BASE + 0x000b0)
+
+#define ISP_HDRTMO_BASE 0x00003900
+#define ISP_HDRTMO_CTRL (ISP_HDRTMO_BASE + 0x00000)
+#define ISP_HDRTMO_CTRL_CFG (ISP_HDRTMO_BASE + 0x00004)
+#define ISP_HDRTMO_LG_CFG0 (ISP_HDRTMO_BASE + 0x00008)
+#define ISP_HDRTMO_LG_CFG1 (ISP_HDRTMO_BASE + 0x0000c)
+#define ISP_HDRTMO_LG_CFG2 (ISP_HDRTMO_BASE + 0x00010)
+#define ISP_HDRTMO_LG_CFG3 (ISP_HDRTMO_BASE + 0x00014)
+#define ISP_HDRTMO_LG_CFG4 (ISP_HDRTMO_BASE + 0x00018)
+#define ISP_HDRTMO_CLIPRATIO (ISP_HDRTMO_BASE + 0x00020)
+#define ISP_HDRTMO_LG_SCL (ISP_HDRTMO_BASE + 0x00024)
+#define ISP_HDRTMO_LG_MAX (ISP_HDRTMO_BASE + 0x00028)
+#define ISP_HDRTMO_HIST_LOW (ISP_HDRTMO_BASE + 0x0002c)
+#define ISP_HDRTMO_HIST_HIGH (ISP_HDRTMO_BASE + 0x00030)
+#define ISP_HDRTMO_PALPHA (ISP_HDRTMO_BASE + 0x00034)
+#define ISP_HDRTMO_MAXGAIN (ISP_HDRTMO_BASE + 0x00038)
+#define ISP_HDRTMO_LG_RO0 (ISP_HDRTMO_BASE + 0x00040)
+#define ISP_HDRTMO_LG_RO1 (ISP_HDRTMO_BASE + 0x00044)
+#define ISP_HDRTMO_LG_RO2 (ISP_HDRTMO_BASE + 0x00048)
+#define ISP_HDRTMO_LG_RO3 (ISP_HDRTMO_BASE + 0x0004c)
+#define ISP_HDRTMO_LG_RO4 (ISP_HDRTMO_BASE + 0x00050)
+#define ISP_HDRTMO_LG_RO5 (ISP_HDRTMO_BASE + 0x00054)
+#define ISP_HDRTMO_HIST_RO0 (ISP_HDRTMO_BASE + 0x00060)
+#define ISP_HDRTMO_HIST_RO1 (ISP_HDRTMO_BASE + 0x00064)
+#define ISP_HDRTMO_HIST_RO2 (ISP_HDRTMO_BASE + 0x00068)
+#define ISP_HDRTMO_HIST_RO3 (ISP_HDRTMO_BASE + 0x0006c)
+#define ISP_HDRTMO_HIST_RO4 (ISP_HDRTMO_BASE + 0x00070)
+#define ISP_HDRTMO_HIST_RO5 (ISP_HDRTMO_BASE + 0x00074)
+#define ISP_HDRTMO_HIST_RO6 (ISP_HDRTMO_BASE + 0x00078)
+#define ISP_HDRTMO_HIST_RO7 (ISP_HDRTMO_BASE + 0x0007c)
+#define ISP_HDRTMO_HIST_RO8 (ISP_HDRTMO_BASE + 0x00080)
+#define ISP_HDRTMO_HIST_RO9 (ISP_HDRTMO_BASE + 0x00084)
+#define ISP_HDRTMO_HIST_RO10 (ISP_HDRTMO_BASE + 0x00088)
+#define ISP_HDRTMO_HIST_RO11 (ISP_HDRTMO_BASE + 0x0008c)
+#define ISP_HDRTMO_HIST_RO12 (ISP_HDRTMO_BASE + 0x00090)
+#define ISP_HDRTMO_HIST_RO13 (ISP_HDRTMO_BASE + 0x00094)
+#define ISP_HDRTMO_HIST_RO14 (ISP_HDRTMO_BASE + 0x00098)
+#define ISP_HDRTMO_HIST_RO15 (ISP_HDRTMO_BASE + 0x0009c)
+#define ISP_HDRTMO_HIST_RO16 (ISP_HDRTMO_BASE + 0x000a0)
+#define ISP_HDRTMO_HIST_RO17 (ISP_HDRTMO_BASE + 0x000a4)
+#define ISP_HDRTMO_HIST_RO18 (ISP_HDRTMO_BASE + 0x000a8)
+#define ISP_HDRTMO_HIST_RO19 (ISP_HDRTMO_BASE + 0x000ac)
+#define ISP_HDRTMO_HIST_RO20 (ISP_HDRTMO_BASE + 0x000b0)
+#define ISP_HDRTMO_HIST_RO21 (ISP_HDRTMO_BASE + 0x000b4)
+#define ISP_HDRTMO_HIST_RO22 (ISP_HDRTMO_BASE + 0x000b8)
+#define ISP_HDRTMO_HIST_RO23 (ISP_HDRTMO_BASE + 0x000bc)
+#define ISP_HDRTMO_HIST_RO24 (ISP_HDRTMO_BASE + 0x000c0)
+#define ISP_HDRTMO_HIST_RO25 (ISP_HDRTMO_BASE + 0x000c4)
+#define ISP_HDRTMO_HIST_RO26 (ISP_HDRTMO_BASE + 0x000c8)
+#define ISP_HDRTMO_HIST_RO27 (ISP_HDRTMO_BASE + 0x000cc)
+#define ISP_HDRTMO_HIST_RO28 (ISP_HDRTMO_BASE + 0x000d0)
+#define ISP_HDRTMO_HIST_RO29 (ISP_HDRTMO_BASE + 0x000d4)
+#define ISP_HDRTMO_HIST_RO30 (ISP_HDRTMO_BASE + 0x000d8)
+#define ISP_HDRTMO_HIST_RO31 (ISP_HDRTMO_BASE + 0x000dc)
+
+#define ISP21_DRC_BASE 0x00003900
+#define ISP21_DRC_CTRL0 (ISP21_DRC_BASE + 0x00000)
+#define ISP21_DRC_CTRL1 (ISP21_DRC_BASE + 0x00004)
+#define ISP21_DRC_LPRATIO (ISP21_DRC_BASE + 0x00008)
+#define ISP21_DRC_EXPLRATIO (ISP21_DRC_BASE + 0x0000c)
+#define ISP21_DRC_SIGMA (ISP21_DRC_BASE + 0x00010)
+#define ISP21_DRC_SPACESGM (ISP21_DRC_BASE + 0x00014)
+#define ISP21_DRC_RANESGM (ISP21_DRC_BASE + 0x00018)
+#define ISP21_DRC_BILAT (ISP21_DRC_BASE + 0x0001c)
+#define ISP21_DRC_GAIN_Y0 (ISP21_DRC_BASE + 0x00020)
+#define ISP21_DRC_GAIN_Y1 (ISP21_DRC_BASE + 0x00024)
+#define ISP21_DRC_GAIN_Y2 (ISP21_DRC_BASE + 0x00028)
+#define ISP21_DRC_GAIN_Y3 (ISP21_DRC_BASE + 0x0002c)
+#define ISP21_DRC_GAIN_Y4 (ISP21_DRC_BASE + 0x00030)
+#define ISP21_DRC_GAIN_Y5 (ISP21_DRC_BASE + 0x00034)
+#define ISP21_DRC_GAIN_Y6 (ISP21_DRC_BASE + 0x00038)
+#define ISP21_DRC_GAIN_Y7 (ISP21_DRC_BASE + 0x0003c)
+#define ISP21_DRC_GAIN_Y8 (ISP21_DRC_BASE + 0x00040)
+#define ISP21_DRC_COMPRES_Y0 (ISP21_DRC_BASE + 0x00044)
+#define ISP21_DRC_COMPRES_Y1 (ISP21_DRC_BASE + 0x00048)
+#define ISP21_DRC_COMPRES_Y2 (ISP21_DRC_BASE + 0x0004c)
+#define ISP21_DRC_COMPRES_Y3 (ISP21_DRC_BASE + 0x00050)
+#define ISP21_DRC_COMPRES_Y4 (ISP21_DRC_BASE + 0x00054)
+#define ISP21_DRC_COMPRES_Y5 (ISP21_DRC_BASE + 0x00058)
+#define ISP21_DRC_COMPRES_Y6 (ISP21_DRC_BASE + 0x0005c)
+#define ISP21_DRC_COMPRES_Y7 (ISP21_DRC_BASE + 0x00060)
+#define ISP21_DRC_COMPRES_Y8 (ISP21_DRC_BASE + 0x00064)
+#define ISP21_DRC_SCALE_Y0 (ISP21_DRC_BASE + 0x00068)
+#define ISP21_DRC_SCALE_Y1 (ISP21_DRC_BASE + 0x0006c)
+#define ISP21_DRC_SCALE_Y2 (ISP21_DRC_BASE + 0x00070)
+#define ISP21_DRC_SCALE_Y3 (ISP21_DRC_BASE + 0x00074)
+#define ISP21_DRC_SCALE_Y4 (ISP21_DRC_BASE + 0x00078)
+#define ISP21_DRC_SCALE_Y5 (ISP21_DRC_BASE + 0x0007c)
+#define ISP21_DRC_SCALE_Y6 (ISP21_DRC_BASE + 0x00080)
+#define ISP21_DRC_SCALE_Y7 (ISP21_DRC_BASE + 0x00084)
+#define ISP21_DRC_SCALE_Y8 (ISP21_DRC_BASE + 0x00088)
+#define ISP21_DRC_IIRWG_GAIN (ISP21_DRC_BASE + 0x0008c)
+
+#define ISP_RAWNR_BASE 0x00003A00
+#define ISP_RAWNR_CTRL (ISP_RAWNR_BASE + 0x00000)
+#define ISP_RAWNR_FILTPAR0 (ISP_RAWNR_BASE + 0x00008)
+#define ISP_RAWNR_FILTPAR1 (ISP_RAWNR_BASE + 0x0000c)
+#define ISP_RAWNR_FILTPAR2 (ISP_RAWNR_BASE + 0x00010)
+#define ISP_RAWNR_DGAIN0 (ISP_RAWNR_BASE + 0x00014)
+#define ISP_RAWNR_DGAIN1 (ISP_RAWNR_BASE + 0x00018)
+#define ISP_RAWNR_DGAIN2 (ISP_RAWNR_BASE + 0x0001c)
+#define ISP_RAWNR_LURTION0_1 (ISP_RAWNR_BASE + 0x00020)
+#define ISP_RAWNR_LURTION3_2 (ISP_RAWNR_BASE + 0x00024)
+#define ISP_RAWNR_LURTION5_4 (ISP_RAWNR_BASE + 0x00028)
+#define ISP_RAWNR_LURTION6_7 (ISP_RAWNR_BASE + 0x0002c)
+#define ISP_RAWNR_LULEVEL0_1 (ISP_RAWNR_BASE + 0x00030)
+#define ISP_RAWNR_LULEVEL2_3 (ISP_RAWNR_BASE + 0x00034)
+#define ISP_RAWNR_LULEVEL4_5 (ISP_RAWNR_BASE + 0x00038)
+#define ISP_RAWNR_LULEVEL6_7 (ISP_RAWNR_BASE + 0x0003c)
+#define ISP_RAWNR_GAUSS (ISP_RAWNR_BASE + 0x00040)
+#define ISP_RAWNR_SIGMA (ISP_RAWNR_BASE + 0x00044)
+#define ISP_RAWNR_PIX_DIFF (ISP_RAWNR_BASE + 0x00048)
+#define ISP_RAWNR_HILD_DIFF (ISP_RAWNR_BASE + 0x0004c)
+#define ISP_RAWNR_THLD_CHANELW (ISP_RAWNR_BASE + 0x00050)
+#define ISP_RAWNR_LAMDA (ISP_RAWNR_BASE + 0x00054)
+#define ISP_RAWNR_FIXW0_1 (ISP_RAWNR_BASE + 0x00058)
+#define ISP_RAWNR_FIXW2_3 (ISP_RAWNR_BASE + 0x0005c)
+#define ISP_RAWNR_WLAMDA0 (ISP_RAWNR_BASE + 0x00060)
+#define ISP_RAWNR_WLAMDA1 (ISP_RAWNR_BASE + 0x00064)
+#define ISP_RAWNR_WLAMDA2 (ISP_RAWNR_BASE + 0x00068)
+#define ISP_RAWNR_RGBAIN_FLIP (ISP_RAWNR_BASE + 0x0006c)
+
+#define ISP21_BAYNR_CTRL (ISP_RAWNR_BASE + 0x00000)
+#define ISP21_BAYNR_DGAIN0 (ISP_RAWNR_BASE + 0x00004)
+#define ISP21_BAYNR_DGAIN1 (ISP_RAWNR_BASE + 0x00008)
+#define ISP21_BAYNR_PIXDIFF (ISP_RAWNR_BASE + 0x0000c)
+#define ISP21_BAYNR_THLD (ISP_RAWNR_BASE + 0x00010)
+#define ISP21_BAYNR_W1_STRENG (ISP_RAWNR_BASE + 0x00014)
+#define ISP21_BAYNR_SIGMAX01 (ISP_RAWNR_BASE + 0x00018)
+#define ISP21_BAYNR_SIGMAX23 (ISP_RAWNR_BASE + 0x0001c)
+#define ISP21_BAYNR_SIGMAX45 (ISP_RAWNR_BASE + 0x00020)
+#define ISP21_BAYNR_SIGMAX67 (ISP_RAWNR_BASE + 0x00024)
+#define ISP21_BAYNR_SIGMAX89 (ISP_RAWNR_BASE + 0x00028)
+#define ISP21_BAYNR_SIGMAX1011 (ISP_RAWNR_BASE + 0x0002c)
+#define ISP21_BAYNR_SIGMAX1213 (ISP_RAWNR_BASE + 0x00030)
+#define ISP21_BAYNR_SIGMAX1415 (ISP_RAWNR_BASE + 0x00034)
+#define ISP21_BAYNR_SIGMAY01 (ISP_RAWNR_BASE + 0x00038)
+#define ISP21_BAYNR_SIGMAY23 (ISP_RAWNR_BASE + 0x0003c)
+#define ISP21_BAYNR_SIGMAY45 (ISP_RAWNR_BASE + 0x00040)
+#define ISP21_BAYNR_SIGMAY67 (ISP_RAWNR_BASE + 0x00044)
+#define ISP21_BAYNR_SIGMAY89 (ISP_RAWNR_BASE + 0x00048)
+#define ISP21_BAYNR_SIGMAY1011 (ISP_RAWNR_BASE + 0x0004c)
+#define ISP21_BAYNR_SIGMAY1213 (ISP_RAWNR_BASE + 0x00050)
+#define ISP21_BAYNR_SIGMAY1415 (ISP_RAWNR_BASE + 0x00054)
+#define ISP21_BAYNR_WRIT_D (ISP_RAWNR_BASE + 0x00058)
+
+#define ISP21_BAY3D_BASE 0x00003A00
+#define ISP21_BAY3D_CTRL (ISP21_BAY3D_BASE + 0x00080)
+#define ISP21_BAY3D_KALRATIO (ISP21_BAY3D_BASE + 0x00084)
+#define ISP21_BAY3D_GLBPK2 (ISP21_BAY3D_BASE + 0x00088)
+#define ISP21_BAY3D_KALSTR (ISP21_BAY3D_BASE + 0x0008c)
+#define ISP21_BAY3D_WGTLMT (ISP21_BAY3D_BASE + 0x00090)
+#define ISP21_BAY3D_SIG_X0 (ISP21_BAY3D_BASE + 0x00094)
+#define ISP21_BAY3D_SIG_X1 (ISP21_BAY3D_BASE + 0x00098)
+#define ISP21_BAY3D_SIG_X2 (ISP21_BAY3D_BASE + 0x0009c)
+#define ISP21_BAY3D_SIG_X3 (ISP21_BAY3D_BASE + 0x000a0)
+#define ISP21_BAY3D_SIG_X4 (ISP21_BAY3D_BASE + 0x000a4)
+#define ISP21_BAY3D_SIG_X5 (ISP21_BAY3D_BASE + 0x000a8)
+#define ISP21_BAY3D_SIG_X6 (ISP21_BAY3D_BASE + 0x000ac)
+#define ISP21_BAY3D_SIG_X7 (ISP21_BAY3D_BASE + 0x000b0)
+#define ISP21_BAY3D_SIG_Y0 (ISP21_BAY3D_BASE + 0x000b4)
+#define ISP21_BAY3D_SIG_Y1 (ISP21_BAY3D_BASE + 0x000b8)
+#define ISP21_BAY3D_SIG_Y2 (ISP21_BAY3D_BASE + 0x000bc)
+#define ISP21_BAY3D_SIG_Y3 (ISP21_BAY3D_BASE + 0x000c0)
+#define ISP21_BAY3D_SIG_Y4 (ISP21_BAY3D_BASE + 0x000c4)
+#define ISP21_BAY3D_SIG_Y5 (ISP21_BAY3D_BASE + 0x000c8)
+#define ISP21_BAY3D_SIG_Y6 (ISP21_BAY3D_BASE + 0x000cc)
+#define ISP21_BAY3D_SIG_Y7 (ISP21_BAY3D_BASE + 0x000d0)
+
+#define ISP_LDCH_BASE 0x00003B00
+#define ISP_LDCH_STS (ISP_LDCH_BASE + 0x00000)
+
+#define ISP_DHAZ_BASE 0x00003C00
+#define ISP_DHAZ_CTRL (ISP_DHAZ_BASE + 0x00000)
+#define ISP_DHAZ_ADP0 (ISP_DHAZ_BASE + 0x00004)
+#define ISP_DHAZ_ADP1 (ISP_DHAZ_BASE + 0x00008)
+#define ISP_DHAZ_ADP2 (ISP_DHAZ_BASE + 0x0000c)
+#define ISP_DHAZ_ADP_TMAX (ISP_DHAZ_BASE + 0x00010)
+#define ISP_DHAZ_ADP_HIST0 (ISP_DHAZ_BASE + 0x00014)
+#define ISP_DHAZ_ADP_HIST1 (ISP_DHAZ_BASE + 0x00018)
+#define ISP_DHAZ_HIST_ENH (ISP_DHAZ_BASE + 0x0001c)
+#define ISP_DHAZ_IIR0 (ISP_DHAZ_BASE + 0x00020)
+#define ISP_DHAZ_IIR1 (ISP_DHAZ_BASE + 0x00024)
+#define ISP_DHAZ_ALPHA0 (ISP_DHAZ_BASE + 0x00028)
+#define ISP_DHAZ_ALPHA1 (ISP_DHAZ_BASE + 0x0002c)
+#define ISP_DHAZ_BI_DC (ISP_DHAZ_BASE + 0x00030)
+#define ISP_DHAZ_DC_BF0 (ISP_DHAZ_BASE + 0x00034)
+#define ISP_DHAZ_DC_BF1 (ISP_DHAZ_BASE + 0x00038)
+#define ISP_DHAZ_BI_AIR (ISP_DHAZ_BASE + 0x0003c)
+#define ISP_DHAZ_AIR_BF (ISP_DHAZ_BASE + 0x00040)
+#define ISP_DHAZ_GAUS (ISP_DHAZ_BASE + 0x00044)
+#define ISP_DHAZ_HIST_CONV0 (ISP_DHAZ_BASE + 0x00048)
+#define ISP_DHAZ_HIST_CONV1 (ISP_DHAZ_BASE + 0x0004c)
+#define ISP_DHAZ_HIST_CONV2 (ISP_DHAZ_BASE + 0x00050)
+#define ISP_DHAZ_CTRL_SHD (ISP_DHAZ_BASE + 0x00060)
+#define ISP_DHAZ_ADP_RD0 (ISP_DHAZ_BASE + 0x00064)
+#define ISP_DHAZ_ADP_RD1 (ISP_DHAZ_BASE + 0x00068)
+#define ISP_DHAZ_HIST_REG0 (ISP_DHAZ_BASE + 0x00070)
+#define ISP_DHAZ_HIST_REG1 (ISP_DHAZ_BASE + 0x00074)
+#define ISP_DHAZ_HIST_REG2 (ISP_DHAZ_BASE + 0x00078)
+#define ISP_DHAZ_HIST_REG3 (ISP_DHAZ_BASE + 0x0007c)
+#define ISP_DHAZ_HIST_REG4 (ISP_DHAZ_BASE + 0x00080)
+#define ISP_DHAZ_HIST_REG5 (ISP_DHAZ_BASE + 0x00084)
+#define ISP_DHAZ_HIST_REG6 (ISP_DHAZ_BASE + 0x00088)
+#define ISP_DHAZ_HIST_REG7 (ISP_DHAZ_BASE + 0x0008c)
+#define ISP_DHAZ_HIST_REG8 (ISP_DHAZ_BASE + 0x00090)
+#define ISP_DHAZ_HIST_REG9 (ISP_DHAZ_BASE + 0x00094)
+#define ISP_DHAZ_HIST_REG10 (ISP_DHAZ_BASE + 0x00098)
+#define ISP_DHAZ_HIST_REG11 (ISP_DHAZ_BASE + 0x0009c)
+#define ISP_DHAZ_HIST_REG12 (ISP_DHAZ_BASE + 0x000a0)
+#define ISP_DHAZ_HIST_REG13 (ISP_DHAZ_BASE + 0x000a4)
+#define ISP_DHAZ_HIST_REG14 (ISP_DHAZ_BASE + 0x000a8)
+#define ISP_DHAZ_HIST_REG15 (ISP_DHAZ_BASE + 0x000ac)
+#define ISP_DHAZ_HIST_REG16 (ISP_DHAZ_BASE + 0x000b0)
+#define ISP_DHAZ_HIST_REG17 (ISP_DHAZ_BASE + 0x000b4)
+#define ISP_DHAZ_HIST_REG18 (ISP_DHAZ_BASE + 0x000b8)
+#define ISP_DHAZ_HIST_REG19 (ISP_DHAZ_BASE + 0x000bc)
+#define ISP_DHAZ_HIST_REG20 (ISP_DHAZ_BASE + 0x000c0)
+#define ISP_DHAZ_HIST_REG21 (ISP_DHAZ_BASE + 0x000c4)
+#define ISP_DHAZ_HIST_REG22 (ISP_DHAZ_BASE + 0x000c8)
+#define ISP_DHAZ_HIST_REG23 (ISP_DHAZ_BASE + 0x000cc)
+#define ISP_DHAZ_HIST_REG24 (ISP_DHAZ_BASE + 0x000d0)
+#define ISP_DHAZ_HIST_REG25 (ISP_DHAZ_BASE + 0x000d4)
+#define ISP_DHAZ_HIST_REG26 (ISP_DHAZ_BASE + 0x000d8)
+#define ISP_DHAZ_HIST_REG27 (ISP_DHAZ_BASE + 0x000dc)
+#define ISP_DHAZ_HIST_REG28 (ISP_DHAZ_BASE + 0x000e0)
+#define ISP_DHAZ_HIST_REG29 (ISP_DHAZ_BASE + 0x000e4)
+#define ISP_DHAZ_HIST_REG30 (ISP_DHAZ_BASE + 0x000e8)
+#define ISP_DHAZ_HIST_REG31 (ISP_DHAZ_BASE + 0x000ec)
+#define ISP_DHAZ_HIST_REG32 (ISP_DHAZ_BASE + 0x000f0)
+#define ISP_DHAZ_HIST_REG33 (ISP_DHAZ_BASE + 0x000f4)
+#define ISP_DHAZ_HIST_REG34 (ISP_DHAZ_BASE + 0x000f8)
+#define ISP_DHAZ_HIST_REG35 (ISP_DHAZ_BASE + 0x000fc)
+#define ISP_DHAZ_HIST_REG36 (ISP_DHAZ_BASE + 0x00100)
+#define ISP_DHAZ_HIST_REG37 (ISP_DHAZ_BASE + 0x00104)
+#define ISP_DHAZ_HIST_REG38 (ISP_DHAZ_BASE + 0x00108)
+#define ISP_DHAZ_HIST_REG39 (ISP_DHAZ_BASE + 0x0010c)
+#define ISP_DHAZ_HIST_REG40 (ISP_DHAZ_BASE + 0x00110)
+#define ISP_DHAZ_HIST_REG41 (ISP_DHAZ_BASE + 0x00114)
+#define ISP_DHAZ_HIST_REG42 (ISP_DHAZ_BASE + 0x00118)
+#define ISP_DHAZ_HIST_REG43 (ISP_DHAZ_BASE + 0x0011c)
+#define ISP_DHAZ_HIST_REG44 (ISP_DHAZ_BASE + 0x00120)
+#define ISP_DHAZ_HIST_REG45 (ISP_DHAZ_BASE + 0x00124)
+#define ISP_DHAZ_HIST_REG46 (ISP_DHAZ_BASE + 0x00128)
+#define ISP_DHAZ_HIST_REG47 (ISP_DHAZ_BASE + 0x0012c)
+#define ISP_DHAZ_HIST_REG48 (ISP_DHAZ_BASE + 0x00130)
+#define ISP_DHAZ_HIST_REG49 (ISP_DHAZ_BASE + 0x00134)
+#define ISP_DHAZ_HIST_REG50 (ISP_DHAZ_BASE + 0x00138)
+#define ISP_DHAZ_HIST_REG51 (ISP_DHAZ_BASE + 0x0013c)
+#define ISP_DHAZ_HIST_REG52 (ISP_DHAZ_BASE + 0x00140)
+#define ISP_DHAZ_HIST_REG53 (ISP_DHAZ_BASE + 0x00144)
+#define ISP_DHAZ_HIST_REG54 (ISP_DHAZ_BASE + 0x00148)
+#define ISP_DHAZ_HIST_REG55 (ISP_DHAZ_BASE + 0x0014c)
+#define ISP_DHAZ_HIST_REG56 (ISP_DHAZ_BASE + 0x00150)
+#define ISP_DHAZ_HIST_REG57 (ISP_DHAZ_BASE + 0x00154)
+#define ISP_DHAZ_HIST_REG58 (ISP_DHAZ_BASE + 0x00158)
+#define ISP_DHAZ_HIST_REG59 (ISP_DHAZ_BASE + 0x0015c)
+#define ISP_DHAZ_HIST_REG60 (ISP_DHAZ_BASE + 0x00160)
+#define ISP_DHAZ_HIST_REG61 (ISP_DHAZ_BASE + 0x00164)
+#define ISP_DHAZ_HIST_REG62 (ISP_DHAZ_BASE + 0x00168)
+#define ISP_DHAZ_HIST_REG63 (ISP_DHAZ_BASE + 0x0016c)
+#define ISP_DHAZ_HIST_REG64 (ISP_DHAZ_BASE + 0x00170)
+#define ISP_DHAZ_HIST_REG65 (ISP_DHAZ_BASE + 0x00174)
+#define ISP_DHAZ_HIST_REG66 (ISP_DHAZ_BASE + 0x00178)
+#define ISP_DHAZ_HIST_REG67 (ISP_DHAZ_BASE + 0x0017c)
+#define ISP_DHAZ_HIST_REG68 (ISP_DHAZ_BASE + 0x00180)
+#define ISP_DHAZ_HIST_REG69 (ISP_DHAZ_BASE + 0x00184)
+#define ISP_DHAZ_HIST_REG70 (ISP_DHAZ_BASE + 0x00188)
+#define ISP_DHAZ_HIST_REG71 (ISP_DHAZ_BASE + 0x0018c)
+#define ISP_DHAZ_HIST_REG72 (ISP_DHAZ_BASE + 0x00190)
+#define ISP_DHAZ_HIST_REG73 (ISP_DHAZ_BASE + 0x00194)
+#define ISP_DHAZ_HIST_REG74 (ISP_DHAZ_BASE + 0x00198)
+#define ISP_DHAZ_HIST_REG75 (ISP_DHAZ_BASE + 0x0019c)
+#define ISP_DHAZ_HIST_REG76 (ISP_DHAZ_BASE + 0x001a0)
+#define ISP_DHAZ_HIST_REG77 (ISP_DHAZ_BASE + 0x001a4)
+#define ISP_DHAZ_HIST_REG78 (ISP_DHAZ_BASE + 0x001a8)
+#define ISP_DHAZ_HIST_REG79 (ISP_DHAZ_BASE + 0x001ac)
+#define ISP_DHAZ_HIST_REG80 (ISP_DHAZ_BASE + 0x001b0)
+#define ISP_DHAZ_HIST_REG81 (ISP_DHAZ_BASE + 0x001b4)
+#define ISP_DHAZ_HIST_REG82 (ISP_DHAZ_BASE + 0x001b8)
+#define ISP_DHAZ_HIST_REG83 (ISP_DHAZ_BASE + 0x001bc)
+#define ISP_DHAZ_HIST_REG84 (ISP_DHAZ_BASE + 0x001c0)
+#define ISP_DHAZ_HIST_REG85 (ISP_DHAZ_BASE + 0x001c4)
+#define ISP_DHAZ_HIST_REG86 (ISP_DHAZ_BASE + 0x001c8)
+#define ISP_DHAZ_HIST_REG87 (ISP_DHAZ_BASE + 0x001cc)
+#define ISP_DHAZ_HIST_REG88 (ISP_DHAZ_BASE + 0x001d0)
+#define ISP_DHAZ_HIST_REG89 (ISP_DHAZ_BASE + 0x001d4)
+#define ISP_DHAZ_HIST_REG90 (ISP_DHAZ_BASE + 0x001d8)
+#define ISP_DHAZ_HIST_REG91 (ISP_DHAZ_BASE + 0x001dc)
+#define ISP_DHAZ_HIST_REG92 (ISP_DHAZ_BASE + 0x001e0)
+#define ISP_DHAZ_HIST_REG93 (ISP_DHAZ_BASE + 0x001e4)
+#define ISP_DHAZ_HIST_REG94 (ISP_DHAZ_BASE + 0x001e8)
+#define ISP_DHAZ_HIST_REG95 (ISP_DHAZ_BASE + 0x001ec)
+
+#define ISP21_DHAZ_CTRL (ISP_DHAZ_BASE + 0x00000)
+#define ISP21_DHAZ_ADP0 (ISP_DHAZ_BASE + 0x00004)
+#define ISP21_DHAZ_ADP1 (ISP_DHAZ_BASE + 0x00008)
+#define ISP21_DHAZ_ADP2 (ISP_DHAZ_BASE + 0x0000c)
+#define ISP21_DHAZ_ADP_TMAX (ISP_DHAZ_BASE + 0x00010)
+#define ISP21_DHAZ_ADP_HIST0 (ISP_DHAZ_BASE + 0x00014)
+#define ISP21_DHAZ_ADP_HIST1 (ISP_DHAZ_BASE + 0x00018)
+#define ISP21_DHAZ_ENHANCE (ISP_DHAZ_BASE + 0x0001c)
+#define ISP21_DHAZ_IIR0 (ISP_DHAZ_BASE + 0x00020)
+#define ISP21_DHAZ_IIR1 (ISP_DHAZ_BASE + 0x00024)
+#define ISP21_DHAZ_SOFT_CFG0 (ISP_DHAZ_BASE + 0x00028)
+#define ISP21_DHAZ_SOFT_CFG1 (ISP_DHAZ_BASE + 0x0002c)
+#define ISP21_DHAZ_BF_SIGMA (ISP_DHAZ_BASE + 0x00030)
+#define ISP21_DHAZ_BF_WET (ISP_DHAZ_BASE + 0x00034)
+#define ISP21_DHAZ_ENH_CURVE0 (ISP_DHAZ_BASE + 0x00038)
+#define ISP21_DHAZ_ENH_CURVE1 (ISP_DHAZ_BASE + 0x0003c)
+#define ISP21_DHAZ_ENH_CURVE2 (ISP_DHAZ_BASE + 0x00040)
+#define ISP21_DHAZ_ENH_CURVE3 (ISP_DHAZ_BASE + 0x00044)
+#define ISP21_DHAZ_ENH_CURVE4 (ISP_DHAZ_BASE + 0x00048)
+#define ISP21_DHAZ_ENH_CURVE5 (ISP_DHAZ_BASE + 0x0004c)
+#define ISP21_DHAZ_ENH_CURVE6 (ISP_DHAZ_BASE + 0x00050)
+#define ISP21_DHAZ_ENH_CURVE7 (ISP_DHAZ_BASE + 0x00054)
+#define ISP21_DHAZ_ENH_CURVE8 (ISP_DHAZ_BASE + 0x00058)
+#define ISP21_DHAZ_GAUS (ISP_DHAZ_BASE + 0x0005c)
+#define ISP21_DHAZ_CTRL_SHD (ISP_DHAZ_BASE + 0x00060)
+#define ISP21_DHAZ_ADP_RD0 (ISP_DHAZ_BASE + 0x00064)
+#define ISP21_DHAZ_ADP_RD1 (ISP_DHAZ_BASE + 0x00068)
+#define ISP21_DHAZ_HIST_REG0 (ISP_DHAZ_BASE + 0x00070)
+#define ISP21_DHAZ_HIST_REG1 (ISP_DHAZ_BASE + 0x00074)
+#define ISP21_DHAZ_HIST_REG2 (ISP_DHAZ_BASE + 0x00078)
+#define ISP21_DHAZ_HIST_REG3 (ISP_DHAZ_BASE + 0x0007c)
+#define ISP21_DHAZ_HIST_REG4 (ISP_DHAZ_BASE + 0x00080)
+#define ISP21_DHAZ_HIST_REG5 (ISP_DHAZ_BASE + 0x00084)
+#define ISP21_DHAZ_HIST_REG6 (ISP_DHAZ_BASE + 0x00088)
+#define ISP21_DHAZ_HIST_REG7 (ISP_DHAZ_BASE + 0x0008c)
+#define ISP21_DHAZ_HIST_REG8 (ISP_DHAZ_BASE + 0x00090)
+#define ISP21_DHAZ_HIST_REG9 (ISP_DHAZ_BASE + 0x00094)
+#define ISP21_DHAZ_HIST_REG10 (ISP_DHAZ_BASE + 0x00098)
+#define ISP21_DHAZ_HIST_REG11 (ISP_DHAZ_BASE + 0x0009c)
+#define ISP21_DHAZ_HIST_REG12 (ISP_DHAZ_BASE + 0x000a0)
+#define ISP21_DHAZ_HIST_REG13 (ISP_DHAZ_BASE + 0x000a4)
+#define ISP21_DHAZ_HIST_REG14 (ISP_DHAZ_BASE + 0x000a8)
+#define ISP21_DHAZ_HIST_REG15 (ISP_DHAZ_BASE + 0x000ac)
+#define ISP21_DHAZ_HIST_REG16 (ISP_DHAZ_BASE + 0x000b0)
+#define ISP21_DHAZ_HIST_REG17 (ISP_DHAZ_BASE + 0x000b4)
+#define ISP21_DHAZ_HIST_REG18 (ISP_DHAZ_BASE + 0x000b8)
+#define ISP21_DHAZ_HIST_REG19 (ISP_DHAZ_BASE + 0x000bc)
+#define ISP21_DHAZ_HIST_REG20 (ISP_DHAZ_BASE + 0x000c0)
+#define ISP21_DHAZ_HIST_REG21 (ISP_DHAZ_BASE + 0x000c4)
+#define ISP21_DHAZ_HIST_REG22 (ISP_DHAZ_BASE + 0x000c8)
+#define ISP21_DHAZ_HIST_REG23 (ISP_DHAZ_BASE + 0x000cc)
+#define ISP21_DHAZ_HIST_REG24 (ISP_DHAZ_BASE + 0x000d0)
+#define ISP21_DHAZ_HIST_REG25 (ISP_DHAZ_BASE + 0x000d4)
+#define ISP21_DHAZ_HIST_REG26 (ISP_DHAZ_BASE + 0x000d8)
+#define ISP21_DHAZ_HIST_REG27 (ISP_DHAZ_BASE + 0x000dc)
+#define ISP21_DHAZ_HIST_REG28 (ISP_DHAZ_BASE + 0x000e0)
+#define ISP21_DHAZ_HIST_REG29 (ISP_DHAZ_BASE + 0x000e4)
+#define ISP21_DHAZ_HIST_REG30 (ISP_DHAZ_BASE + 0x000e8)
+#define ISP21_DHAZ_HIST_REG31 (ISP_DHAZ_BASE + 0x000ec)
+
+#define ISP_3DLUT_BASE 0x00003E00
+#define ISP_3DLUT_CTRL (ISP_3DLUT_BASE + 0x00000)
+#define ISP_3DLUT_UPDATE (ISP_3DLUT_BASE + 0x00004)
+
+#define ISP_GAIN_BASE 0x00003F00
+#define ISP_GAIN_CTRL (ISP_GAIN_BASE + 0x00000)
+#define ISP_GAIN_G0 (ISP_GAIN_BASE + 0x00004)
+#define ISP_GAIN_G1_G2 (ISP_GAIN_BASE + 0x00008)
+#define ISP_GAIN_IDX0 (ISP_GAIN_BASE + 0x0000c)
+#define ISP_GAIN_IDX1 (ISP_GAIN_BASE + 0x00010)
+#define ISP_GAIN_IDX2 (ISP_GAIN_BASE + 0x00014)
+#define ISP_GAIN_IDX3 (ISP_GAIN_BASE + 0x00018)
+#define ISP_GAIN_LUT0 (ISP_GAIN_BASE + 0x0001c)
+#define ISP_GAIN_LUT1 (ISP_GAIN_BASE + 0x00020)
+#define ISP_GAIN_LUT2 (ISP_GAIN_BASE + 0x00024)
+#define ISP_GAIN_LUT3 (ISP_GAIN_BASE + 0x00028)
+#define ISP_GAIN_LUT4 (ISP_GAIN_BASE + 0x0002c)
+#define ISP_GAIN_LUT5 (ISP_GAIN_BASE + 0x00030)
+#define ISP_GAIN_LUT6 (ISP_GAIN_BASE + 0x00034)
+#define ISP_GAIN_LUT7 (ISP_GAIN_BASE + 0x00038)
+#define ISP_GAIN_LUT8 (ISP_GAIN_BASE + 0x0003c)
+
+#define ISP_AFM_BASE 0x00004100
+#define ISP_AFM_CTRL (ISP_AFM_BASE + 0x00000)
+#define ISP_AFM_LT_A (ISP_AFM_BASE + 0x00004)
+#define ISP_AFM_RB_A (ISP_AFM_BASE + 0x00008)
+#define ISP_AFM_LT_B (ISP_AFM_BASE + 0x0000c)
+#define ISP_AFM_RB_B (ISP_AFM_BASE + 0x00010)
+#define ISP_AFM_LT_C (ISP_AFM_BASE + 0x00014)
+#define ISP_AFM_RB_C (ISP_AFM_BASE + 0x00018)
+#define ISP_AFM_THRES (ISP_AFM_BASE + 0x0001c)
+#define ISP_AFM_VAR_SHIFT (ISP_AFM_BASE + 0x00020)
+#define ISP_AFM_SUM_A (ISP_AFM_BASE + 0x00024)
+#define ISP_AFM_SUM_B (ISP_AFM_BASE + 0x00028)
+#define ISP_AFM_SUM_C (ISP_AFM_BASE + 0x0002c)
+#define ISP_AFM_LUM_A (ISP_AFM_BASE + 0x00030)
+#define ISP_AFM_LUM_B (ISP_AFM_BASE + 0x00034)
+#define ISP_AFM_LUM_C (ISP_AFM_BASE + 0x00038)
+
+#define ISP_HIST_BASE 0x00004200
+#define ISP_HIST_HIST_CTRL (ISP_HIST_BASE + 0x00000)
+#define ISP_HIST_HIST_SIZE (ISP_HIST_BASE + 0x00004)
+#define ISP_HIST_HIST_OFFS (ISP_HIST_BASE + 0x00008)
+#define ISP_HIST_HIST_DBG1 (ISP_HIST_BASE + 0x0000c)
+#define ISP_HIST_HIST1_CTRL (ISP_HIST_BASE + 0x00010)
+#define ISP_HIST_HIST1_SIZE (ISP_HIST_BASE + 0x00014)
+#define ISP_HIST_HIST1_OFFS (ISP_HIST_BASE + 0x00018)
+#define ISP_HIST_HIST_DBG2 (ISP_HIST_BASE + 0x0001c)
+#define ISP_HIST_HIST2_CTRL (ISP_HIST_BASE + 0x00020)
+#define ISP_HIST_HIST2_SIZE (ISP_HIST_BASE + 0x00024)
+#define ISP_HIST_HIST2_OFFS (ISP_HIST_BASE + 0x00028)
+#define ISP_HIST_HIST_DBG3 (ISP_HIST_BASE + 0x0002c)
+#define ISP_HIST_HIST3_CTRL (ISP_HIST_BASE + 0x00030)
+#define ISP_HIST_HIST3_SIZE (ISP_HIST_BASE + 0x00034)
+#define ISP_HIST_HIST3_OFFS (ISP_HIST_BASE + 0x00038)
+#define ISP_HIST_HIST_WEIGHT_0 (ISP_HIST_BASE + 0x0003c)
+#define ISP_HIST_HIST_BIN (ISP_HIST_BASE + 0x00120)
+#define ISP_HIST_HIST1_BIN (ISP_HIST_BASE + 0x00160)
+#define ISP_HIST_HIST2_BIN (ISP_HIST_BASE + 0x001a0)
+#define ISP_HIST_HIST3_BIN (ISP_HIST_BASE + 0x001e0)
+#define ISP_HIST_HIST1_DBG1 (ISP_HIST_BASE + 0x00220)
+#define ISP_HIST_HIST1_DBG2 (ISP_HIST_BASE + 0x00224)
+#define ISP_HIST_HIST2_DBG1 (ISP_HIST_BASE + 0x00228)
+#define ISP_HIST_HIST2_DBG2 (ISP_HIST_BASE + 0x0022c)
+#define ISP_HIST_HIST3_DBG1 (ISP_HIST_BASE + 0x00230)
+#define ISP_HIST_HIST3_DBG2 (ISP_HIST_BASE + 0x00234)
+
+#define RAWAE_BIG1_BASE 0x00004400
+#define RAWAE_BIG2_BASE 0x00004600
+#define RAWAE_BIG3_BASE 0x00004700
+#define RAWAE_BIG_CTRL (0x00000)
+#define RAWAE_BIG_BLK_SIZE (0x00004)
+#define RAWAE_BIG_OFFSET (0x00008)
+#define RAWAE_BIG_RAM_CTRL (0x0000c)
+#define RAWAE_BIG_WND1_SIZE (0x00010)
+#define RAWAE_BIG_WND1_OFFSET (0x00014)
+#define RAWAE_BIG_WND2_SIZE (0x00018)
+#define RAWAE_BIG_WND2_OFFSET (0x0001c)
+#define RAWAE_BIG_WND3_SIZE (0x00020)
+#define RAWAE_BIG_WND3_OFFSET (0x00024)
+#define RAWAE_BIG_WND4_SIZE (0x00028)
+#define RAWAE_BIG_WND4_OFFSET (0x0002c)
+#define RAWAE_BIG_WND1_SUMR (0x00030)
+#define RAWAE_BIG_WND2_SUMR (0x00034)
+#define RAWAE_BIG_WND3_SUMR (0x00038)
+#define RAWAE_BIG_WND4_SUMR (0x0003c)
+#define RAWAE_BIG_WND1_SUMG (0x00040)
+#define RAWAE_BIG_WND2_SUMG (0x00044)
+#define RAWAE_BIG_WND3_SUMG (0x00048)
+#define RAWAE_BIG_WND4_SUMG (0x0004c)
+#define RAWAE_BIG_WND1_SUMB (0x00050)
+#define RAWAE_BIG_WND2_SUMB (0x00054)
+#define RAWAE_BIG_WND3_SUMB (0x00058)
+#define RAWAE_BIG_WND4_SUMB (0x0005c)
+#define RAWAE_BIG_RO_DBG1 (0x00060)
+#define RAWAE_BIG_RO_DBG2 (0x00064)
+#define RAWAE_BIG_RO_DBG3 (0x00068)
+#define RAWAE_BIG_RO_MEAN_BASE_ADDR (0x00080)
+
+#define ISP_RAWAE_LITE_BASE 0x00004500
+#define ISP_RAWAE_LITE_CTRL (ISP_RAWAE_LITE_BASE + 0x00000)
+#define ISP_RAWAE_LITE_BLK_SIZ (ISP_RAWAE_LITE_BASE + 0x00004)
+#define ISP_RAWAE_LITE_OFFSET (ISP_RAWAE_LITE_BASE + 0x00008)
+#define ISP_RAWAE_LITE_R2Y_CC (ISP_RAWAE_LITE_BASE + 0x0000c)
+#define ISP_RAWAE_LITE_RO_MEAN (ISP_RAWAE_LITE_BASE + 0x00010)
+#define ISP_RAWAE_LITE_RO_DBG1 (ISP_RAWAE_LITE_BASE + 0x00074)
+#define ISP_RAWAE_LITE_RO_DBG2 (ISP_RAWAE_LITE_BASE + 0x00078)
+
+#define ISP_RAWHIST_LITE_BASE 0x00004900
+#define ISP_RAWHIST_LITE_CTRL (ISP_RAWHIST_LITE_BASE + 0x00000)
+#define ISP_RAWHIST_LITE_SIZE (ISP_RAWHIST_LITE_BASE + 0x00004)
+#define ISP_RAWHIST_LITE_OFFS (ISP_RAWHIST_LITE_BASE + 0x00008)
+#define ISP_RAWHIST_LITE_RAM_CTRL (ISP_RAWHIST_LITE_BASE + 0x0000c)
+#define ISP_RAWHIST_LITE_RAW2Y_CC (ISP_RAWHIST_LITE_BASE + 0x00010)
+#define ISP_RAWHIST_LITE_DBG1 (ISP_RAWHIST_LITE_BASE + 0x00020)
+#define ISP_RAWHIST_LITE_DBG2 (ISP_RAWHIST_LITE_BASE + 0x00024)
+#define ISP_RAWHIST_LITE_DBG3 (ISP_RAWHIST_LITE_BASE + 0x00028)
+#define ISP_RAWHIST_LITE_WEIGHT (ISP_RAWHIST_LITE_BASE + 0x00040)
+#define ISP_RAWHIST_LITE_RO_BASE_BIN (ISP_RAWHIST_LITE_BASE + 0x00080)
+
+#define ISP_RAWHIST_BIG1_BASE 0x00004800
+#define ISP_RAWHIST_BIG2_BASE 0x00004A00
+#define ISP_RAWHIST_BIG3_BASE 0x00004B00
+#define ISP_RAWHIST_BIG_CTRL (0x00000)
+#define ISP_RAWHIST_BIG_SIZE (0x00004)
+#define ISP_RAWHIST_BIG_OFFS (0x00008)
+#define ISP_RAWHIST_BIG_HRAM_CTRL (0x0000c)
+#define ISP_RAWHIST_BIG_RAW2Y_CC (0x00010)
+#define ISP_RAWHIST_BIG_WRAM_CTRL (0x00014)
+#define ISP_RAWHIST_BIG_DBG1 (0x00020)
+#define ISP_RAWHIST_BIG_DBG2 (0x00024)
+#define ISP_RAWHIST_BIG_DBG3 (0x00028)
+#define ISP_RAWHIST_BIG_WEIGHT_BASE (0x00040)
+#define ISP_RAWHIST_BIG_RO_BASE_BIN (0x00080)
+
+#define ISP_YUVAE_BASE 0x00004C00
+#define ISP_YUVAE_CTRL (ISP_YUVAE_BASE + 0x00000)
+#define ISP_YUVAE_BLK_SIZE (ISP_YUVAE_BASE + 0x00004)
+#define ISP_YUVAE_OFFSET (ISP_YUVAE_BASE + 0x00008)
+#define ISP_YUVAE_RAM_CTRL (ISP_YUVAE_BASE + 0x0000c)
+#define ISP_YUVAE_WND1_SIZE (ISP_YUVAE_BASE + 0x00010)
+#define ISP_YUVAE_WND1_OFFSET (ISP_YUVAE_BASE + 0x00014)
+#define ISP_YUVAE_WND2_SIZE (ISP_YUVAE_BASE + 0x00018)
+#define ISP_YUVAE_WND2_OFFSET (ISP_YUVAE_BASE + 0x0001c)
+#define ISP_YUVAE_WND3_SIZE (ISP_YUVAE_BASE + 0x00020)
+#define ISP_YUVAE_WND3_OFFSET (ISP_YUVAE_BASE + 0x00024)
+#define ISP_YUVAE_WND4_SIZE (ISP_YUVAE_BASE + 0x00028)
+#define ISP_YUVAE_WND4_OFFSET (ISP_YUVAE_BASE + 0x0002c)
+#define ISP_YUVAE_WND1_SUMY (ISP_YUVAE_BASE + 0x00030)
+#define ISP_YUVAE_WND2_SUMY (ISP_YUVAE_BASE + 0x00034)
+#define ISP_YUVAE_WND3_SUMY (ISP_YUVAE_BASE + 0x00038)
+#define ISP_YUVAE_WND4_SUMY (ISP_YUVAE_BASE + 0x0003c)
+#define ISP_YUVAE_RO_DBG1 (ISP_YUVAE_BASE + 0x00040)
+#define ISP_YUVAE_RO_DBG2 (ISP_YUVAE_BASE + 0x00044)
+#define ISP_YUVAE_RO_DBG3 (ISP_YUVAE_BASE + 0x00048)
+#define ISP_YUVAE_RO_MEAN_BASE_ADDR (ISP_YUVAE_BASE + 0x00080)
+
+#define ISP_RAWAF_BASE 0x00004D00
+#define ISP_RAWAF_CTRL (ISP_RAWAF_BASE + 0x00000)
+#define ISP_RAWAF_LT_A (ISP_RAWAF_BASE + 0x00004)
+#define ISP_RAWAF_RB_A (ISP_RAWAF_BASE + 0x00008)
+#define ISP_RAWAF_LT_B (ISP_RAWAF_BASE + 0x0000c)
+#define ISP_RAWAF_RB_B (ISP_RAWAF_BASE + 0x00010)
+#define ISP_RAWAF_INT_LINE (ISP_RAWAF_BASE + 0x00014)
+#define ISP_RAWAF_GAUS_COE (ISP_RAWAF_BASE + 0x00018)
+#define ISP_RAWAF_THRES (ISP_RAWAF_BASE + 0x0001c)
+#define ISP_RAWAF_VAR_SHIFT (ISP_RAWAF_BASE + 0x00020)
+#define ISP_RAWAF_SUM_A (ISP_RAWAF_BASE + 0x00024)
+#define ISP_RAWAF_SUM_B (ISP_RAWAF_BASE + 0x00028)
+#define ISP_RAWAF_LUM_A (ISP_RAWAF_BASE + 0x0002c)
+#define ISP_RAWAF_LUM_B (ISP_RAWAF_BASE + 0x00030)
+#define ISP_RAWAF_GAMMA_Y0 (ISP_RAWAF_BASE + 0x00034)
+#define ISP_RAWAF_GAMMA_Y1 (ISP_RAWAF_BASE + 0x00038)
+#define ISP_RAWAF_GAMMA_Y2 (ISP_RAWAF_BASE + 0x0003c)
+#define ISP_RAWAF_GAMMA_Y3 (ISP_RAWAF_BASE + 0x00040)
+#define ISP_RAWAF_GAMMA_Y4 (ISP_RAWAF_BASE + 0x00044)
+#define ISP_RAWAF_GAMMA_Y5 (ISP_RAWAF_BASE + 0x00048)
+#define ISP_RAWAF_GAMMA_Y6 (ISP_RAWAF_BASE + 0x0004c)
+#define ISP_RAWAF_GAMMA_Y7 (ISP_RAWAF_BASE + 0x00050)
+#define ISP_RAWAF_GAMMA_Y8 (ISP_RAWAF_BASE + 0x00054)
+#define ISP_RAWAF_INT_STATE (ISP_RAWAF_BASE + 0x00058)
+#define ISP_RAWAF_RAM_DATA (ISP_RAWAF_BASE + 0x0005c)
+
+#define ISP_RAWAWB_BASE 0x00005000
+#define ISP_RAWAWB_CTRL (ISP_RAWAWB_BASE + 0x00000)
+#define ISP_RAWAWB_BLK_CTRL (ISP_RAWAWB_BASE + 0x00004)
+#define ISP_RAWAWB_WIN_OFFS (ISP_RAWAWB_BASE + 0x00008)
+#define ISP_RAWAWB_WIN_SIZE (ISP_RAWAWB_BASE + 0x0000c)
+#define ISP_RAWAWB_LIMIT_RG_MAX (ISP_RAWAWB_BASE + 0x00010)
+#define ISP_RAWAWB_LIMIT_BY_MAX (ISP_RAWAWB_BASE + 0x00014)
+#define ISP_RAWAWB_LIMIT_RG_MIN (ISP_RAWAWB_BASE + 0x00018)
+#define ISP_RAWAWB_LIMIT_BY_MIN (ISP_RAWAWB_BASE + 0x0001c)
+#define ISP_RAWAWB_RGB2Y_0 (ISP_RAWAWB_BASE + 0x00020)
+#define ISP_RAWAWB_RGB2Y_1 (ISP_RAWAWB_BASE + 0x00024)
+#define ISP_RAWAWB_RGB2U_0 (ISP_RAWAWB_BASE + 0x00028)
+#define ISP_RAWAWB_RGB2U_1 (ISP_RAWAWB_BASE + 0x0002c)
+#define ISP_RAWAWB_RGB2V_0 (ISP_RAWAWB_BASE + 0x00030)
+#define ISP_RAWAWB_RGB2V_1 (ISP_RAWAWB_BASE + 0x00034)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_0 (ISP_RAWAWB_BASE + 0x00038)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_0 (ISP_RAWAWB_BASE + 0x0003c)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_0 (ISP_RAWAWB_BASE + 0x00040)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_0 (ISP_RAWAWB_BASE + 0x00044)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_0 (ISP_RAWAWB_BASE + 0x00048)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_0 (ISP_RAWAWB_BASE + 0x0004c)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_0 (ISP_RAWAWB_BASE + 0x00050)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_0 (ISP_RAWAWB_BASE + 0x00054)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_1 (ISP_RAWAWB_BASE + 0x00058)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_1 (ISP_RAWAWB_BASE + 0x0005c)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_1 (ISP_RAWAWB_BASE + 0x00060)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_1 (ISP_RAWAWB_BASE + 0x00064)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_1 (ISP_RAWAWB_BASE + 0x00068)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_1 (ISP_RAWAWB_BASE + 0x0006c)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_1 (ISP_RAWAWB_BASE + 0x00070)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_1 (ISP_RAWAWB_BASE + 0x00074)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_2 (ISP_RAWAWB_BASE + 0x00078)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_2 (ISP_RAWAWB_BASE + 0x0007c)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_2 (ISP_RAWAWB_BASE + 0x00080)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_2 (ISP_RAWAWB_BASE + 0x00084)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_2 (ISP_RAWAWB_BASE + 0x00088)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_2 (ISP_RAWAWB_BASE + 0x0008c)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_2 (ISP_RAWAWB_BASE + 0x00090)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_2 (ISP_RAWAWB_BASE + 0x00094)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_3 (ISP_RAWAWB_BASE + 0x00098)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_3 (ISP_RAWAWB_BASE + 0x0009c)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_3 (ISP_RAWAWB_BASE + 0x000a0)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_3 (ISP_RAWAWB_BASE + 0x000a4)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_3 (ISP_RAWAWB_BASE + 0x000a8)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_3 (ISP_RAWAWB_BASE + 0x000ac)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_3 (ISP_RAWAWB_BASE + 0x000b0)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_3 (ISP_RAWAWB_BASE + 0x000b4)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_4 (ISP_RAWAWB_BASE + 0x000b8)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_4 (ISP_RAWAWB_BASE + 0x000bc)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_4 (ISP_RAWAWB_BASE + 0x000c0)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_4 (ISP_RAWAWB_BASE + 0x000c4)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_4 (ISP_RAWAWB_BASE + 0x000c8)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_4 (ISP_RAWAWB_BASE + 0x000cc)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_4 (ISP_RAWAWB_BASE + 0x000d0)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_4 (ISP_RAWAWB_BASE + 0x000d4)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_5 (ISP_RAWAWB_BASE + 0x000d8)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_5 (ISP_RAWAWB_BASE + 0x000dc)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_5 (ISP_RAWAWB_BASE + 0x000e0)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_5 (ISP_RAWAWB_BASE + 0x000e4)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_5 (ISP_RAWAWB_BASE + 0x000e8)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_5 (ISP_RAWAWB_BASE + 0x000ec)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_5 (ISP_RAWAWB_BASE + 0x000f0)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_5 (ISP_RAWAWB_BASE + 0x000f4)
+#define ISP_RAWAWB_UV_DETC_VERTEX0_6 (ISP_RAWAWB_BASE + 0x000f8)
+#define ISP_RAWAWB_UV_DETC_VERTEX1_6 (ISP_RAWAWB_BASE + 0x000fc)
+#define ISP_RAWAWB_UV_DETC_VERTEX2_6 (ISP_RAWAWB_BASE + 0x00100)
+#define ISP_RAWAWB_UV_DETC_VERTEX3_6 (ISP_RAWAWB_BASE + 0x00104)
+#define ISP_RAWAWB_UV_DETC_ISLOPE01_6 (ISP_RAWAWB_BASE + 0x00108)
+#define ISP_RAWAWB_UV_DETC_ISLOPE12_6 (ISP_RAWAWB_BASE + 0x0010c)
+#define ISP_RAWAWB_UV_DETC_ISLOPE23_6 (ISP_RAWAWB_BASE + 0x00110)
+#define ISP_RAWAWB_UV_DETC_ISLOPE30_6 (ISP_RAWAWB_BASE + 0x00114)
+#define ISP_RAWAWB_YUV_DETC_B_UV_0 (ISP_RAWAWB_BASE + 0x00118)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_0 (ISP_RAWAWB_BASE + 0x0011c)
+#define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_0 (ISP_RAWAWB_BASE + 0x00120)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_0 (ISP_RAWAWB_BASE + 0x00124)
+#define ISP_RAWAWB_YUV_DETC_B_YDIS_0 (ISP_RAWAWB_BASE + 0x00128)
+#define ISP_RAWAWB_YUV_DETC_B_UV_1 (ISP_RAWAWB_BASE + 0x0012c)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_1 (ISP_RAWAWB_BASE + 0x00130)
+#define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_1 (ISP_RAWAWB_BASE + 0x00134)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_1 (ISP_RAWAWB_BASE + 0x00138)
+#define ISP_RAWAWB_YUV_DETC_B_YDIS_1 (ISP_RAWAWB_BASE + 0x0013c)
+#define ISP_RAWAWB_YUV_DETC_B_UV_2 (ISP_RAWAWB_BASE + 0x00140)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_2 (ISP_RAWAWB_BASE + 0x00144)
+#define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_2 (ISP_RAWAWB_BASE + 0x00148)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_2 (ISP_RAWAWB_BASE + 0x0014c)
+#define ISP_RAWAWB_YUV_DETC_B_YDIS_2 (ISP_RAWAWB_BASE + 0x00150)
+#define ISP_RAWAWB_YUV_DETC_B_UV_3 (ISP_RAWAWB_BASE + 0x00154)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_3 (ISP_RAWAWB_BASE + 0x00158)
+#define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_3 (ISP_RAWAWB_BASE + 0x0015c)
+#define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_3 (ISP_RAWAWB_BASE + 0x00160)
+#define ISP_RAWAWB_YUV_DETC_B_YDIS_3 (ISP_RAWAWB_BASE + 0x00164)
+#define ISP_RAWAWB_YUV_DETC_REF_U (ISP_RAWAWB_BASE + 0x00168)
+#define ISP_RAWAWB_YUV_DETC_REF_V (ISP_RAWAWB_BASE + 0x0016c)
+#define ISP_RAWAWB_YUV_DETC_DIS01_0 (ISP_RAWAWB_BASE + 0x00170)
+#define ISP_RAWAWB_YUV_DETC_DIS23_0 (ISP_RAWAWB_BASE + 0x00174)
+#define ISP_RAWAWB_YUV_DETC_DIS45_0 (ISP_RAWAWB_BASE + 0x00178)
+#define ISP_RAWAWB_YUV_DETC_TH03_0 (ISP_RAWAWB_BASE + 0x0017c)
+#define ISP_RAWAWB_YUV_DETC_TH45_0 (ISP_RAWAWB_BASE + 0x00180)
+#define ISP_RAWAWB_YUV_DETC_DIS01_1 (ISP_RAWAWB_BASE + 0x00184)
+#define ISP_RAWAWB_YUV_DETC_DIS23_1 (ISP_RAWAWB_BASE + 0x00188)
+#define ISP_RAWAWB_YUV_DETC_DIS45_1 (ISP_RAWAWB_BASE + 0x0018c)
+#define ISP_RAWAWB_YUV_DETC_TH03_1 (ISP_RAWAWB_BASE + 0x00190)
+#define ISP_RAWAWB_YUV_DETC_TH45_1 (ISP_RAWAWB_BASE + 0x00194)
+#define ISP_RAWAWB_YUV_DETC_DIS01_2 (ISP_RAWAWB_BASE + 0x00198)
+#define ISP_RAWAWB_YUV_DETC_DIS23_2 (ISP_RAWAWB_BASE + 0x0019c)
+#define ISP_RAWAWB_YUV_DETC_DIS45_2 (ISP_RAWAWB_BASE + 0x001a0)
+#define ISP_RAWAWB_YUV_DETC_TH03_2 (ISP_RAWAWB_BASE + 0x001a4)
+#define ISP_RAWAWB_YUV_DETC_TH45_2 (ISP_RAWAWB_BASE + 0x001a8)
+#define ISP_RAWAWB_YUV_DETC_DIS01_3 (ISP_RAWAWB_BASE + 0x001ac)
+#define ISP_RAWAWB_YUV_DETC_DIS23_3 (ISP_RAWAWB_BASE + 0x001b0)
+#define ISP_RAWAWB_YUV_DETC_DIS45_3 (ISP_RAWAWB_BASE + 0x001b4)
+#define ISP_RAWAWB_YUV_DETC_TH03_3 (ISP_RAWAWB_BASE + 0x001b8)
+#define ISP_RAWAWB_YUV_DETC_TH45_3 (ISP_RAWAWB_BASE + 0x001bc)
+#define ISP_RAWAWB_RGB2XY_WT01 (ISP_RAWAWB_BASE + 0x001fc)
+#define ISP_RAWAWB_RGB2XY_WT2 (ISP_RAWAWB_BASE + 0x00200)
+#define ISP_RAWAWB_RGB2XY_MAT0_XY (ISP_RAWAWB_BASE + 0x00204)
+#define ISP_RAWAWB_RGB2XY_MAT1_XY (ISP_RAWAWB_BASE + 0x00208)
+#define ISP_RAWAWB_RGB2XY_MAT2_XY (ISP_RAWAWB_BASE + 0x0020c)
+#define ISP_RAWAWB_XY_DETC_NOR_X_0 (ISP_RAWAWB_BASE + 0x00210)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_0 (ISP_RAWAWB_BASE + 0x00214)
+#define ISP_RAWAWB_XY_DETC_BIG_X_0 (ISP_RAWAWB_BASE + 0x00218)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_0 (ISP_RAWAWB_BASE + 0x0021c)
+#define ISP_RAWAWB_XY_DETC_SMA_X_0 (ISP_RAWAWB_BASE + 0x00220)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_0 (ISP_RAWAWB_BASE + 0x00224)
+#define ISP_RAWAWB_XY_DETC_NOR_X_1 (ISP_RAWAWB_BASE + 0x00228)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_1 (ISP_RAWAWB_BASE + 0x0022c)
+#define ISP_RAWAWB_XY_DETC_BIG_X_1 (ISP_RAWAWB_BASE + 0x00230)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_1 (ISP_RAWAWB_BASE + 0x00234)
+#define ISP_RAWAWB_XY_DETC_SMA_X_1 (ISP_RAWAWB_BASE + 0x00238)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_1 (ISP_RAWAWB_BASE + 0x0023c)
+#define ISP_RAWAWB_XY_DETC_NOR_X_2 (ISP_RAWAWB_BASE + 0x00240)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_2 (ISP_RAWAWB_BASE + 0x00244)
+#define ISP_RAWAWB_XY_DETC_BIG_X_2 (ISP_RAWAWB_BASE + 0x00248)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_2 (ISP_RAWAWB_BASE + 0x0024c)
+#define ISP_RAWAWB_XY_DETC_SMA_X_2 (ISP_RAWAWB_BASE + 0x00250)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_2 (ISP_RAWAWB_BASE + 0x00254)
+#define ISP_RAWAWB_XY_DETC_NOR_X_3 (ISP_RAWAWB_BASE + 0x00258)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_3 (ISP_RAWAWB_BASE + 0x0025c)
+#define ISP_RAWAWB_XY_DETC_BIG_X_3 (ISP_RAWAWB_BASE + 0x00260)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_3 (ISP_RAWAWB_BASE + 0x00264)
+#define ISP_RAWAWB_XY_DETC_SMA_X_3 (ISP_RAWAWB_BASE + 0x00268)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_3 (ISP_RAWAWB_BASE + 0x0026c)
+#define ISP_RAWAWB_XY_DETC_NOR_X_4 (ISP_RAWAWB_BASE + 0x00270)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_4 (ISP_RAWAWB_BASE + 0x00274)
+#define ISP_RAWAWB_XY_DETC_BIG_X_4 (ISP_RAWAWB_BASE + 0x00278)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_4 (ISP_RAWAWB_BASE + 0x0027c)
+#define ISP_RAWAWB_XY_DETC_SMA_X_4 (ISP_RAWAWB_BASE + 0x00280)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_4 (ISP_RAWAWB_BASE + 0x00284)
+#define ISP_RAWAWB_XY_DETC_NOR_X_5 (ISP_RAWAWB_BASE + 0x00288)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_5 (ISP_RAWAWB_BASE + 0x0028c)
+#define ISP_RAWAWB_XY_DETC_BIG_X_5 (ISP_RAWAWB_BASE + 0x00290)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_5 (ISP_RAWAWB_BASE + 0x00294)
+#define ISP_RAWAWB_XY_DETC_SMA_X_5 (ISP_RAWAWB_BASE + 0x00298)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_5 (ISP_RAWAWB_BASE + 0x0029c)
+#define ISP_RAWAWB_XY_DETC_NOR_X_6 (ISP_RAWAWB_BASE + 0x002a0)
+#define ISP_RAWAWB_XY_DETC_NOR_Y_6 (ISP_RAWAWB_BASE + 0x002a4)
+#define ISP_RAWAWB_XY_DETC_BIG_X_6 (ISP_RAWAWB_BASE + 0x002a8)
+#define ISP_RAWAWB_XY_DETC_BIG_Y_6 (ISP_RAWAWB_BASE + 0x002ac)
+#define ISP_RAWAWB_XY_DETC_SMA_X_6 (ISP_RAWAWB_BASE + 0x002b0)
+#define ISP_RAWAWB_XY_DETC_SMA_Y_6 (ISP_RAWAWB_BASE + 0x002b4)
+#define ISP_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP_RAWAWB_BASE + 0x002b8)
+#define ISP_RAWAWB_MULTIWINDOW0_OFFS (ISP_RAWAWB_BASE + 0x002bc)
+#define ISP_RAWAWB_MULTIWINDOW0_SIZE (ISP_RAWAWB_BASE + 0x002c0)
+#define ISP_RAWAWB_MULTIWINDOW1_OFFS (ISP_RAWAWB_BASE + 0x002c4)
+#define ISP_RAWAWB_MULTIWINDOW1_SIZE (ISP_RAWAWB_BASE + 0x002c8)
+#define ISP_RAWAWB_MULTIWINDOW2_OFFS (ISP_RAWAWB_BASE + 0x002cc)
+#define ISP_RAWAWB_MULTIWINDOW2_SIZE (ISP_RAWAWB_BASE + 0x002d0)
+#define ISP_RAWAWB_MULTIWINDOW3_OFFS (ISP_RAWAWB_BASE + 0x002d4)
+#define ISP_RAWAWB_MULTIWINDOW3_SIZE (ISP_RAWAWB_BASE + 0x002d8)
+#define ISP_RAWAWB_MULTIWINDOW4_OFFS (ISP_RAWAWB_BASE + 0x002dc)
+#define ISP_RAWAWB_MULTIWINDOW4_SIZE (ISP_RAWAWB_BASE + 0x002e0)
+#define ISP_RAWAWB_MULTIWINDOW5_OFFS (ISP_RAWAWB_BASE + 0x002e4)
+#define ISP_RAWAWB_MULTIWINDOW5_SIZE (ISP_RAWAWB_BASE + 0x002e8)
+#define ISP_RAWAWB_MULTIWINDOW6_OFFS (ISP_RAWAWB_BASE + 0x002ec)
+#define ISP_RAWAWB_MULTIWINDOW6_SIZE (ISP_RAWAWB_BASE + 0x002f0)
+#define ISP_RAWAWB_MULTIWINDOW7_OFFS (ISP_RAWAWB_BASE + 0x002f4)
+#define ISP_RAWAWB_MULTIWINDOW7_SIZE (ISP_RAWAWB_BASE + 0x002f8)
+#define ISP_RAWAWB_EXC_WP_REGION0_XU (ISP_RAWAWB_BASE + 0x002fc)
+#define ISP_RAWAWB_EXC_WP_REGION0_YV (ISP_RAWAWB_BASE + 0x00300)
+#define ISP_RAWAWB_EXC_WP_REGION1_XU (ISP_RAWAWB_BASE + 0x00304)
+#define ISP_RAWAWB_EXC_WP_REGION1_YV (ISP_RAWAWB_BASE + 0x00308)
+#define ISP_RAWAWB_EXC_WP_REGION2_XU (ISP_RAWAWB_BASE + 0x0030c)
+#define ISP_RAWAWB_EXC_WP_REGION2_YV (ISP_RAWAWB_BASE + 0x00310)
+#define ISP_RAWAWB_EXC_WP_REGION3_XU (ISP_RAWAWB_BASE + 0x00314)
+#define ISP_RAWAWB_EXC_WP_REGION3_YV (ISP_RAWAWB_BASE + 0x00318)
+#define ISP_RAWAWB_EXC_WP_REGION4_XU (ISP_RAWAWB_BASE + 0x0031c)
+#define ISP_RAWAWB_EXC_WP_REGION4_YV (ISP_RAWAWB_BASE + 0x00320)
+#define ISP_RAWAWB_EXC_WP_REGION5_XU (ISP_RAWAWB_BASE + 0x00324)
+#define ISP_RAWAWB_EXC_WP_REGION5_YV (ISP_RAWAWB_BASE + 0x00328)
+#define ISP_RAWAWB_EXC_WP_REGION6_XU (ISP_RAWAWB_BASE + 0x0032c)
+#define ISP_RAWAWB_EXC_WP_REGION6_YV (ISP_RAWAWB_BASE + 0x00330)
+#define ISP_RAWAWB_SUM_R_NOR_0 (ISP_RAWAWB_BASE + 0x00340)
+#define ISP_RAWAWB_SUM_G_NOR_0 (ISP_RAWAWB_BASE + 0x00344)
+#define ISP_RAWAWB_SUM_B_NOR_0 (ISP_RAWAWB_BASE + 0x00348)
+#define ISP_RAWAWB_WP_NUM_NOR_0 (ISP_RAWAWB_BASE + 0x0034c)
+#define ISP_RAWAWB_SUM_R_BIG_0 (ISP_RAWAWB_BASE + 0x00350)
+#define ISP_RAWAWB_SUM_G_BIG_0 (ISP_RAWAWB_BASE + 0x00354)
+#define ISP_RAWAWB_SUM_B_BIG_0 (ISP_RAWAWB_BASE + 0x00358)
+#define ISP_RAWAWB_WP_NUM_BIG_0 (ISP_RAWAWB_BASE + 0x0035c)
+#define ISP_RAWAWB_SUM_R_SMA_0 (ISP_RAWAWB_BASE + 0x00360)
+#define ISP_RAWAWB_SUM_G_SMA_0 (ISP_RAWAWB_BASE + 0x00364)
+#define ISP_RAWAWB_SUM_B_SMA_0 (ISP_RAWAWB_BASE + 0x00368)
+#define ISP_RAWAWB_WP_NUM_SMA_0 (ISP_RAWAWB_BASE + 0x0036c)
+#define ISP_RAWAWB_SUM_R_NOR_1 (ISP_RAWAWB_BASE + 0x00370)
+#define ISP_RAWAWB_SUM_G_NOR_1 (ISP_RAWAWB_BASE + 0x00374)
+#define ISP_RAWAWB_SUM_B_NOR_1 (ISP_RAWAWB_BASE + 0x00378)
+#define ISP_RAWAWB_WP_NUM_NOR_1 (ISP_RAWAWB_BASE + 0x0037c)
+#define ISP_RAWAWB_SUM_R_BIG_1 (ISP_RAWAWB_BASE + 0x00380)
+#define ISP_RAWAWB_SUM_G_BIG_1 (ISP_RAWAWB_BASE + 0x00384)
+#define ISP_RAWAWB_SUM_B_BIG_1 (ISP_RAWAWB_BASE + 0x00388)
+#define ISP_RAWAWB_WP_NUM_BIG_1 (ISP_RAWAWB_BASE + 0x0038c)
+#define ISP_RAWAWB_SUM_R_SMA_1 (ISP_RAWAWB_BASE + 0x00390)
+#define ISP_RAWAWB_SUM_G_SMA_1 (ISP_RAWAWB_BASE + 0x00394)
+#define ISP_RAWAWB_SUM_B_SMA_1 (ISP_RAWAWB_BASE + 0x00398)
+#define ISP_RAWAWB_WP_NUM_SMA_1 (ISP_RAWAWB_BASE + 0x0039c)
+#define ISP_RAWAWB_SUM_R_NOR_2 (ISP_RAWAWB_BASE + 0x003a0)
+#define ISP_RAWAWB_SUM_G_NOR_2 (ISP_RAWAWB_BASE + 0x003a4)
+#define ISP_RAWAWB_SUM_B_NOR_2 (ISP_RAWAWB_BASE + 0x003a8)
+#define ISP_RAWAWB_WP_NUM_NOR_2 (ISP_RAWAWB_BASE + 0x003ac)
+#define ISP_RAWAWB_SUM_R_BIG_2 (ISP_RAWAWB_BASE + 0x003b0)
+#define ISP_RAWAWB_SUM_G_BIG_2 (ISP_RAWAWB_BASE + 0x003b4)
+#define ISP_RAWAWB_SUM_B_BIG_2 (ISP_RAWAWB_BASE + 0x003b8)
+#define ISP_RAWAWB_WP_NUM_BIG_2 (ISP_RAWAWB_BASE + 0x003bc)
+#define ISP_RAWAWB_SUM_R_SMA_2 (ISP_RAWAWB_BASE + 0x003c0)
+#define ISP_RAWAWB_SUM_G_SMA_2 (ISP_RAWAWB_BASE + 0x003c4)
+#define ISP_RAWAWB_SUM_B_SMA_2 (ISP_RAWAWB_BASE + 0x003c8)
+#define ISP_RAWAWB_WP_NUM_SMA_2 (ISP_RAWAWB_BASE + 0x003cc)
+#define ISP_RAWAWB_SUM_R_NOR_3 (ISP_RAWAWB_BASE + 0x003d0)
+#define ISP_RAWAWB_SUM_G_NOR_3 (ISP_RAWAWB_BASE + 0x003d4)
+#define ISP_RAWAWB_SUM_B_NOR_3 (ISP_RAWAWB_BASE + 0x003d8)
+#define ISP_RAWAWB_WP_NUM_NOR_3 (ISP_RAWAWB_BASE + 0x003dc)
+#define ISP_RAWAWB_SUM_R_BIG_3 (ISP_RAWAWB_BASE + 0x003e0)
+#define ISP_RAWAWB_SUM_G_BIG_3 (ISP_RAWAWB_BASE + 0x003e4)
+#define ISP_RAWAWB_SUM_B_BIG_3 (ISP_RAWAWB_BASE + 0x003e8)
+#define ISP_RAWAWB_WP_NUM_BIG_3 (ISP_RAWAWB_BASE + 0x003ec)
+#define ISP_RAWAWB_SUM_R_SMA_3 (ISP_RAWAWB_BASE + 0x003f0)
+#define ISP_RAWAWB_SUM_G_SMA_3 (ISP_RAWAWB_BASE + 0x003f4)
+#define ISP_RAWAWB_SUM_B_SMA_3 (ISP_RAWAWB_BASE + 0x003f8)
+#define ISP_RAWAWB_WP_NUM_SMA_3 (ISP_RAWAWB_BASE + 0x003fc)
+#define ISP_RAWAWB_SUM_R_NOR_4 (ISP_RAWAWB_BASE + 0x00400)
+#define ISP_RAWAWB_SUM_G_NOR_4 (ISP_RAWAWB_BASE + 0x00404)
+#define ISP_RAWAWB_SUM_B_NOR_4 (ISP_RAWAWB_BASE + 0x00408)
+#define ISP_RAWAWB_WP_NUM_NOR_4 (ISP_RAWAWB_BASE + 0x0040c)
+#define ISP_RAWAWB_SUM_R_BIG_4 (ISP_RAWAWB_BASE + 0x00410)
+#define ISP_RAWAWB_SUM_G_BIG_4 (ISP_RAWAWB_BASE + 0x00414)
+#define ISP_RAWAWB_SUM_B_BIG_4 (ISP_RAWAWB_BASE + 0x00418)
+#define ISP_RAWAWB_WP_NUM_BIG_4 (ISP_RAWAWB_BASE + 0x0041c)
+#define ISP_RAWAWB_SUM_R_SMA_4 (ISP_RAWAWB_BASE + 0x00420)
+#define ISP_RAWAWB_SUM_G_SMA_4 (ISP_RAWAWB_BASE + 0x00424)
+#define ISP_RAWAWB_SUM_B_SMA_4 (ISP_RAWAWB_BASE + 0x00428)
+#define ISP_RAWAWB_WP_NUM_SMA_4 (ISP_RAWAWB_BASE + 0x0042c)
+#define ISP_RAWAWB_SUM_R_NOR_5 (ISP_RAWAWB_BASE + 0x00430)
+#define ISP_RAWAWB_SUM_G_NOR_5 (ISP_RAWAWB_BASE + 0x00434)
+#define ISP_RAWAWB_SUM_B_NOR_5 (ISP_RAWAWB_BASE + 0x00438)
+#define ISP_RAWAWB_WP_NUM_NOR_5 (ISP_RAWAWB_BASE + 0x0043c)
+#define ISP_RAWAWB_SUM_R_BIG_5 (ISP_RAWAWB_BASE + 0x00440)
+#define ISP_RAWAWB_SUM_G_BIG_5 (ISP_RAWAWB_BASE + 0x00444)
+#define ISP_RAWAWB_SUM_B_BIG_5 (ISP_RAWAWB_BASE + 0x00448)
+#define ISP_RAWAWB_WP_NUM_BIG_5 (ISP_RAWAWB_BASE + 0x0044c)
+#define ISP_RAWAWB_SUM_R_SMA_5 (ISP_RAWAWB_BASE + 0x00450)
+#define ISP_RAWAWB_SUM_G_SMA_5 (ISP_RAWAWB_BASE + 0x00454)
+#define ISP_RAWAWB_SUM_B_SMA_5 (ISP_RAWAWB_BASE + 0x00458)
+#define ISP_RAWAWB_WP_NUM_SMA_5 (ISP_RAWAWB_BASE + 0x0045c)
+#define ISP_RAWAWB_SUM_R_NOR_6 (ISP_RAWAWB_BASE + 0x00460)
+#define ISP_RAWAWB_SUM_G_NOR_6 (ISP_RAWAWB_BASE + 0x00464)
+#define ISP_RAWAWB_SUM_B_NOR_6 (ISP_RAWAWB_BASE + 0x00468)
+#define ISP_RAWAWB_WP_NUM_NOR_6 (ISP_RAWAWB_BASE + 0x0046c)
+#define ISP_RAWAWB_SUM_R_BIG_6 (ISP_RAWAWB_BASE + 0x00470)
+#define ISP_RAWAWB_SUM_G_BIG_6 (ISP_RAWAWB_BASE + 0x00474)
+#define ISP_RAWAWB_SUM_B_BIG_6 (ISP_RAWAWB_BASE + 0x00478)
+#define ISP_RAWAWB_WP_NUM_BIG_6 (ISP_RAWAWB_BASE + 0x0047c)
+#define ISP_RAWAWB_SUM_R_SMA_6 (ISP_RAWAWB_BASE + 0x00480)
+#define ISP_RAWAWB_SUM_G_SMA_6 (ISP_RAWAWB_BASE + 0x00484)
+#define ISP_RAWAWB_SUM_B_SMA_6 (ISP_RAWAWB_BASE + 0x00488)
+#define ISP_RAWAWB_WP_NUM_SMA_6 (ISP_RAWAWB_BASE + 0x0048c)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x00490)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x00494)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x00498)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x0049c)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004a0)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004a4)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004a8)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004ac)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004b0)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004b4)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004b8)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004bc)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004c0)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004c4)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004c8)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004cc)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004d0)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004d4)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004d8)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004dc)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004e0)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004e4)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004e8)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004ec)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004f0)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004f4)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004f8)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004fc)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00500)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00504)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00508)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x0050c)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00510)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00514)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00518)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x0051c)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00520)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00524)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00528)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x0052c)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00530)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00534)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00538)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x0053c)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00540)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00544)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00548)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x0054c)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00550)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00554)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00558)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x0055c)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00560)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00564)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00568)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x0056c)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00570)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00574)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00578)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x0057c)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00580)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00584)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00588)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x0058c)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00590)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00594)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00598)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x0059c)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005a0)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005a4)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005a8)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005ac)
+#define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005b0)
+#define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005b4)
+#define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005b8)
+#define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005bc)
+#define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005c0)
+#define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005c4)
+#define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005c8)
+#define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005cc)
+#define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005d0)
+#define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005d4)
+#define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005d8)
+#define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005dc)
+#define ISP_RAWAWB_SUM_R_EXC_0 (ISP_RAWAWB_BASE + 0x005e0)
+#define ISP_RAWAWB_SUM_G_EXC_0 (ISP_RAWAWB_BASE + 0x005e4)
+#define ISP_RAWAWB_SUM_B_EXC_0 (ISP_RAWAWB_BASE + 0x005e8)
+#define ISP_RAWAWB_WP_NM_EXC_0 (ISP_RAWAWB_BASE + 0x005ec)
+#define ISP_RAWAWB_SUM_R_EXC_1 (ISP_RAWAWB_BASE + 0x005f0)
+#define ISP_RAWAWB_SUM_G_EXC_1 (ISP_RAWAWB_BASE + 0x005f4)
+#define ISP_RAWAWB_SUM_B_EXC_1 (ISP_RAWAWB_BASE + 0x005f8)
+#define ISP_RAWAWB_WP_NM_EXC_1 (ISP_RAWAWB_BASE + 0x005fc)
+#define ISP_RAWAWB_SUM_R_EXC_2 (ISP_RAWAWB_BASE + 0x00600)
+#define ISP_RAWAWB_SUM_G_EXC_2 (ISP_RAWAWB_BASE + 0x00604)
+#define ISP_RAWAWB_SUM_B_EXC_2 (ISP_RAWAWB_BASE + 0x00608)
+#define ISP_RAWAWB_WP_NM_EXC_2 (ISP_RAWAWB_BASE + 0x0060c)
+#define ISP_RAWAWB_SUM_R_EXC_3 (ISP_RAWAWB_BASE + 0x00610)
+#define ISP_RAWAWB_SUM_G_EXC_3 (ISP_RAWAWB_BASE + 0x00614)
+#define ISP_RAWAWB_SUM_B_EXC_3 (ISP_RAWAWB_BASE + 0x00618)
+#define ISP_RAWAWB_WP_NM_EXC_3 (ISP_RAWAWB_BASE + 0x0061c)
+#define ISP_RAWAWB_SUM_R_EXC_4 (ISP_RAWAWB_BASE + 0x00620)
+#define ISP_RAWAWB_SUM_G_EXC_4 (ISP_RAWAWB_BASE + 0x00624)
+#define ISP_RAWAWB_SUM_B_EXC_4 (ISP_RAWAWB_BASE + 0x00628)
+#define ISP_RAWAWB_WP_NM_EXC_4 (ISP_RAWAWB_BASE + 0x0062c)
+#define ISP_RAWAWB_SUM_R_EXC_5 (ISP_RAWAWB_BASE + 0x00630)
+#define ISP_RAWAWB_SUM_G_EXC_5 (ISP_RAWAWB_BASE + 0x00634)
+#define ISP_RAWAWB_SUM_B_EXC_5 (ISP_RAWAWB_BASE + 0x00638)
+#define ISP_RAWAWB_WP_NM_EXC_5 (ISP_RAWAWB_BASE + 0x0063c)
+#define ISP_RAWAWB_SUM_R_EXC_6 (ISP_RAWAWB_BASE + 0x00640)
+#define ISP_RAWAWB_SUM_G_EXC_6 (ISP_RAWAWB_BASE + 0x00644)
+#define ISP_RAWAWB_SUM_B_EXC_6 (ISP_RAWAWB_BASE + 0x00648)
+#define ISP_RAWAWB_WP_NM_EXC_6 (ISP_RAWAWB_BASE + 0x0064c)
+#define ISP_RAWAWB_RAM_CTRL (ISP_RAWAWB_BASE + 0x00650)
+#define ISP_RAWAWB_RAM_DATA (ISP_RAWAWB_BASE + 0x00660)
+
+#define ISP21_RAWAWB_BASE 0x00005000
+#define ISP21_RAWAWB_CTRL (ISP21_RAWAWB_BASE + 0x0000)
+#define ISP21_RAWAWB_BLK_CTRL (ISP21_RAWAWB_BASE + 0x0004)
+#define ISP21_RAWAWB_WIN_OFFS (ISP21_RAWAWB_BASE + 0x0008)
+#define ISP21_RAWAWB_WIN_SIZE (ISP21_RAWAWB_BASE + 0x000c)
+#define ISP21_RAWAWB_LIMIT_RG_MAX (ISP21_RAWAWB_BASE + 0x0010)
+#define ISP21_RAWAWB_LIMIT_BY_MAX (ISP21_RAWAWB_BASE + 0x0014)
+#define ISP21_RAWAWB_LIMIT_RG_MIN (ISP21_RAWAWB_BASE + 0x0018)
+#define ISP21_RAWAWB_LIMIT_BY_MIN (ISP21_RAWAWB_BASE + 0x001c)
+#define ISP21_RAWAWB_WEIGHT_CURVE_CTRL (ISP21_RAWAWB_BASE + 0x0020)
+#define ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR03 (ISP21_RAWAWB_BASE + 0x0024)
+#define ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR47 (ISP21_RAWAWB_BASE + 0x0028)
+#define ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR8 (ISP21_RAWAWB_BASE + 0x002c)
+#define ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR03 (ISP21_RAWAWB_BASE + 0x0030)
+#define ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR47 (ISP21_RAWAWB_BASE + 0x0034)
+#define ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR8 (ISP21_RAWAWB_BASE + 0x0038)
+#define ISP21_RAWAWB_PRE_WBGAIN_INV (ISP21_RAWAWB_BASE + 0x003c)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_0 (ISP21_RAWAWB_BASE + 0x0040)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_0 (ISP21_RAWAWB_BASE + 0x0044)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_0 (ISP21_RAWAWB_BASE + 0x0048)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_0 (ISP21_RAWAWB_BASE + 0x004c)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_0 (ISP21_RAWAWB_BASE + 0x0050)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE12_0 (ISP21_RAWAWB_BASE + 0x0054)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_0 (ISP21_RAWAWB_BASE + 0x0058)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_0 (ISP21_RAWAWB_BASE + 0x005c)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_1 (ISP21_RAWAWB_BASE + 0x0060)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_1 (ISP21_RAWAWB_BASE + 0x0064)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_1 (ISP21_RAWAWB_BASE + 0x0068)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_1 (ISP21_RAWAWB_BASE + 0x006c)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_1 (ISP21_RAWAWB_BASE + 0x0070)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE12_1 (ISP21_RAWAWB_BASE + 0x0074)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_1 (ISP21_RAWAWB_BASE + 0x0078)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_1 (ISP21_RAWAWB_BASE + 0x007c)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_2 (ISP21_RAWAWB_BASE + 0x0080)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_2 (ISP21_RAWAWB_BASE + 0x0084)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_2 (ISP21_RAWAWB_BASE + 0x0088)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_2 (ISP21_RAWAWB_BASE + 0x008c)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_2 (ISP21_RAWAWB_BASE + 0x0090)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE12_2 (ISP21_RAWAWB_BASE + 0x0094)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_2 (ISP21_RAWAWB_BASE + 0x0098)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_2 (ISP21_RAWAWB_BASE + 0x009c)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_3 (ISP21_RAWAWB_BASE + 0x00a0)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_3 (ISP21_RAWAWB_BASE + 0x00a4)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_3 (ISP21_RAWAWB_BASE + 0x00a8)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_3 (ISP21_RAWAWB_BASE + 0x00ac)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_3 (ISP21_RAWAWB_BASE + 0x00b0)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE12_3 (ISP21_RAWAWB_BASE + 0x00b4)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_3 (ISP21_RAWAWB_BASE + 0x00b8)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_3 (ISP21_RAWAWB_BASE + 0x00bc)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_4 (ISP21_RAWAWB_BASE + 0x00c0)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_4 (ISP21_RAWAWB_BASE + 0x00c4)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_4 (ISP21_RAWAWB_BASE + 0x00c8)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_4 (ISP21_RAWAWB_BASE + 0x00cc)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_4 (ISP21_RAWAWB_BASE + 0x00d0)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE12_4 (ISP21_RAWAWB_BASE + 0x00d4)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_4 (ISP21_RAWAWB_BASE + 0x00d8)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_4 (ISP21_RAWAWB_BASE + 0x00dc)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_5 (ISP21_RAWAWB_BASE + 0x00e0)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_5 (ISP21_RAWAWB_BASE + 0x00e4)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_5 (ISP21_RAWAWB_BASE + 0x00e8)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_5 (ISP21_RAWAWB_BASE + 0x00ec)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_5 (ISP21_RAWAWB_BASE + 0x00f0)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE10_5 (ISP21_RAWAWB_BASE + 0x00f4)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_5 (ISP21_RAWAWB_BASE + 0x00f8)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_5 (ISP21_RAWAWB_BASE + 0x00fc)
+#define ISP21_RAWAWB_UV_DETC_VERTEX0_6 (ISP21_RAWAWB_BASE + 0x0100)
+#define ISP21_RAWAWB_UV_DETC_VERTEX1_6 (ISP21_RAWAWB_BASE + 0x0104)
+#define ISP21_RAWAWB_UV_DETC_VERTEX2_6 (ISP21_RAWAWB_BASE + 0x0108)
+#define ISP21_RAWAWB_UV_DETC_VERTEX3_6 (ISP21_RAWAWB_BASE + 0x010c)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE01_6 (ISP21_RAWAWB_BASE + 0x0110)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE10_6 (ISP21_RAWAWB_BASE + 0x0114)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE23_6 (ISP21_RAWAWB_BASE + 0x0118)
+#define ISP21_RAWAWB_UV_DETC_ISLOPE30_6 (ISP21_RAWAWB_BASE + 0x011c)
+#define ISP21_RAWAWB_YUV_RGB2ROTY_0 (ISP21_RAWAWB_BASE + 0x0120)
+#define ISP21_RAWAWB_YUV_RGB2ROTY_1 (ISP21_RAWAWB_BASE + 0x0124)
+#define ISP21_RAWAWB_YUV_RGB2ROTU_0 (ISP21_RAWAWB_BASE + 0x0128)
+#define ISP21_RAWAWB_YUV_RGB2ROTU_1 (ISP21_RAWAWB_BASE + 0x012c)
+#define ISP21_RAWAWB_YUV_RGB2ROTV_0 (ISP21_RAWAWB_BASE + 0x0130)
+#define ISP21_RAWAWB_YUV_RGB2ROTV_1 (ISP21_RAWAWB_BASE + 0x0134)
+#define ISP21_RAWAWB_YUV_X_COOR_Y_0 (ISP21_RAWAWB_BASE + 0x0140)
+#define ISP21_RAWAWB_YUV_X_COOR_U_0 (ISP21_RAWAWB_BASE + 0x0144)
+#define ISP21_RAWAWB_YUV_X_COOR_V_0 (ISP21_RAWAWB_BASE + 0x0148)
+#define ISP21_RAWAWB_YUV_X1X2_DIS_0 (ISP21_RAWAWB_BASE + 0x014c)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_0 (ISP21_RAWAWB_BASE + 0x0150)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_0 (ISP21_RAWAWB_BASE + 0x0154)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_0 (ISP21_RAWAWB_BASE + 0x0158)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_0 (ISP21_RAWAWB_BASE + 0x015c)
+#define ISP21_RAWAWB_YUV_X_COOR_Y_1 (ISP21_RAWAWB_BASE + 0x0160)
+#define ISP21_RAWAWB_YUV_X_COOR_U_1 (ISP21_RAWAWB_BASE + 0x0164)
+#define ISP21_RAWAWB_YUV_X_COOR_V_1 (ISP21_RAWAWB_BASE + 0x0168)
+#define ISP21_RAWAWB_YUV_X1X2_DIS_1 (ISP21_RAWAWB_BASE + 0x016c)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_1 (ISP21_RAWAWB_BASE + 0x0170)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_1 (ISP21_RAWAWB_BASE + 0x0174)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_1 (ISP21_RAWAWB_BASE + 0x0178)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_1 (ISP21_RAWAWB_BASE + 0x017c)
+#define ISP21_RAWAWB_YUV_X_COOR_Y_2 (ISP21_RAWAWB_BASE + 0x0180)
+#define ISP21_RAWAWB_YUV_X_COOR_U_2 (ISP21_RAWAWB_BASE + 0x0184)
+#define ISP21_RAWAWB_YUV_X_COOR_V_2 (ISP21_RAWAWB_BASE + 0x0188)
+#define ISP21_RAWAWB_YUV_X1X2_DIS_2 (ISP21_RAWAWB_BASE + 0x018c)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_2 (ISP21_RAWAWB_BASE + 0x0190)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_2 (ISP21_RAWAWB_BASE + 0x0194)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_2 (ISP21_RAWAWB_BASE + 0x0198)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_2 (ISP21_RAWAWB_BASE + 0x019c)
+#define ISP21_RAWAWB_YUV_X_COOR_Y_3 (ISP21_RAWAWB_BASE + 0x01a0)
+#define ISP21_RAWAWB_YUV_X_COOR_U_3 (ISP21_RAWAWB_BASE + 0x01a4)
+#define ISP21_RAWAWB_YUV_X_COOR_V_3 (ISP21_RAWAWB_BASE + 0x01a8)
+#define ISP21_RAWAWB_YUV_X1X2_DIS_3 (ISP21_RAWAWB_BASE + 0x01ac)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_3 (ISP21_RAWAWB_BASE + 0x01b0)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_3 (ISP21_RAWAWB_BASE + 0x01b4)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_3 (ISP21_RAWAWB_BASE + 0x01b8)
+#define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_3 (ISP21_RAWAWB_BASE + 0x01bc)
+#define ISP21_RAWAWB_RGB2XY_WT01 (ISP21_RAWAWB_BASE + 0x01fc)
+#define ISP21_RAWAWB_RGB2XY_WT2 (ISP21_RAWAWB_BASE + 0x0200)
+#define ISP21_RAWAWB_RGB2XY_MAT0_XY (ISP21_RAWAWB_BASE + 0x0204)
+#define ISP21_RAWAWB_RGB2XY_MAT1_XY (ISP21_RAWAWB_BASE + 0x0208)
+#define ISP21_RAWAWB_RGB2XY_MAT2_XY (ISP21_RAWAWB_BASE + 0x020c)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_0 (ISP21_RAWAWB_BASE + 0x0210)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_0 (ISP21_RAWAWB_BASE + 0x0214)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_0 (ISP21_RAWAWB_BASE + 0x0218)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_0 (ISP21_RAWAWB_BASE + 0x021c)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_1 (ISP21_RAWAWB_BASE + 0x0228)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_1 (ISP21_RAWAWB_BASE + 0x022c)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_1 (ISP21_RAWAWB_BASE + 0x0230)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_1 (ISP21_RAWAWB_BASE + 0x0234)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_2 (ISP21_RAWAWB_BASE + 0x0240)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_2 (ISP21_RAWAWB_BASE + 0x0244)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_2 (ISP21_RAWAWB_BASE + 0x0248)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_2 (ISP21_RAWAWB_BASE + 0x024c)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_3 (ISP21_RAWAWB_BASE + 0x0258)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_3 (ISP21_RAWAWB_BASE + 0x025c)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_3 (ISP21_RAWAWB_BASE + 0x0260)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_3 (ISP21_RAWAWB_BASE + 0x0264)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_4 (ISP21_RAWAWB_BASE + 0x0270)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_4 (ISP21_RAWAWB_BASE + 0x0274)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_4 (ISP21_RAWAWB_BASE + 0x0278)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_4 (ISP21_RAWAWB_BASE + 0x027c)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_5 (ISP21_RAWAWB_BASE + 0x0288)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_5 (ISP21_RAWAWB_BASE + 0x028c)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_5 (ISP21_RAWAWB_BASE + 0x0290)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_5 (ISP21_RAWAWB_BASE + 0x0294)
+#define ISP21_RAWAWB_XY_DETC_NOR_X_6 (ISP21_RAWAWB_BASE + 0x02a0)
+#define ISP21_RAWAWB_XY_DETC_NOR_Y_6 (ISP21_RAWAWB_BASE + 0x02a4)
+#define ISP21_RAWAWB_XY_DETC_BIG_X_6 (ISP21_RAWAWB_BASE + 0x02a8)
+#define ISP21_RAWAWB_XY_DETC_BIG_Y_6 (ISP21_RAWAWB_BASE + 0x02ac)
+#define ISP21_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP21_RAWAWB_BASE + 0x02b8)
+#define ISP21_RAWAWB_EXC_WP_REGION0_XU (ISP21_RAWAWB_BASE + 0x02fc)
+#define ISP21_RAWAWB_EXC_WP_REGION0_YV (ISP21_RAWAWB_BASE + 0x0300)
+#define ISP21_RAWAWB_EXC_WP_REGION1_XU (ISP21_RAWAWB_BASE + 0x0304)
+#define ISP21_RAWAWB_EXC_WP_REGION1_YV (ISP21_RAWAWB_BASE + 0x0308)
+#define ISP21_RAWAWB_EXC_WP_REGION2_XU (ISP21_RAWAWB_BASE + 0x030c)
+#define ISP21_RAWAWB_EXC_WP_REGION2_YV (ISP21_RAWAWB_BASE + 0x0310)
+#define ISP21_RAWAWB_EXC_WP_REGION3_XU (ISP21_RAWAWB_BASE + 0x0314)
+#define ISP21_RAWAWB_EXC_WP_REGION3_YV (ISP21_RAWAWB_BASE + 0x0318)
+#define ISP21_RAWAWB_EXC_WP_REGION4_XU (ISP21_RAWAWB_BASE + 0x031c)
+#define ISP21_RAWAWB_EXC_WP_REGION4_YV (ISP21_RAWAWB_BASE + 0x0320)
+#define ISP21_RAWAWB_EXC_WP_REGION5_XU (ISP21_RAWAWB_BASE + 0x0324)
+#define ISP21_RAWAWB_EXC_WP_REGION5_YV (ISP21_RAWAWB_BASE + 0x0328)
+#define ISP21_RAWAWB_EXC_WP_REGION6_XU (ISP21_RAWAWB_BASE + 0x032c)
+#define ISP21_RAWAWB_EXC_WP_REGION6_YV (ISP21_RAWAWB_BASE + 0x0330)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_0 (ISP21_RAWAWB_BASE + 0x0340)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_0 (ISP21_RAWAWB_BASE + 0x0348)
+#define ISP21_RAWAWB_WP_NUM_NOR_0 (ISP21_RAWAWB_BASE + 0x034c)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_0 (ISP21_RAWAWB_BASE + 0x0350)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_0 (ISP21_RAWAWB_BASE + 0x0358)
+#define ISP21_RAWAWB_WP_NUM_BIG_0 (ISP21_RAWAWB_BASE + 0x035c)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_1 (ISP21_RAWAWB_BASE + 0x0370)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_1 (ISP21_RAWAWB_BASE + 0x0378)
+#define ISP21_RAWAWB_WP_NUM_NOR_1 (ISP21_RAWAWB_BASE + 0x037c)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_1 (ISP21_RAWAWB_BASE + 0x0380)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_1 (ISP21_RAWAWB_BASE + 0x0388)
+#define ISP21_RAWAWB_WP_NUM_BIG_1 (ISP21_RAWAWB_BASE + 0x038c)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_2 (ISP21_RAWAWB_BASE + 0x03a0)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_2 (ISP21_RAWAWB_BASE + 0x03a8)
+#define ISP21_RAWAWB_WP_NUM_NOR_2 (ISP21_RAWAWB_BASE + 0x03ac)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_2 (ISP21_RAWAWB_BASE + 0x03b0)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_2 (ISP21_RAWAWB_BASE + 0x03b8)
+#define ISP21_RAWAWB_WP_NUM_BIG_2 (ISP21_RAWAWB_BASE + 0x03bc)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_3 (ISP21_RAWAWB_BASE + 0x03d0)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_3 (ISP21_RAWAWB_BASE + 0x03d8)
+#define ISP21_RAWAWB_WP_NUM_NOR_3 (ISP21_RAWAWB_BASE + 0x03dc)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_3 (ISP21_RAWAWB_BASE + 0x03e0)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_3 (ISP21_RAWAWB_BASE + 0x03e8)
+#define ISP21_RAWAWB_WP_NUM_BIG_3 (ISP21_RAWAWB_BASE + 0x03ec)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_4 (ISP21_RAWAWB_BASE + 0x0400)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_4 (ISP21_RAWAWB_BASE + 0x0408)
+#define ISP21_RAWAWB_WP_NUM_NOR_4 (ISP21_RAWAWB_BASE + 0x040c)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_4 (ISP21_RAWAWB_BASE + 0x0410)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_4 (ISP21_RAWAWB_BASE + 0x0418)
+#define ISP21_RAWAWB_WP_NUM_BIG_4 (ISP21_RAWAWB_BASE + 0x041c)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_5 (ISP21_RAWAWB_BASE + 0x0430)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_5 (ISP21_RAWAWB_BASE + 0x0438)
+#define ISP21_RAWAWB_WP_NUM_NOR_5 (ISP21_RAWAWB_BASE + 0x043c)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_5 (ISP21_RAWAWB_BASE + 0x0440)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_5 (ISP21_RAWAWB_BASE + 0x0448)
+#define ISP21_RAWAWB_WP_NUM_BIG_5 (ISP21_RAWAWB_BASE + 0x044c)
+#define ISP21_RAWAWB_SUM_RGAIN_NOR_6 (ISP21_RAWAWB_BASE + 0x0460)
+#define ISP21_RAWAWB_SUM_BGAIN_NOR_6 (ISP21_RAWAWB_BASE + 0x0468)
+#define ISP21_RAWAWB_WP_NUM_NOR_6 (ISP21_RAWAWB_BASE + 0x046c)
+#define ISP21_RAWAWB_SUM_RGAIN_BIG_6 (ISP21_RAWAWB_BASE + 0x0470)
+#define ISP21_RAWAWB_SUM_BGAIN_BIG_6 (ISP21_RAWAWB_BASE + 0x0478)
+#define ISP21_RAWAWB_WP_NUM_BIG_6 (ISP21_RAWAWB_BASE + 0x047c)
+#define ISP21_RAWAWB_Y_HIST01 (ISP21_RAWAWB_BASE + 0x0620)
+#define ISP21_RAWAWB_Y_HIST23 (ISP21_RAWAWB_BASE + 0x0624)
+#define ISP21_RAWAWB_Y_HIST45 (ISP21_RAWAWB_BASE + 0x0628)
+#define ISP21_RAWAWB_Y_HIST67 (ISP21_RAWAWB_BASE + 0x062c)
+#define ISP21_RAWAWB_RAM_CTRL (ISP21_RAWAWB_BASE + 0x0650)
+#define ISP21_RAWAWB_WRAM_CTRL (ISP21_RAWAWB_BASE + 0x0654)
+#define ISP21_RAWAWB_WRAM_DATA_BASE (ISP21_RAWAWB_BASE + 0x0660)
+#define ISP21_RAWAWB_RAM_DATA_BASE (ISP21_RAWAWB_BASE + 0x0700)
+
+
+/* VI_ISP_EN */
+#define VI_CCL_EN BIT(0)
+#define VI_ISP_EN_SEL BIT(1)
+#define VI_ISP_BLS_EN BIT(5)
+#define VI_ISP_GAMMA_IN_EN BIT(6)
+#define VI_ISP_HDRMGE_EN BIT(7)
+#define VI_ISP_RAWNR_EN BIT(9)
+#define VI_ISP_LSC_EN BIT(10)
+#define VI_ISP_HDRTMO_EN BIT(11)
+#define VI_ISP_GIC_EN BTI(12)
+#define VI_ISP_DEBAYER_EN BIT(13)
+#define VI_ISP_CCM_EN BIT(14)
+#define VI_ISP_GAMMA12_EN BIT(15)
+#define VI_ISP_RKWDR_EN BIT(16)
+#define VI_ISP_DHAZ_EN BIT(17)
+#define VI_ISP_3DLUT_EN BIT(18)
+#define VI_ISP_AWB_EN BIT(20)
+#define VI_ISP_CP_EN BIT(21)
+#define VI_ISP_RSZ_EN BIT(22)
+#define VI_ISP_EFF_EN BIT(24)
+#define VI_ISP_IMP_EN BIT(25)
+
+/* VI_ISP_PATH */
+#define SW_3A_RAWAE_SEL(a) (((a) & 0x3) << 16)
+#define SW_3A_RAWAF_SEL(a) (((a) & 0x3) << 18)
+#define SW_3A_RAWAWB_SEL(a) (((a) & 0x3) << 20)
+#define SW_3A_RAWAE_SWAP(a) (((a) & 0x3) << 22)
+
+/* VI_ISP_CLK_CTRL */
+#define CLK_CTRL_ISP_RAW BIT(0)
+#define CLK_CTRL_ISP_RGB BIT(1)
+#define CLK_CTRL_ISP_YUV BIT(2)
+#define CLK_CTRL_ISP_3A BIT(3)
+#define CLK_CTRL_MIPI_RAM BIT(4)
+#define CLK_CTRL_ISP_FIFO_RAM BIT(5)
+#define CLK_CTRL_ISP_DEM_RAM BIT(6)
+#define CLK_CTRL_ISP_DPCC_RAM BIT(7)
+#define CLK_CTRL_ISP_IE_RAM BIT(8)
+#define CLK_CTRL_RSZ_RAM BIT(9)
+#define CLK_CTRL_JPEG_RAM BIT(10)
+#define CLK_CTRL_ACLK_ISP BIT(11)
+#define CLK_CTRL_LDC_RAM BIT(12)
+#define CLK_CTRL_MI_LDC BIT(13)
+#define CLK_CTRL_MI_MP BIT(14)
+#define CLK_CTRL_MI_JPEG BIT(15)
+#define CLK_CTRL_MI_DP BIT(16)
+#define CLK_CTRL_MI_Y12 BIT(17)
+#define CLK_CTRL_MI_SP BIT(18)
+#define CLK_CTRL_MI_RAW0 BIT(19)
+#define CLK_CTRL_MI_RAW1 BIT(20)
+#define CLK_CTRL_MI_READ BIT(21)
+#define CLK_CTRL_MI_RAWRD BIT(22)
+#define CLK_CTRL_CP BIT(23)
+#define CLK_CTRL_IE BIT(24)
+#define CLK_CTRL_SI BIT(25)
+#define CLK_CTRL_RSZM BIT(26)
+#define CLK_CTRL_DPMUX BIT(27)
+#define CLK_CTRL_JPEG BIT(28)
+#define CLK_CTRL_RSZS BIT(29)
+#define CLK_CTRL_MIPI BIT(30)
+#define CLK_CTRL_MARVINMI BIT(31)
+
+/* VI_ICCL */
+#define ICCL_ISP_CLK BIT(0)
+#define ICCL_CP_CLK BIT(1)
+#define ICCL_MRSZ_CLK BIT(3)
+#define ICCL_SRSZ_CLK BIT(4)
+#define ICCL_JPEG_CLK BIT(5)
+#define ICCL_MI_CLK BIT(6)
+#define ICCL_IE_CLK BIT(8)
+#define ICCL_SIMP_CLK BIT(9)
+#define ICCL_SMIA_CLK BIT(10)
+#define ICCL_MIPI_CLK BIT(11)
+#define ICCL_MPFBC_CLK BIT(14)
+
+/* VI_IRCL */
+#define IRCL_ISP_SW_RST BIT(0)
+#define IRCL_CP_SW_RST BIT(1)
+#define IRCL_YCS_SW_RST BIT(2)
+#define IRCL_MRSZ_SW_RST BIT(3)
+#define IRCL_SRSZ_SW_RST BIT(4)
+#define IRCL_JPEG_SW_RST BIT(5)
+#define IRCL_MI_SW_RST BIT(6)
+#define IRCL_MARVIN_RST BIT(7)
+#define IRCL_IE_SW_RST BIT(8)
+#define IRCL_SI_SW_RST BIT(9)
+#define IRCL_MIPI_SW_RST BIT(11)
+#define IRCL_3A_SW_RST BIT(13)
+
+/* VI_DPCL */
+#define VI_DPCL_IF_SEL_LVDS BIT(8)
+
+/* SWS_CFG */
+#define SW_SWS_EN BIT(0)
+#define SW_ISP2PP_PIPE_EN BIT(1)
+#define SW_MPIP_DROP_FRM_DIS BIT(2)
+#define SW_SENSOR_ID(a) (((a) & 0x3) << 4)
+#define SW_SWS_TMO_DDR_RD BIT(8)
+#define SW_SWS_WDR_DDR_RD BIT(9)
+#define SW_SWS_DHAZ_DDR_RD BIT(10)
+#define SW_SWS_ISP_DDRLOAD_DIS BIT(11)
+#define SW_SWS_DMA_START_MODE(a) (((a) & 0x3) << 12)
+#define SW_ISP2PP_DIFX16(a) (((a) & 0xff) << 16)
+#define SW_3A_DDR_WRITE_EN BIT(24)
+#define SW_ISP2PP_HOLD BIT(31)
+
+/* LVDS_CTRL */
+#define SW_LVDS_EN BIT(0)
+#define SW_LVDS_MODE BIT(1)
+#define SW_LVDS_WIDTH(a) (((a) & 0x3) << 2)
+#define SW_LVDS_LANE_EN(a) (((a) & 0xf) << 4)
+#define SW_LVDS_MAIN_LANE(a) (((a) & 0x3) << 8)
+#define SW_LVDS_START_X(a) (((a) & 0x7ff) << 10)
+#define SW_LVDS_START_Y(a) (((a) & 0x7ff) << 21)
+
+#define SW_LVDS_SAV(a) ((a) & 0xfff)
+#define SW_LVDS_EAV(a) (((a) & 0xfff) << 16)
+
+/* ISP CTRL */
+#define NOC_HURRY_PRIORITY(a) (((a) & 0x3) << 30)
+#define NOC_HURRY_W_MODE(a) (((a) & 0x7) << 21)
+#define NOC_HURRY_R_MODE(a) (((a) & 0x7) << 18)
+
+/* ISP CTRL1 */
+#define ISP2X_SYS_YNR_FST BIT(23)
+#define ISP2X_SYS_ADRC_FST BIT(24)
+#define ISP2X_SYS_DHAZ_FST BIT(25)
+#define ISP2X_SYS_CNR_FST BIT(26)
+#define ISP2X_SYS_BAY3D_FST BIT(27)
+#define ISP2X_SYS_BIGMODE_FORCEEN BIT(28)
+#define ISP2X_SYS_BIGMODE_MANUAL BIT(29)
+
+/* isp interrupt */
+#define ISP2X_OFF BIT(0)
+#define ISP2X_FRAME BIT(1)
+#define ISP2X_DATA_LOSS BIT(2)
+#define ISP2X_PIC_SIZE_ERROR BIT(3)
+#define ISP2X_SIAWB_DONE BIT(4)
+#define ISP2X_FRAME_IN BIT(5)
+#define ISP2X_V_START BIT(6)
+#define ISP2X_H_START BIT(7)
+#define ISP2X_FLASH_ON BIT(8)
+#define ISP2X_FLASH_OFF BIT(9)
+#define ISP2X_SHUTTER_ON BIT(10)
+#define ISP2X_SHUTTER_OFF BIT(11)
+#define ISP2X_AFM_SUM_OF BIT(12)
+#define ISP2X_AFM_LUM_OF BIT(13)
+#define ISP2X_SIAF_FIN BIT(14)
+#define ISP2X_SIHST_RDY BIT(15)
+#define ISP2X_LSC_LUT_ERR BIT(16)
+#define ISP2X_FLASH_CAP BIT(17)
+#define ISP2X_YUVAE_END BIT(18)
+#define ISP2X_VSM_END BIT(19)
+#define ISP2X_HDR_DONE BIT(20)
+#define ISP2X_DHAZ_DONE BIT(21)
+#define ISP2X_GAIN_DONE BIT(22)
+
+/* isp3a interrupt */
+#define ISP2X_3A_RAWAE_BIG BIT(0)
+#define ISP2X_3A_RAWAE_CH0 BIT(1)
+#define ISP2X_3A_RAWAE_CH1 BIT(2)
+#define ISP2X_3A_RAWAE_CH2 BIT(3)
+#define ISP2X_3A_RAWHIST_BIG BIT(4)
+#define ISP2X_3A_RAWHIST_CH0 BIT(5)
+#define ISP2X_3A_RAWHIST_CH1 BIT(6)
+#define ISP2X_3A_RAWHIST_CH2 BIT(7)
+#define ISP2X_3A_RAWAF_SUM BIT(8)
+#define ISP2X_3A_RAWAF_LUM BIT(9)
+#define ISP2X_3A_RAWAF BIT(10)
+#define ISP2X_3A_RAWAWB BIT(11)
+#define ISP2X_3A_DDR_DONE BIT(12)
+
+/* MI_WR_CTRL */
+#define MI_LUM_BURST_MASK GENMASK(17, 16)
+#define MI_MIPI_LUM_BURST2 BIT(16)
+#define MI_MIPI_LUM_BURST4 BIT(17)
+#define MI_MIPI_LUM_BURST8 (3 << 16)
+#define MI_MIPI_LUM_BURST16 (0 << 16)
+
+/* mi interrupt */
+#define MI_MP_FRAME BIT(0)
+#define MI_SP_FRAME BIT(1)
+#define MI_MBLK_LINE BIT(2)
+#define MI_FILL_MP_Y BIT(3)
+#define MI_WRAP_MP_Y BIT(4)
+#define MI_WRAP_MP_CB BIT(5)
+#define MI_WRAP_MP_CR BIT(6)
+#define MI_WRAP_SP_Y BIT(7)
+#define MI_WRAP_SP_CB BIT(8)
+#define MI_WARP_SP_CR BIT(9)
+#define MI_FILL_MP_Y2 BIT(10)
+#define MI_DMA_READY BIT(11)
+#define MI_Y12Y_FRAME BIT(12)
+#define MI_Y12C_FRAME BIT(13)
+#define MI_ALL_FRAME BIT(14)
+#define MI_RAW0_WR_FRAME BIT(16)
+#define MI_RAW1_WR_FRAME BIT(17)
+#define MI_RAW2_WR_FRAME BIT(18)
+#define MI_RAW3_WR_FRAME BIT(19)
+#define MI_DBR_WR_FRAME BIT(20)
+#define MI_GAIN_WR_FRAME BIT(21)
+#define MI_MPFBC_FRAME BIT(31)
+
+/* MI_CTRL2 */
+#define SW_BAY3D_FORCEUPD BIT(22)
+#define SW_BAY3D_WR_AUTOUPD BIT(16)
+#define SW_GAIN_WR_AUTOUPD BIT(13)
+#define SW_GAIN_WR_PINGPONG BIT(12)
+#define SW_DBR_WR_AUTOUPD BIT(10)
+#define SW_MIMUX_BYTE_SWAP BIT(9)
+#define SW_MIMUX_EN BIT(8)
+#define SW_RAW3_WR_AUTOUPD BIT(3)
+#define SW_RAW2_WR_AUTOUPD BIT(2)
+#define SW_RAW1_WR_AUTOUPD BIT(1)
+#define SW_RAW0_WR_AUTOUPD BIT(0)
+
+/* MI_RD_CTRL2 */
+#define BAY3D_RW_ONEADDR_EN BIT(4)
+
+/* MPFBC */
+#define SW_MPFBC_EN BIT(0)
+#define SW_MPFBC_MAINISP_MODE BIT(3)
+#define SW_MPFBC_YUV_MODE(a) (((a) & 0x3) << 1)
+#define SW_MPFBC_PINGPONG_EN BIT(4)
+
+/* CSI2RX */
+#define SW_CSI2RX_EN BIT(0)
+#define SW_HDR_ESP_MODE(a) (((a) & 0x3) << 2)
+#define SW_IBUF_OP_MODE(a) (((a) & 0x0F) << 8)
+#define SW_DMA_2FRM_MODE(a) (((a) & 0x3) << 12)
+
+#define SW_CSI_LANE(a) ((a) & 0x3)
+#define SW_CSI_CH0_SEL(a) (((a) & 0x7) << 4)
+#define SW_CSI_CH1_SEL(a) (((a) & 0x7) << 8)
+#define SW_CSI_CH2_SEL(a) (((a) & 0x7) << 12)
+#define SW_CSI_CH3_SEL(a) (((a) & 0x7) << 16)
+#define SW_LVL0_SEL0_CSI1 BIT(20)
+#define SW_LVL0_SEL1_RAW0 BIT(21)
+#define SW_LVL0_SEL2_RAW1 BIT(22)
+#define SW_LVL0_SEL3_RAW3 BIT(23)
+#define SW_LVL1_SEL0(a) (((a) & 0x3) << 24)
+#define SW_LVL1_SEL1(a) (((a) & 0x3) << 26)
+#define SW_LVL1_SEL2(a) (((a) & 0x3) << 28)
+
+#define SW_CSI_ID0(a) ((a) & 0xff)
+#define SW_CSI_ID1(a) (((a) & 0xff) << 8)
+#define SW_CSI_ID2(a) (((a) & 0xff) << 16)
+#define SW_CSI_ID3(a) (((a) & 0xff) << 24)
+
+#define SW_CSI_ID4(a) ((a) & 0xff)
+#define SW_CSI_ID5(a) (((a) & 0xff) << 8)
+#define SW_CSI_ID6(a) (((a) & 0xff) << 16)
+#define SW_CSI_ID7(a) (((a) & 0xff) << 24)
+
+#define PHY_ERR_SOTHS GENMASK(3, 0)
+#define PHY_ERR_SOTSYNCHS GENMASK(7, 4)
+#define PHY_ERR_EOTSYNCHS GENMASK(11, 8)
+#define PHY_ERR_ESC GENMASK(15, 12)
+#define PHY_ERR_CTL GENMASK(23, 20)
+
+#define PACKET_ERR_F_BNDRY_MATCG GENMASK(3, 0)
+#define PACKET_ERR_F_SEQ GENMASK(7, 4)
+#define PACKET_ERR_FRAME_DATA GENMASK(11, 8)
+#define PACKET_ERR_ID GENMASK(15, 12)
+#define PACKET_ERR_ECC_1BIT GENMASK(19, 16)
+#define PACKET_ERR_ECC_2BIT BIT(20)
+#define PACKET_ERR_CHECKSUM GENMASK(27, 24)
+
+#define AFIFO0_OVERFLOW BIT(0)
+#define AFIFO1X_OVERFLOW GENMASK(7, 4)
+#define LAFIFO1X_OVERFLOW GENMASK(11, 8)
+#define AFIFO2X_OVERFLOW GENMASK(14, 12)
+#define IBUFX3_OVERFLOW GENMASK(18, 16)
+#define IBUF3R_OVERFLOW BIT(19)
+#define Y_STAT_AFIFOX3_OVERFLOW GENMASK(22, 20)
+
+#define RAW0_WR_FRAME BIT(0)
+#define RAW1_WR_FRAME BIT(1)
+#define RAW2_WR_FRAME BIT(2)
+#define MIPI_DROP_FRM BIT(3)
+#define RAW0_RD_FRAME BIT(4)
+#define RAW1_RD_FRAME BIT(5)
+#define RAW2_RD_FRAME BIT(6)
+#define RAW_WR_SIZE_ERR GENMASK(15, 8)
+#define MIPI_LINECNT BIT(16)
+#define RAW_RD_SIZE_ERR GENMASK(19, 17)
+#define MIPI_FRAME_ST_VC(a) (((a) & 0xf) << 20)
+#define MIPI_FRAME_END_VC(a) (((a) & 0xf) << 24)
+#define RAW0_Y_STATE BIT(28)
+#define RAW1_Y_STATE BIT(29)
+#define RAW2_Y_STATE BIT(30)
+
+#define SW_CSI_RAW_WR_EN_ORG BIT(0)
+#define SW_CSI_RAW_WR_SIMG_MODE BIT(1)
+#define SW_CSI_RWA_WR_SIMG_SWP BIT(2)
+#define SW_CSI_RAW_WR_H_OUT BIT(3)
+#define SW_CSI_RAW_WR_CRC_OUT BIT(4)
+#define SW_CSI_RAW_WR_CH_EN(a) (((a) & 0xff) << 8)
+#define SW_CSI_RAW_WR_EN_SHD BIT(31)
+
+#define SW_CSI_RAW_PIC_V_SIZE(a) (((a) & 0x3FFF) << 16)
+#define SW_CSI_RAW_PIC_H_SIZE(a) ((a) & 0x3FFF)
+
+#define SW_CSI_RAW_PIC_V_OFF(a) (((a) & 0x3FFF) << 16)
+#define SW_CSI_RAW_PIC_H_OFF(a) ((a) & 0x3FFF)
+
+#define SW_CSI_RAW0_RD_EN_ORG BIT(0)
+#define SW_CSI_RAW1_RD_EN_ORG BIT(1)
+#define SW_CSI_RAW2_RD_EN_ORG BIT(2)
+#define SW_CSI_RAW_RD_SIMG_MOD BIT(3)
+#define SW_CSI_RAW_RD_SIMG_SWP BIT(4)
+#define SW_CSI_RAW_RD_CH_SEL(a) (((a) & 0x7) << 5)
+
+#define SW_RAW_OUT_EN BIT(0)
+#define SW_RAWFBC_EN BIT(1)
+#define SW_RAWFBC_HEAD_DIFF_EN BIT(4)
+#define SW_RAWFBC_HEAD_DIFF_NUM(a) (((a) & 0x3) << 8)
+
+#define SW_CSI_ESP_LCNT_PADPIX(a) ((a) & 0xFFF)
+#define SW_CSI_ESP_LCNT_PADNUM(a) (((a) & 0x3F) << 12)
+
+#define SW_CSI_ESP_IDCD_OBPIX(a) ((a) & 0x7F)
+#define SW_CSI_ESP_IDCD_EFPIX(a) (((a) & 0x7F) << 16)
+
+#define SW_FPN_EN BIT(0)
+#define SW_FPN_ROW_EN BIT(1)
+#define SW_FPN_BITS(a) (((a) & 0x3) << 2)
+
+#define SW_FPN_CFG BIT(0)
+
+#define SW_Y_STAT_INT_MODE_MASK GENMASK(3, 2)
+#define SW_Y_STAT_RD_FRM_ID_MASK GENMASK(5, 4)
+#define SW_Y_STAT_RD_TILE_ID_MASK GENMASK(7, 6)
+#define SW_Y_STAT_EN BIT(0)
+#define SW_Y_STAT_RD_EN BIT(1)
+#define SW_Y_STAT_INT_MODE(a) (((a) & 0x3) << 2)
+#define SW_Y_STAT_RD_FRM_ID(a) (((a) & 0x3) << 4)
+#define SW_Y_STAT_RD_TILE_ID(a) (((a) & 0x3) << 6)
+#define SW_Y_STAT_BLK_R(a) (((a) & 0x1f) << 8)
+#define SW_Y_STAT_BLK_G(a) (((a) & 0x1f) << 16)
+#define SW_Y_STAT_BLK_B(a) (((a) & 0x1f) << 24)
+
+/* DEBAYER */
+#define SW_DEBAYER_EN BIT(0)
+#define SW_DEBAYER_FILTER_G_EN BIT(4)
+#define SW_DEBAYER_FILTER_C_EN BIT(8)
+
+#define SW_DEBAYER_CLIP_EN BIT(0)
+
+/* HDRMGE */
+#define SW_HDRMGE_EN BIT(0)
+#define SW_HDRMGE_MODE_NORMAL (0 << 2)
+#define SW_HDRMGE_MODE_FRAMEX2 BIT(2)
+#define SW_HDRMGE_MODE_FRAMEX3 (2 << 2)
+
+/* BLS */
+/* ISP_BLS_CTRL */
+#define ISP_BLS_ENA BIT(0)
+#define ISP_BLS_MODE_MEASURED BIT(1)
+#define ISP_BLS_MODE_FIXED 0
+#define ISP_BLS_WINDOW_1 (1 << 2)
+#define ISP_BLS_WINDOW_2 (2 << 2)
+#define ISP_BLS_BLS1_EN BIT(4)
+
+/* GIC */
+/* ISP_GIC_CTRL */
+#define ISP_GIC_ENA BIT(0)
+#define ISP_GIC_EDGE_OPEN BIT(1)
+
+/* DHAZ */
+/* ISP_DHAZ_CTRL */
+#define ISP_DHAZ_ENMUX BIT(0)
+#define ISP_DHAZ_NOBIGEN BIT(2)
+#define ISP_DHAZ_BIGEN BIT(3)
+#define ISP_DHAZ_DCEN BIT(4)
+#define ISP_DHAZ_HSTEN BIT(8)
+#define ISP_DHAZ_HPARAEN BIT(12)
+#define ISP_DHAZ_HSTCHN BIT(16)
+#define ISP_DHAZ_ENHANCE BIT(20)
+
+/* HDRTMO */
+/* ISP_HDRTMO_CTRL */
+#define ISP_HDRTMO_EN BIT(0)
+
+/* HDRDRC */
+/* ISP21_DRC_CTRL0 */
+#define ISP_DRC_EN BIT(0)
+
+/* HDRMGE */
+/* ISP_HDRMGE_CTRL */
+#define ISP_HDRMGE_MODE_MASK GENMASK(3, 2)
+#define ISP_HDRMGE_EN BIT(0)
+
+/* RAWNR */
+/* ISP_RAWNR_CTRL */
+#define ISP_RAWNR_EN BIT(0)
+
+/* DPCC */
+/* ISP_DPCC_CTRL */
+#define ISP_DPCC_EN BIT(0)
+
+/* CCM */
+/* ISP_CCM_CTRL */
+#define ISP_CCM_EN BIT(0)
+
+/* 3DLUT */
+/* ISP_3DLUT_CTRL */
+#define ISP_3DLUT_EN BIT(0)
+#define ISP_3DLUT_BYPASS BIT(1)
+
+/* DEBAYER */
+/* ISP_DEBAYER_CONTROL */
+#define ISP_DEBAYER_EN BIT(0)
+
+/* LSC */
+/* ISP_LSC_CTRL */
+#define ISP_LSC_EN BIT(0)
+#define ISP_LSC_LUT_EN BIT(1)
+#define ISP_ISP_LSC_TABLE_DATA(v0, v1) \
+ (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
+
+#define ISP21_YNR_EN BIT(0)
+#define ISP21_CNR_EN BIT(0)
+#define ISP21_SHARP_EN BIT(0)
+#define ISP21_BAYNR_EN BIT(0)
+#define ISP21_BAY3D_EN BIT(0)
+
+/* ISP21 ISP CTRL0 */
+#define ISP21_CGC_RATIO_EN BIT(29)
+#define ISP21_CGC_YUV_LIMIT BIT(28)
+#define ISP21_NOC_HURRY_W1_MODE(a) (((a) & 0x7) << 24)
+
+/* ISP CTRL1 */
+#define ISP21_BIGMODE_MODE BIT(29)
+#define ISP21_BIGMODE_FORCE_EN BIT(28)
+#define ISP21_RAW3D_FST_FRAME BIT(27)
+#define ISP21_CNR_FST_FRAME BIT(26)
+#define ISP21_DHAZ_FST_FRAME BIT(25)
+#define ISP21_ADRC_FST_FRAME BIT(24)
+#define ISP21_YNR_FST_FRAME BIT(23)
+#define ISP21_BT1120_YC_SWAP BIT(22)
+#define ISP21_DUALEDGE_EN BIT(21)
+#define ISP21_BI1120_EN BIT(20)
+#define ISP21_FIELD_INV BIT(11)
+
+/* ISP21 ACQ_H_OFFS */
+#define ISP21_SENSOR_MODE(a) (((a) & 3) << 30)
+#define ISP21_SENSOR_INDEX(a) (((a) & 3) << 28)
+#define ISP21_ACQ_H_OFFS(a) ((a) & 0x7fff)
+
+/* ISP21 ACQ_H_SIZE */
+#define ISP21_ACQ_H_SIZE_BAY3DMI(a) (((a) & 0xffff) << 16)
+#define ISP21_ACQ_H_SIZE(a) ((a) & 0x7fff)
+
+/* ISP21 MI_WR_INIT */
+#define ISP21_SP_FORCE_UPD BIT(21)
+#define ISP21_MP_FORCE_UPD BIT(20)
+
+/* ISP21 MI_WR_CTRL2*/
+#define ISP21_BAY3D_FORCE_UPD BIT(22)
+#define ISP21_GAIN_FORCE_UPD BIT(21)
+#define ISP21_DBR_FORCE_UPD BIT(20)
+#define ISP21_BAY3D_WR_AUTO_UPD BIT(16)
+
+/* ISP21 CSI2RX */
+#define ISP21_CSI_2PIX_MODE BIT(1)
+
+#define ISP21_MIPI_DROP_FRM BIT(31)
+
+#define ISP21_RAW3_WR_FRAME BIT(3)
+
+#define ISP21_RAW_FORCE_UPD BIT(31)
+
+/* ISP21 DHAZ/DRC/BAY3D */
+#define ISP21_SELF_FORCE_UPD BIT(31)
+
+#endif /* _RKISP_REGS_V2X_H */
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
new file mode 100644
index 000000000000..bb79d08d206f
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
@@ -0,0 +1,3383 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _RKISP2_REGS_ISP3X_H
+#define _RKISP2_REGS_ISP3X_H
+
+#define ISP3X_CTRL_BASE 0x00000000
+#define ISP3X_VI_ISP_EN (ISP3X_CTRL_BASE + 0x00000)
+#define ISP3X_VI_ISP_PATH (ISP3X_CTRL_BASE + 0x00004)
+#define ISP3X_VI_ID (ISP3X_CTRL_BASE + 0x00008)
+#define ISP3X_VI_ISP_CLK_CTRL (ISP3X_CTRL_BASE + 0x0000c)
+#define ISP3X_VI_ICCL (ISP3X_CTRL_BASE + 0x00010)
+#define ISP3X_VI_IRCL (ISP3X_CTRL_BASE + 0x00014)
+#define ISP3X_VI_DPCL (ISP3X_CTRL_BASE + 0x00018)
+#define ISP3X_SWS_CFG (ISP3X_CTRL_BASE + 0x0001c)
+
+#define ISP3X_IMG_EFF_BASE 0x00000200
+#define ISP3X_IMG_EFF_CTRL (ISP3X_IMG_EFF_BASE + 0x00000)
+#define ISP3X_IMG_EFF_COLOR_SEL (ISP3X_IMG_EFF_BASE + 0x00004)
+#define ISP3X_IMG_EFF_TINT (ISP3X_IMG_EFF_BASE + 0x0001c)
+#define ISP3X_IMG_EFF_CTRL_SHD (ISP3X_IMG_EFF_BASE + 0x00020)
+
+#define ISP3X_CMSK_BASE 0x00000230
+#define ISP3X_CMSK_CTRL0 (ISP3X_CMSK_BASE + 0x00000)
+#define ISP3X_CMSK_CTRL1 (ISP3X_CMSK_BASE + 0x00004)
+#define ISP3X_CMSK_CTRL2 (ISP3X_CMSK_BASE + 0x00008)
+#define ISP3X_CMSK_CTRL3 (ISP3X_CMSK_BASE + 0x0000c)
+#define ISP3X_CMSK_CTRL4 (ISP3X_CMSK_BASE + 0x00010)
+#define ISP3X_CMSK_CTRL5 (ISP3X_CMSK_BASE + 0x00014)
+#define ISP3X_CMSK_CTRL6 (ISP3X_CMSK_BASE + 0x00018)
+#define ISP3X_CMSK_PIC_SIZE (ISP3X_CMSK_BASE + 0x0001c)
+#define ISP3X_CMSK_YUV0 (ISP3X_CMSK_BASE + 0x00020)
+#define ISP3X_CMSK_YUV1 (ISP3X_CMSK_BASE + 0x00024)
+#define ISP3X_CMSK_YUV2 (ISP3X_CMSK_BASE + 0x00028)
+#define ISP3X_CMSK_YUV3 (ISP3X_CMSK_BASE + 0x0002c)
+#define ISP3X_CMSK_YUV4 (ISP3X_CMSK_BASE + 0x00030)
+#define ISP3X_CMSK_YUV5 (ISP3X_CMSK_BASE + 0x00034)
+#define ISP3X_CMSK_YUV6 (ISP3X_CMSK_BASE + 0x00038)
+#define ISP3X_CMSK_YUV7 (ISP3X_CMSK_BASE + 0x0003c)
+#define ISP32_CMSK_YUV8 (ISP3X_CMSK_BASE + 0x00040)
+#define ISP32_CMSK_YUV9 (ISP3X_CMSK_BASE + 0x00044)
+#define ISP32_CMSK_YUV10 (ISP3X_CMSK_BASE + 0x00048)
+#define ISP32_CMSK_YUV11 (ISP3X_CMSK_BASE + 0x0004c)
+#define ISP3X_CMSK_OFFS0 (ISP3X_CMSK_BASE + 0x00050)
+#define ISP3X_CMSK_SIZE0 (ISP3X_CMSK_BASE + 0x00054)
+#define ISP3X_CMSK_OFFS1 (ISP3X_CMSK_BASE + 0x00058)
+#define ISP3X_CMSK_SIZE1 (ISP3X_CMSK_BASE + 0x0005c)
+#define ISP3X_CMSK_OFFS2 (ISP3X_CMSK_BASE + 0x00060)
+#define ISP3X_CMSK_SIZE2 (ISP3X_CMSK_BASE + 0x00064)
+#define ISP3X_CMSK_OFFS3 (ISP3X_CMSK_BASE + 0x00068)
+#define ISP3X_CMSK_SIZE3 (ISP3X_CMSK_BASE + 0x0006c)
+#define ISP3X_CMSK_OFFS4 (ISP3X_CMSK_BASE + 0x00070)
+#define ISP3X_CMSK_SIZE4 (ISP3X_CMSK_BASE + 0x00074)
+#define ISP3X_CMSK_OFFS5 (ISP3X_CMSK_BASE + 0x00078)
+#define ISP3X_CMSK_SIZE5 (ISP3X_CMSK_BASE + 0x0007c)
+#define ISP3X_CMSK_OFFS6 (ISP3X_CMSK_BASE + 0x00080)
+#define ISP3X_CMSK_SIZE6 (ISP3X_CMSK_BASE + 0x00084)
+#define ISP3X_CMSK_OFFS7 (ISP3X_CMSK_BASE + 0x00088)
+#define ISP3X_CMSK_SIZE7 (ISP3X_CMSK_BASE + 0x0008c)
+#define ISP32_CMSK_OFFS8 (ISP3X_CMSK_BASE + 0x00090)
+#define ISP32_CMSK_SIZE8 (ISP3X_CMSK_BASE + 0x00094)
+#define ISP32_CMSK_OFFS9 (ISP3X_CMSK_BASE + 0x00098)
+#define ISP32_CMSK_SIZE9 (ISP3X_CMSK_BASE + 0x0009c)
+#define ISP32_CMSK_OFFS10 (ISP3X_CMSK_BASE + 0x000a0)
+#define ISP32_CMSK_SIZE10 (ISP3X_CMSK_BASE + 0x000a4)
+#define ISP32_CMSK_OFFS11 (ISP3X_CMSK_BASE + 0x000a8)
+#define ISP32_CMSK_SIZE11 (ISP3X_CMSK_BASE + 0x000ac)
+
+#define ISP3X_SUPER_IMP_BASE 0x00000300
+#define ISP3X_SUPER_IMP_CTRL (ISP3X_SUPER_IMP_BASE + 0x00000)
+#define ISP3X_SUPER_IMP_OFFSET_X (ISP3X_SUPER_IMP_BASE + 0x00004)
+#define ISP3X_SUPER_IMP_OFFSET_Y (ISP3X_SUPER_IMP_BASE + 0x00008)
+#define ISP3X_SUPER_IMP_COLOR_Y (ISP3X_SUPER_IMP_BASE + 0x0000c)
+#define ISP3X_SUPER_IMP_COLOR_CB (ISP3X_SUPER_IMP_BASE + 0x00010)
+#define ISP3X_SUPER_IMP_COLOR_CR (ISP3X_SUPER_IMP_BASE + 0x00014)
+
+#define ISP3X_ISP_BASE 0x00000400
+#define ISP3X_ISP_CTRL0 (ISP3X_ISP_BASE + 0x00000)
+#define ISP3X_ISP_CTRL1 (ISP3X_ISP_BASE + 0x00004)
+#define ISP3X_ISP_ACQ_H_OFFS (ISP3X_ISP_BASE + 0x00008)
+#define ISP3X_ISP_ACQ_V_OFFS (ISP3X_ISP_BASE + 0x0000c)
+#define ISP3X_ISP_ACQ_H_SIZE (ISP3X_ISP_BASE + 0x00010)
+#define ISP3X_ISP_ACQ_V_SIZE (ISP3X_ISP_BASE + 0x00014)
+#define ISP3X_ISP_ACQ_NR_FRAMES (ISP3X_ISP_BASE + 0x00018)
+#define ISP3X_ISP_GAMMA_DX_LO (ISP3X_ISP_BASE + 0x0001c)
+#define ISP3X_ISP_GAMMA_DX_HI (ISP3X_ISP_BASE + 0x00020)
+#define ISP3X_ISP_GAMMA_R_Y_0 (ISP3X_ISP_BASE + 0x00024)
+#define ISP3X_ISP_GAMMA_R_Y_1 (ISP3X_ISP_BASE + 0x00028)
+#define ISP3X_ISP_GAMMA_R_Y_2 (ISP3X_ISP_BASE + 0x0002c)
+#define ISP3X_ISP_GAMMA_R_Y_3 (ISP3X_ISP_BASE + 0x00030)
+#define ISP3X_ISP_GAMMA_R_Y_4 (ISP3X_ISP_BASE + 0x00034)
+#define ISP3X_ISP_GAMMA_R_Y_5 (ISP3X_ISP_BASE + 0x00038)
+#define ISP3X_ISP_GAMMA_R_Y_6 (ISP3X_ISP_BASE + 0x0003c)
+#define ISP3X_ISP_GAMMA_R_Y_7 (ISP3X_ISP_BASE + 0x00040)
+#define ISP3X_ISP_GAMMA_R_Y_8 (ISP3X_ISP_BASE + 0x00044)
+#define ISP3X_ISP_GAMMA_R_Y_9 (ISP3X_ISP_BASE + 0x00048)
+#define ISP3X_ISP_GAMMA_R_Y_10 (ISP3X_ISP_BASE + 0x0004c)
+#define ISP3X_ISP_GAMMA_R_Y_11 (ISP3X_ISP_BASE + 0x00050)
+#define ISP3X_ISP_GAMMA_R_Y_12 (ISP3X_ISP_BASE + 0x00054)
+#define ISP3X_ISP_GAMMA_R_Y_13 (ISP3X_ISP_BASE + 0x00058)
+#define ISP3X_ISP_GAMMA_R_Y_14 (ISP3X_ISP_BASE + 0x0005c)
+#define ISP3X_ISP_GAMMA_R_Y_15 (ISP3X_ISP_BASE + 0x00060)
+#define ISP3X_ISP_GAMMA_R_Y_16 (ISP3X_ISP_BASE + 0x00064)
+#define ISP3X_ISP_GAMMA_G_Y_0 (ISP3X_ISP_BASE + 0x00068)
+#define ISP3X_ISP_GAMMA_G_Y_1 (ISP3X_ISP_BASE + 0x0006c)
+#define ISP3X_ISP_GAMMA_G_Y_2 (ISP3X_ISP_BASE + 0x00070)
+#define ISP3X_ISP_GAMMA_G_Y_3 (ISP3X_ISP_BASE + 0x00074)
+#define ISP3X_ISP_GAMMA_G_Y_4 (ISP3X_ISP_BASE + 0x00078)
+#define ISP3X_ISP_GAMMA_G_Y_5 (ISP3X_ISP_BASE + 0x0007c)
+#define ISP3X_ISP_GAMMA_G_Y_6 (ISP3X_ISP_BASE + 0x00080)
+#define ISP3X_ISP_GAMMA_G_Y_7 (ISP3X_ISP_BASE + 0x00084)
+#define ISP3X_ISP_GAMMA_G_Y_8 (ISP3X_ISP_BASE + 0x00088)
+#define ISP3X_ISP_GAMMA_G_Y_9 (ISP3X_ISP_BASE + 0x0008c)
+#define ISP3X_ISP_GAMMA_G_Y_10 (ISP3X_ISP_BASE + 0x00090)
+#define ISP3X_ISP_GAMMA_G_Y_11 (ISP3X_ISP_BASE + 0x00094)
+#define ISP3X_ISP_GAMMA_G_Y_12 (ISP3X_ISP_BASE + 0x00098)
+#define ISP3X_ISP_GAMMA_G_Y_13 (ISP3X_ISP_BASE + 0x0009c)
+#define ISP3X_ISP_GAMMA_G_Y_14 (ISP3X_ISP_BASE + 0x000a0)
+#define ISP3X_ISP_GAMMA_G_Y_15 (ISP3X_ISP_BASE + 0x000a4)
+#define ISP3X_ISP_GAMMA_G_Y_16 (ISP3X_ISP_BASE + 0x000a8)
+#define ISP3X_ISP_GAMMA_B_Y_0 (ISP3X_ISP_BASE + 0x000ac)
+#define ISP3X_ISP_GAMMA_B_Y_1 (ISP3X_ISP_BASE + 0x000b0)
+#define ISP3X_ISP_GAMMA_B_Y_2 (ISP3X_ISP_BASE + 0x000b4)
+#define ISP3X_ISP_GAMMA_B_Y_3 (ISP3X_ISP_BASE + 0x000b8)
+#define ISP3X_ISP_GAMMA_B_Y_4 (ISP3X_ISP_BASE + 0x000bc)
+#define ISP3X_ISP_GAMMA_B_Y_5 (ISP3X_ISP_BASE + 0x000c0)
+#define ISP3X_ISP_GAMMA_B_Y_6 (ISP3X_ISP_BASE + 0x000c4)
+#define ISP3X_ISP_GAMMA_B_Y_7 (ISP3X_ISP_BASE + 0x000c8)
+#define ISP3X_ISP_GAMMA_B_Y_8 (ISP3X_ISP_BASE + 0x000cc)
+#define ISP3X_ISP_GAMMA_B_Y_9 (ISP3X_ISP_BASE + 0x000d0)
+#define ISP3X_ISP_GAMMA_B_Y_10 (ISP3X_ISP_BASE + 0x000d4)
+#define ISP3X_ISP_GAMMA_B_Y_11 (ISP3X_ISP_BASE + 0x000d8)
+#define ISP3X_ISP_GAMMA_B_Y_12 (ISP3X_ISP_BASE + 0x000dc)
+#define ISP3X_ISP_GAMMA_B_Y_13 (ISP3X_ISP_BASE + 0x000e0)
+#define ISP3X_ISP_GAMMA_B_Y_14 (ISP3X_ISP_BASE + 0x000e4)
+#define ISP3X_ISP_GAMMA_B_Y_15 (ISP3X_ISP_BASE + 0x000e8)
+#define ISP3X_ISP_GAMMA_B_Y_16 (ISP3X_ISP_BASE + 0x000ec)
+#define ISP32_ISP_AWB1_GAIN_G (ISP3X_ISP_BASE + 0x00130)
+#define ISP32_ISP_AWB1_GAIN_RB (ISP3X_ISP_BASE + 0x00134)
+#define ISP3X_ISP_AWB_GAIN0_G (ISP3X_ISP_BASE + 0x00138)
+#define ISP3X_ISP_AWB_GAIN0_RB (ISP3X_ISP_BASE + 0x0013c)
+#define ISP3X_ISP_AWB_GAIN1_G (ISP3X_ISP_BASE + 0x00140)
+#define ISP3X_ISP_AWB_GAIN1_RB (ISP3X_ISP_BASE + 0x00144)
+#define ISP3X_ISP_AWB_GAIN2_G (ISP3X_ISP_BASE + 0x00148)
+#define ISP3X_ISP_AWB_GAIN2_RB (ISP3X_ISP_BASE + 0x0014C)
+#define ISP3X_ISP_HURRY_CTRL (ISP3X_ISP_BASE + 0x00158)
+#define ISP3X_ISP_AWQOS_CTRL (ISP3X_ISP_BASE + 0x0015C)
+#define ISP3X_ISP_ARQOS_CTRL (ISP3X_ISP_BASE + 0x00160)
+#define ISP32_ISP_IRQ_CFG0 (ISP3X_ISP_BASE + 0x00164)
+#define ISP32_ISP_IRQ_CFG1 (ISP3X_ISP_BASE + 0x00168)
+#define ISP3X_ISP_CC_COEFF_0 (ISP3X_ISP_BASE + 0x00170)
+#define ISP3X_ISP_CC_COEFF_1 (ISP3X_ISP_BASE + 0x00174)
+#define ISP3X_ISP_CC_COEFF_2 (ISP3X_ISP_BASE + 0x00178)
+#define ISP3X_ISP_CC_COEFF_3 (ISP3X_ISP_BASE + 0x0017c)
+#define ISP3X_ISP_CC_COEFF_4 (ISP3X_ISP_BASE + 0x00180)
+#define ISP3X_ISP_CC_COEFF_5 (ISP3X_ISP_BASE + 0x00184)
+#define ISP3X_ISP_CC_COEFF_6 (ISP3X_ISP_BASE + 0x00188)
+#define ISP3X_ISP_CC_COEFF_7 (ISP3X_ISP_BASE + 0x0018c)
+#define ISP3X_ISP_CC_COEFF_8 (ISP3X_ISP_BASE + 0x00190)
+#define ISP3X_ISP_OUT_H_OFFS (ISP3X_ISP_BASE + 0x00194)
+#define ISP3X_ISP_OUT_V_OFFS (ISP3X_ISP_BASE + 0x00198)
+#define ISP3X_ISP_OUT_H_SIZE (ISP3X_ISP_BASE + 0x0019c)
+#define ISP3X_ISP_OUT_V_SIZE (ISP3X_ISP_BASE + 0x001a0)
+#define ISP3X_ISP_FLAGS_SHD (ISP3X_ISP_BASE + 0x001a8)
+#define ISP3X_ISP_OUT_H_OFFS_SHD (ISP3X_ISP_BASE + 0x001ac)
+#define ISP3X_ISP_OUT_V_OFFS_SHD (ISP3X_ISP_BASE + 0x001b0)
+#define ISP3X_ISP_OUT_H_SIZE_SHD (ISP3X_ISP_BASE + 0x001b4)
+#define ISP3X_ISP_OUT_V_SIZE_SHD (ISP3X_ISP_BASE + 0x001b8)
+#define ISP3X_ISP_IMSC (ISP3X_ISP_BASE + 0x001bc)
+#define ISP3X_ISP_RIS (ISP3X_ISP_BASE + 0x001c0)
+#define ISP3X_ISP_MIS (ISP3X_ISP_BASE + 0x001c4)
+#define ISP3X_ISP_ICR (ISP3X_ISP_BASE + 0x001c8)
+#define ISP3X_ISP_ISR (ISP3X_ISP_BASE + 0x001cc)
+#define ISP3X_ISP_3A_IMSC (ISP3X_ISP_BASE + 0x001d0)
+#define ISP3X_ISP_3A_RIS (ISP3X_ISP_BASE + 0x001d4)
+#define ISP3X_ISP_3A_MIS (ISP3X_ISP_BASE + 0x001d8)
+#define ISP3X_ISP_3A_ICR (ISP3X_ISP_BASE + 0x001dc)
+#define ISP3X_ISP_ERR (ISP3X_ISP_BASE + 0x0023c)
+#define ISP3X_ISP_ERR_CLR (ISP3X_ISP_BASE + 0x00240)
+#define ISP3X_ISP_FRAME_COUNT (ISP3X_ISP_BASE + 0x00244)
+#define ISP3X_ISP_DEBUG1 (ISP3X_ISP_BASE + 0x00248)
+#define ISP3X_ISP_DEBUG2 (ISP3X_ISP_BASE + 0x0024C)
+#define ISP3X_ISP_DEBUG3 (ISP3X_ISP_BASE + 0x00250)
+#define ISP32_ISP_DEBUG4 (ISP3X_ISP_BASE + 0x00254)
+#define ISP32_YNR_LUMA_RCTRL (ISP3X_ISP_BASE + 0x00290)
+#define ISP32_YNR_LUMA_RDATA (ISP3X_ISP_BASE + 0x00294)
+#define ISP39_SLICE_ST_CTRL (ISP3X_ISP_BASE + 0x002a4)
+#define ISP39_AIISP_LINE_CNT (ISP3X_ISP_BASE + 0x002a8)
+
+#define ISP3X_FLASH_BASE 0x00000660
+#define ISP3X_FLASH_CMD (ISP3X_FLASH_BASE + 0x00000)
+#define ISP3X_FLASH_CONFIG (ISP3X_FLASH_BASE + 0x00004)
+#define ISP3X_FLASH_PREDIV (ISP3X_FLASH_BASE + 0x00008)
+#define ISP3X_FLASH_DELAY (ISP3X_FLASH_BASE + 0x0000c)
+#define ISP3X_FLASH_TIME (ISP3X_FLASH_BASE + 0x00010)
+#define ISP3X_FLASH_MAXP (ISP3X_FLASH_BASE + 0x00014)
+
+#define ISP3X_SHUTTER_BASE 0x00000680
+#define ISP3X_SHUTTER_CTRL (ISP3X_SHUTTER_BASE + 0x00000)
+#define ISP3X_SHUTTER_PREDIV (ISP3X_SHUTTER_BASE + 0x00004)
+#define ISP3X_SHUTTER_DELAY (ISP3X_SHUTTER_BASE + 0x00008)
+#define ISP3X_SHUTTER_TIME (ISP3X_SHUTTER_BASE + 0x0000c)
+
+#define ISP3X_CCM_BASE 0x00000700
+#define ISP3X_CCM_CTRL (ISP3X_CCM_BASE + 0x00000)
+#define ISP3X_CCM_COEFF0_R (ISP3X_CCM_BASE + 0x00004)
+#define ISP3X_CCM_COEFF1_R (ISP3X_CCM_BASE + 0x00008)
+#define ISP3X_CCM_COEFF0_G (ISP3X_CCM_BASE + 0x0000c)
+#define ISP3X_CCM_COEFF1_G (ISP3X_CCM_BASE + 0x00010)
+#define ISP3X_CCM_COEFF0_B (ISP3X_CCM_BASE + 0x00014)
+#define ISP3X_CCM_COEFF1_B (ISP3X_CCM_BASE + 0x00018)
+#define ISP3X_CCM_COEFF0_Y (ISP3X_CCM_BASE + 0x0001c)
+#define ISP3X_CCM_COEFF1_Y (ISP3X_CCM_BASE + 0x00020)
+#define ISP3X_CCM_ALP_Y0 (ISP3X_CCM_BASE + 0x00024)
+#define ISP3X_CCM_ALP_Y1 (ISP3X_CCM_BASE + 0x00028)
+#define ISP3X_CCM_ALP_Y2 (ISP3X_CCM_BASE + 0x0002c)
+#define ISP3X_CCM_ALP_Y3 (ISP3X_CCM_BASE + 0x00030)
+#define ISP3X_CCM_ALP_Y4 (ISP3X_CCM_BASE + 0x00034)
+#define ISP3X_CCM_ALP_Y5 (ISP3X_CCM_BASE + 0x00038)
+#define ISP3X_CCM_ALP_Y6 (ISP3X_CCM_BASE + 0x0003c)
+#define ISP3X_CCM_ALP_Y7 (ISP3X_CCM_BASE + 0x00040)
+#define ISP3X_CCM_ALP_Y8 (ISP3X_CCM_BASE + 0x00044)
+#define ISP3X_CCM_BOUND_BIT (ISP3X_CCM_BASE + 0x00048)
+#define ISP32_CCM_ENHANCE0 (ISP3X_CCM_BASE + 0x0004c)
+#define ISP32_CCM_ENHANCE1 (ISP3X_CCM_BASE + 0x00050)
+#define ISP39_CCM_HF_THD (ISP3X_CCM_BASE + 0x00054)
+#define ISP39_HF_FACTOR0 (ISP3X_CCM_BASE + 0x00058)
+#define ISP39_HF_FACTOR1 (ISP3X_CCM_BASE + 0x0005c)
+#define ISP39_HF_FACTOR2 (ISP3X_CCM_BASE + 0x00060)
+#define ISP39_HF_FACTOR3 (ISP3X_CCM_BASE + 0x00064)
+#define ISP39_HF_FACTOR4 (ISP3X_CCM_BASE + 0x00068)
+#define ISP39_HF_FACTOR5 (ISP3X_CCM_BASE + 0x0006c)
+#define ISP39_HF_FACTOR6 (ISP3X_CCM_BASE + 0x00070)
+#define ISP39_HF_FACTOR7 (ISP3X_CCM_BASE + 0x00074)
+#define ISP39_HF_FACTOR8 (ISP3X_CCM_BASE + 0x00078)
+#define ISP33_CCM_HF_THD (ISP3X_CCM_BASE + 0x00054)
+#define ISP33_CCM_HF_FACTOR0 (ISP3X_CCM_BASE + 0x00058)
+#define ISP33_CCM_HF_FACTOR8 (ISP3X_CCM_BASE + 0x00078)
+
+#define ISP3X_CPROC_BASE 0x00000800
+#define ISP3X_CPROC_CTRL (ISP3X_CPROC_BASE + 0x00000)
+#define ISP3X_CPROC_CONTRAST (ISP3X_CPROC_BASE + 0x00004)
+#define ISP3X_CPROC_BRIGHTNESS (ISP3X_CPROC_BASE + 0x00008)
+#define ISP3X_CPROC_SATURATION (ISP3X_CPROC_BASE + 0x0000c)
+#define ISP3X_CPROC_HUE (ISP3X_CPROC_BASE + 0x00010)
+
+#define ISP3X_DUAL_CROP_BASE 0x00000880
+#define ISP3X_DUAL_CROP_CTRL (ISP3X_DUAL_CROP_BASE + 0x00000)
+#define ISP3X_DUAL_CROP_M_H_OFFS (ISP3X_DUAL_CROP_BASE + 0x00004)
+#define ISP3X_DUAL_CROP_M_V_OFFS (ISP3X_DUAL_CROP_BASE + 0x00008)
+#define ISP3X_DUAL_CROP_M_H_SIZE (ISP3X_DUAL_CROP_BASE + 0x0000c)
+#define ISP3X_DUAL_CROP_M_V_SIZE (ISP3X_DUAL_CROP_BASE + 0x00010)
+#define ISP3X_DUAL_CROP_S_H_OFFS (ISP3X_DUAL_CROP_BASE + 0x00014)
+#define ISP3X_DUAL_CROP_S_V_OFFS (ISP3X_DUAL_CROP_BASE + 0x00018)
+#define ISP3X_DUAL_CROP_S_H_SIZE (ISP3X_DUAL_CROP_BASE + 0x0001c)
+#define ISP3X_DUAL_CROP_S_V_SIZE (ISP3X_DUAL_CROP_BASE + 0x00020)
+#define ISP3X_DUAL_CROP_M_H_OFFS_SHD (ISP3X_DUAL_CROP_BASE + 0x00024)
+#define ISP3X_DUAL_CROP_M_V_OFFS_SHD (ISP3X_DUAL_CROP_BASE + 0x00028)
+#define ISP3X_DUAL_CROP_M_H_SIZE_SHD (ISP3X_DUAL_CROP_BASE + 0x0002c)
+#define ISP3X_DUAL_CROP_M_V_SIZE_SHD (ISP3X_DUAL_CROP_BASE + 0x00030)
+#define ISP3X_DUAL_CROP_S_H_OFFS_SHD (ISP3X_DUAL_CROP_BASE + 0x00034)
+#define ISP3X_DUAL_CROP_S_V_OFFS_SHD (ISP3X_DUAL_CROP_BASE + 0x00038)
+#define ISP3X_DUAL_CROP_S_H_SIZE_SHD (ISP3X_DUAL_CROP_BASE + 0x0003c)
+#define ISP3X_DUAL_CROP_S_V_SIZE_SHD (ISP3X_DUAL_CROP_BASE + 0x00040)
+#define ISP3X_DUAL_CROP_FBC_H_OFFS (ISP3X_DUAL_CROP_BASE + 0x00044)
+#define ISP3X_DUAL_CROP_FBC_V_OFFS (ISP3X_DUAL_CROP_BASE + 0x00048)
+#define ISP3X_DUAL_CROP_FBC_H_SIZE (ISP3X_DUAL_CROP_BASE + 0x0004C)
+#define ISP3X_DUAL_CROP_FBC_V_SIZE (ISP3X_DUAL_CROP_BASE + 0x00050)
+#define ISP3X_DUAL_CROP_FBC_H_OFFS_SHD (ISP3X_DUAL_CROP_BASE + 0x00054)
+#define ISP3X_DUAL_CROP_FBC_V_OFFS_SHD (ISP3X_DUAL_CROP_BASE + 0x00058)
+#define ISP3X_DUAL_CROP_FBC_H_SIZE_SHD (ISP3X_DUAL_CROP_BASE + 0x0005C)
+#define ISP3X_DUAL_CROP_FBC_V_SIZE_SHD (ISP3X_DUAL_CROP_BASE + 0x00060)
+
+#define ISP3X_GAMMA_OUT_BASE 0x00000900
+#define ISP3X_GAMMA_OUT_CTRL (ISP3X_GAMMA_OUT_BASE + 0x00000)
+#define ISP3X_GAMMA_OUT_OFFSET (ISP3X_GAMMA_OUT_BASE + 0x00004)
+#define ISP3X_GAMMA_OUT_Y0 (ISP3X_GAMMA_OUT_BASE + 0x00010)
+#define ISP3X_GAMMA_OUT_Y1 (ISP3X_GAMMA_OUT_BASE + 0x00014)
+#define ISP3X_GAMMA_OUT_Y2 (ISP3X_GAMMA_OUT_BASE + 0x00018)
+#define ISP3X_GAMMA_OUT_Y3 (ISP3X_GAMMA_OUT_BASE + 0x0001c)
+#define ISP3X_GAMMA_OUT_Y4 (ISP3X_GAMMA_OUT_BASE + 0x00020)
+#define ISP3X_GAMMA_OUT_Y5 (ISP3X_GAMMA_OUT_BASE + 0x00024)
+#define ISP3X_GAMMA_OUT_Y6 (ISP3X_GAMMA_OUT_BASE + 0x00028)
+#define ISP3X_GAMMA_OUT_Y7 (ISP3X_GAMMA_OUT_BASE + 0x0002c)
+#define ISP3X_GAMMA_OUT_Y8 (ISP3X_GAMMA_OUT_BASE + 0x00030)
+#define ISP3X_GAMMA_OUT_Y9 (ISP3X_GAMMA_OUT_BASE + 0x00034)
+#define ISP3X_GAMMA_OUT_Y10 (ISP3X_GAMMA_OUT_BASE + 0x00038)
+#define ISP3X_GAMMA_OUT_Y11 (ISP3X_GAMMA_OUT_BASE + 0x0003c)
+#define ISP3X_GAMMA_OUT_Y12 (ISP3X_GAMMA_OUT_BASE + 0x00040)
+#define ISP3X_GAMMA_OUT_Y13 (ISP3X_GAMMA_OUT_BASE + 0x00044)
+#define ISP3X_GAMMA_OUT_Y14 (ISP3X_GAMMA_OUT_BASE + 0x00048)
+#define ISP3X_GAMMA_OUT_Y15 (ISP3X_GAMMA_OUT_BASE + 0x0004c)
+#define ISP3X_GAMMA_OUT_Y16 (ISP3X_GAMMA_OUT_BASE + 0x00050)
+#define ISP3X_GAMMA_OUT_Y17 (ISP3X_GAMMA_OUT_BASE + 0x00054)
+#define ISP3X_GAMMA_OUT_Y18 (ISP3X_GAMMA_OUT_BASE + 0x00058)
+#define ISP3X_GAMMA_OUT_Y19 (ISP3X_GAMMA_OUT_BASE + 0x0005c)
+#define ISP3X_GAMMA_OUT_Y20 (ISP3X_GAMMA_OUT_BASE + 0x00060)
+#define ISP3X_GAMMA_OUT_Y21 (ISP3X_GAMMA_OUT_BASE + 0x00064)
+#define ISP3X_GAMMA_OUT_Y22 (ISP3X_GAMMA_OUT_BASE + 0x00068)
+#define ISP3X_GAMMA_OUT_Y23 (ISP3X_GAMMA_OUT_BASE + 0x0006c)
+#define ISP3X_GAMMA_OUT_Y24 (ISP3X_GAMMA_OUT_BASE + 0x00070)
+
+#define ISP3X_MAIN_RESIZE_BASE 0x00000C00
+#define ISP3X_MAIN_RESIZE_CTRL (ISP3X_MAIN_RESIZE_BASE + 0x00000)
+#define ISP3X_MAIN_RESIZE_SCALE_HY (ISP3X_MAIN_RESIZE_BASE + 0x00004)
+#define ISP3X_MAIN_RESIZE_SCALE_HCB (ISP3X_MAIN_RESIZE_BASE + 0x00008)
+#define ISP3X_MAIN_RESIZE_SCALE_HCR (ISP3X_MAIN_RESIZE_BASE + 0x0000c)
+#define ISP3X_MAIN_RESIZE_SCALE_VY (ISP3X_MAIN_RESIZE_BASE + 0x00010)
+#define ISP3X_MAIN_RESIZE_SCALE_VC (ISP3X_MAIN_RESIZE_BASE + 0x00014)
+#define ISP3X_MAIN_RESIZE_PHASE_HY (ISP3X_MAIN_RESIZE_BASE + 0x00018)
+#define ISP3X_MAIN_RESIZE_PHASE_HC (ISP3X_MAIN_RESIZE_BASE + 0x0001c)
+#define ISP3X_MAIN_RESIZE_PHASE_VY (ISP3X_MAIN_RESIZE_BASE + 0x00020)
+#define ISP3X_MAIN_RESIZE_PHASE_VC (ISP3X_MAIN_RESIZE_BASE + 0x00024)
+#define ISP3X_MAIN_RESIZE_SCALE_LUT_ADDR (ISP3X_MAIN_RESIZE_BASE + 0x00028)
+#define ISP3X_MAIN_RESIZE_SCALE_LUT (ISP3X_MAIN_RESIZE_BASE + 0x0002c)
+#define ISP3X_MAIN_RESIZE_CTRL_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00030)
+#define ISP3X_MAIN_RESIZE_SCALE_HY_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00034)
+#define ISP3X_MAIN_RESIZE_SCALE_HCB_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00038)
+#define ISP3X_MAIN_RESIZE_SCALE_HCR_SHD (ISP3X_MAIN_RESIZE_BASE + 0x0003c)
+#define ISP3X_MAIN_RESIZE_SCALE_VY_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00040)
+#define ISP3X_MAIN_RESIZE_SCALE_VC_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00044)
+#define ISP3X_MAIN_RESIZE_PHASE_HY_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00048)
+#define ISP3X_MAIN_RESIZE_PHASE_HC_SHD (ISP3X_MAIN_RESIZE_BASE + 0x0004c)
+#define ISP3X_MAIN_RESIZE_PHASE_VY_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00050)
+#define ISP3X_MAIN_RESIZE_PHASE_VC_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00054)
+#define ISP3X_MAIN_RESIZE_HY_SIZE (ISP3X_MAIN_RESIZE_BASE + 0x00058)
+#define ISP3X_MAIN_RESIZE_HC_SIZE (ISP3X_MAIN_RESIZE_BASE + 0x0005C)
+#define ISP3X_MAIN_RESIZE_HY_OFFS_MI (ISP3X_MAIN_RESIZE_BASE + 0x00060)
+#define ISP3X_MAIN_RESIZE_HC_OFFS_MI (ISP3X_MAIN_RESIZE_BASE + 0x00064)
+#define ISP3X_MAIN_RESIZE_HY_SIZE_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00068)
+#define ISP3X_MAIN_RESIZE_HC_SIZE_SHD (ISP3X_MAIN_RESIZE_BASE + 0x0006C)
+#define ISP3X_MAIN_RESIZE_HY_OFFS_MI_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00070)
+#define ISP3X_MAIN_RESIZE_HC_OFFS_MI_SHD (ISP3X_MAIN_RESIZE_BASE + 0x00074)
+#define ISP3X_MAIN_RESIZE_IN_CROP_OFFSET (ISP3X_MAIN_RESIZE_BASE + 0x00078)
+
+#define ISP39_MAIN_SCALE_BASE 0x00000c00
+#define ISP39_MAIN_SCALE_CTRL (ISP39_MAIN_SCALE_BASE + 0x0000)
+#define ISP39_MAIN_SCALE_UPDATE (ISP39_MAIN_SCALE_BASE + 0x0004)
+#define ISP39_MAIN_SCALE_SRC_SIZE (ISP39_MAIN_SCALE_BASE + 0x0008)
+#define ISP39_MAIN_SCALE_DST_SIZE (ISP39_MAIN_SCALE_BASE + 0x000c)
+#define ISP39_MAIN_SCALE_HY_FAC (ISP39_MAIN_SCALE_BASE + 0x0010)
+#define ISP39_MAIN_SCALE_HC_FAC (ISP39_MAIN_SCALE_BASE + 0x0014)
+#define ISP39_MAIN_SCALE_VY_FAC (ISP39_MAIN_SCALE_BASE + 0x0018)
+#define ISP39_MAIN_SCALE_VC_FAC (ISP39_MAIN_SCALE_BASE + 0x001c)
+#define ISP39_MAIN_SCALE_HY_OFFS (ISP39_MAIN_SCALE_BASE + 0x0020)
+#define ISP39_MAIN_SCALE_HC_OFFS (ISP39_MAIN_SCALE_BASE + 0x0024)
+#define ISP39_MAIN_SCALE_PHASE_HY (ISP39_MAIN_SCALE_BASE + 0x0030)
+#define ISP39_MAIN_SCALE_PHASE_HC (ISP39_MAIN_SCALE_BASE + 0x0034)
+#define ISP39_MAIN_SCALE_PHASE_VY (ISP39_MAIN_SCALE_BASE + 0x0038)
+#define ISP39_MAIN_SCALE_PHASE_VC (ISP39_MAIN_SCALE_BASE + 0x003c)
+#define ISP39_MAIN_SCALE_HY_SIZE (ISP39_MAIN_SCALE_BASE + 0x0040)
+#define ISP39_MAIN_SCALE_HC_SIZE (ISP39_MAIN_SCALE_BASE + 0x0044)
+#define ISP39_MAIN_SCALE_HY_OFFS_MI (ISP39_MAIN_SCALE_BASE + 0x0048)
+#define ISP39_MAIN_SCALE_HC_OFFS_MI (ISP39_MAIN_SCALE_BASE + 0x004c)
+#define ISP39_MAIN_SCALE_IN_CROP_OFFSET (ISP39_MAIN_SCALE_BASE + 0x0050)
+#define ISP39_MAIN_SCALE_CTRL_SHD (ISP39_MAIN_SCALE_BASE + 0x0080)
+#define ISP39_MAIN_SCALE_SRC_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x0088)
+#define ISP39_MAIN_SCALE_DST_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x008c)
+#define ISP39_MAIN_SCALE_HY_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x0090)
+#define ISP39_MAIN_SCALE_HC_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x0094)
+#define ISP39_MAIN_SCALE_VY_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x0098)
+#define ISP39_MAIN_SCALE_VC_FAC_SHD (ISP39_MAIN_SCALE_BASE + 0x009c)
+#define ISP39_MAIN_SCALE_HY_OFFS_SHD (ISP39_MAIN_SCALE_BASE + 0x00a0)
+#define ISP39_MAIN_SCALE_HC_OFFS_SHD (ISP39_MAIN_SCALE_BASE + 0x00a4)
+#define ISP39_MAIN_SCALE_PHASE_HY_SHD (ISP39_MAIN_SCALE_BASE + 0x00b0)
+#define ISP39_MAIN_SCALE_PHASE_HC_SHD (ISP39_MAIN_SCALE_BASE + 0x00b4)
+#define ISP39_MAIN_SCALE_PHASE_VY_SHD (ISP39_MAIN_SCALE_BASE + 0x00b8)
+#define ISP39_MAIN_SCALE_PHASE_VC_SHD (ISP39_MAIN_SCALE_BASE + 0x00bc)
+#define ISP39_MAIN_SCALE_HY_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x00c0)
+#define ISP39_MAIN_SCALE_HC_SIZE_SHD (ISP39_MAIN_SCALE_BASE + 0x00c4)
+#define ISP39_MAIN_SCALE_HY_OFFS_MI_SHD (ISP39_MAIN_SCALE_BASE + 0x00c8)
+#define ISP39_MAIN_SCALE_HC_OFFS_MI_SHD (ISP39_MAIN_SCALE_BASE + 0x00cc)
+#define ISP39_MAIN_SCALE_IN_CROP_OFFSET_SHD (ISP39_MAIN_SCALE_BASE + 0x00d0)
+
+#define ISP32_BP_RESIZE_BASE 0x00000E00
+#define ISP32_BP_RESIZE_CTRL (ISP32_BP_RESIZE_BASE + 0x00000)
+#define ISP32_BP_RESIZE_SCALE_HY (ISP32_BP_RESIZE_BASE + 0x00004)
+#define ISP32_BP_RESIZE_SCALE_HCB (ISP32_BP_RESIZE_BASE + 0x00008)
+#define ISP32_BP_RESIZE_SCALE_HCR (ISP32_BP_RESIZE_BASE + 0x0000c)
+#define ISP32_BP_RESIZE_SCALE_VY (ISP32_BP_RESIZE_BASE + 0x00010)
+#define ISP32_BP_RESIZE_SCALE_VC (ISP32_BP_RESIZE_BASE + 0x00014)
+#define ISP32_BP_RESIZE_PHASE_HY (ISP32_BP_RESIZE_BASE + 0x00018)
+#define ISP32_BP_RESIZE_PHASE_HC (ISP32_BP_RESIZE_BASE + 0x0001c)
+#define ISP32_BP_RESIZE_PHASE_VY (ISP32_BP_RESIZE_BASE + 0x00020)
+#define ISP32_BP_RESIZE_PHASE_VC (ISP32_BP_RESIZE_BASE + 0x00024)
+#define ISP32_BP_RESIZE_SCALE_LUT_ADDR (ISP32_BP_RESIZE_BASE + 0x00028)
+#define ISP32_BP_RESIZE_SCALE_LUT (ISP32_BP_RESIZE_BASE + 0x0002c)
+#define ISP32_BP_RESIZE_CTRL_SHD (ISP32_BP_RESIZE_BASE + 0x00030)
+#define ISP32_BP_RESIZE_SCALE_HY_SHD (ISP32_BP_RESIZE_BASE + 0x00034)
+#define ISP32_BP_RESIZE_SCALE_HCB_SHD (ISP32_BP_RESIZE_BASE + 0x00038)
+#define ISP32_BP_RESIZE_SCALE_HCR_SHD (ISP32_BP_RESIZE_BASE + 0x0003c)
+#define ISP32_BP_RESIZE_SCALE_VY_SHD (ISP32_BP_RESIZE_BASE + 0x00040)
+#define ISP32_BP_RESIZE_SCALE_VC_SHD (ISP32_BP_RESIZE_BASE + 0x00044)
+#define ISP32_BP_RESIZE_PHASE_HY_SHD (ISP32_BP_RESIZE_BASE + 0x00048)
+#define ISP32_BP_RESIZE_PHASE_HC_SHD (ISP32_BP_RESIZE_BASE + 0x0004c)
+#define ISP32_BP_RESIZE_PHASE_VY_SHD (ISP32_BP_RESIZE_BASE + 0x00050)
+#define ISP32_BP_RESIZE_PHASE_VC_SHD (ISP32_BP_RESIZE_BASE + 0x00054)
+#define ISP32_BP_RESIZE_HY_SIZE (ISP32_BP_RESIZE_BASE + 0x00058)
+#define ISP32_BP_RESIZE_HC_SIZE (ISP32_BP_RESIZE_BASE + 0x0005c)
+#define ISP32_BP_RESIZE_HY_OFFS_MI (ISP32_BP_RESIZE_BASE + 0x00060)
+#define ISP32_BP_RESIZE_HC_OFFS_MI (ISP32_BP_RESIZE_BASE + 0x00064)
+#define ISP32_BP_RESIZE_HY_SIZE_SHD (ISP32_BP_RESIZE_BASE + 0x00068)
+#define ISP32_BP_RESIZE_HC_SIZE_SHD (ISP32_BP_RESIZE_BASE + 0x0006c)
+#define ISP32_BP_RESIZE_HY_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00070)
+#define ISP32_BP_RESIZE_HC_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00074)
+#define ISP32_BP_RESIZE_IN_CROP_OFFSET (ISP32_BP_RESIZE_BASE + 0x00078)
+
+#define ISP33_BP_SCALE_BASE 0x00000E00
+#define ISP33_BP_SCALE_CTRL (ISP33_BP_SCALE_BASE + 0x0000)
+#define ISP33_BP_SCALE_UPDATE (ISP33_BP_SCALE_BASE + 0x0004)
+#define ISP33_BP_SCALE_SRC_SIZE (ISP33_BP_SCALE_BASE + 0x0008)
+#define ISP33_BP_SCALE_DST_SIZE (ISP33_BP_SCALE_BASE + 0x000c)
+#define ISP33_BP_SCALE_HY_FAC (ISP33_BP_SCALE_BASE + 0x0010)
+#define ISP33_BP_SCALE_HC_FAC (ISP33_BP_SCALE_BASE + 0x0014)
+#define ISP33_BP_SCALE_VY_FAC (ISP33_BP_SCALE_BASE + 0x0018)
+#define ISP33_BP_SCALE_VC_FAC (ISP33_BP_SCALE_BASE + 0x001c)
+#define ISP33_BP_SCALE_HY_OFFS (ISP33_BP_SCALE_BASE + 0x0020)
+#define ISP33_BP_SCALE_HC_OFFS (ISP33_BP_SCALE_BASE + 0x0024)
+#define ISP33_BP_SCALE_VY_OFFS (ISP33_BP_SCALE_BASE + 0x0028)
+#define ISP33_BP_SCALE_HY_SIZE (ISP33_BP_SCALE_BASE + 0x0040)
+#define ISP33_BP_SCALE_HC_SIZE (ISP33_BP_SCALE_BASE + 0x0044)
+#define ISP33_BP_SCALE_HY_OFFS_MI (ISP33_BP_SCALE_BASE + 0x0048)
+#define ISP33_BP_SCALE_HC_OFFS_MI (ISP33_BP_SCALE_BASE + 0x004c)
+#define ISP33_BP_SCALE_IN_CROP_OFFSET (ISP33_BP_SCALE_BASE + 0x0050)
+#define ISP33_BP_SCALE_CTRL_SHD (ISP33_BP_SCALE_BASE + 0x0080)
+#define ISP33_BP_SCALE_SRC_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x0088)
+#define ISP33_BP_SCALE_DST_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x008c)
+#define ISP33_BP_SCALE_HY_FAC_SHD (ISP33_BP_SCALE_BASE + 0x0090)
+#define ISP33_BP_SCALE_HC_FAC_SHD (ISP33_BP_SCALE_BASE + 0x0094)
+#define ISP33_BP_SCALE_VY_FAC_SHD (ISP33_BP_SCALE_BASE + 0x0098)
+#define ISP33_BP_SCALE_VC_FAC_SHD (ISP33_BP_SCALE_BASE + 0x009c)
+#define ISP33_BP_SCALE_HY_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00a0)
+#define ISP33_BP_SCALE_HC_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00a4)
+#define ISP33_BP_SCALE_VY_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00a8)
+#define ISP33_BP_SCALE_VC_OFFS_SHD (ISP33_BP_SCALE_BASE + 0x00ac)
+#define ISP33_BP_SCALE_HY_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x00c0)
+#define ISP33_BP_SCALE_HC_SIZE_SHD (ISP33_BP_SCALE_BASE + 0x00c4)
+#define ISP33_BP_SCALE_HY_OFFS_MI_SHD (ISP33_BP_SCALE_BASE + 0x00c8)
+#define ISP33_BP_SCALE_HC_OFFS_MI_SHD (ISP33_BP_SCALE_BASE + 0x00cc)
+#define ISP33_BP_SCALE_IN_CROP_OFFSET_SHD (ISP33_BP_SCALE_BASE + 0x00d0)
+
+#define ISP3X_SELF_RESIZE_BASE 0x00001000
+#define ISP3X_SELF_RESIZE_CTRL (ISP3X_SELF_RESIZE_BASE + 0x00000)
+#define ISP3X_SELF_RESIZE_SCALE_HY (ISP3X_SELF_RESIZE_BASE + 0x00004)
+#define ISP3X_SELF_RESIZE_SCALE_HCB (ISP3X_SELF_RESIZE_BASE + 0x00008)
+#define ISP3X_SELF_RESIZE_SCALE_HCR (ISP3X_SELF_RESIZE_BASE + 0x0000c)
+#define ISP3X_SELF_RESIZE_SCALE_VY (ISP3X_SELF_RESIZE_BASE + 0x00010)
+#define ISP3X_SELF_RESIZE_SCALE_VC (ISP3X_SELF_RESIZE_BASE + 0x00014)
+#define ISP3X_SELF_RESIZE_PHASE_HY (ISP3X_SELF_RESIZE_BASE + 0x00018)
+#define ISP3X_SELF_RESIZE_PHASE_HC (ISP3X_SELF_RESIZE_BASE + 0x0001c)
+#define ISP3X_SELF_RESIZE_PHASE_VY (ISP3X_SELF_RESIZE_BASE + 0x00020)
+#define ISP3X_SELF_RESIZE_PHASE_VC (ISP3X_SELF_RESIZE_BASE + 0x00024)
+#define ISP3X_SELF_RESIZE_SCALE_LUT_ADDR (ISP3X_SELF_RESIZE_BASE + 0x00028)
+#define ISP3X_SELF_RESIZE_SCALE_LUT (ISP3X_SELF_RESIZE_BASE + 0x0002c)
+#define ISP3X_SELF_RESIZE_CTRL_SHD (ISP3X_SELF_RESIZE_BASE + 0x00030)
+#define ISP3X_SELF_RESIZE_SCALE_HY_SHD (ISP3X_SELF_RESIZE_BASE + 0x00034)
+#define ISP3X_SELF_RESIZE_SCALE_HCB_SHD (ISP3X_SELF_RESIZE_BASE + 0x00038)
+#define ISP3X_SELF_RESIZE_SCALE_HCR_SHD (ISP3X_SELF_RESIZE_BASE + 0x0003c)
+#define ISP3X_SELF_RESIZE_SCALE_VY_SHD (ISP3X_SELF_RESIZE_BASE + 0x00040)
+#define ISP3X_SELF_RESIZE_SCALE_VC_SHD (ISP3X_SELF_RESIZE_BASE + 0x00044)
+#define ISP3X_SELF_RESIZE_PHASE_HY_SHD (ISP3X_SELF_RESIZE_BASE + 0x00048)
+#define ISP3X_SELF_RESIZE_PHASE_HC_SHD (ISP3X_SELF_RESIZE_BASE + 0x0004c)
+#define ISP3X_SELF_RESIZE_PHASE_VY_SHD (ISP3X_SELF_RESIZE_BASE + 0x00050)
+#define ISP3X_SELF_RESIZE_PHASE_VC_SHD (ISP3X_SELF_RESIZE_BASE + 0x00054)
+#define ISP3X_SELF_RESIZE_HY_SIZE (ISP3X_SELF_RESIZE_BASE + 0x00058)
+#define ISP3X_SELF_RESIZE_HC_SIZE (ISP3X_SELF_RESIZE_BASE + 0x0005C)
+#define ISP3X_SELF_RESIZE_HY_OFFS_MI (ISP3X_SELF_RESIZE_BASE + 0x00060)
+#define ISP3X_SELF_RESIZE_HC_OFFS_MI (ISP3X_SELF_RESIZE_BASE + 0x00064)
+#define ISP3X_SELF_RESIZE_HY_SIZE_SHD (ISP3X_SELF_RESIZE_BASE + 0x00068)
+#define ISP3X_SELF_RESIZE_HC_SIZE_SHD (ISP3X_SELF_RESIZE_BASE + 0x0006C)
+#define ISP3X_SELF_RESIZE_HY_OFFS_MI_SHD (ISP3X_SELF_RESIZE_BASE + 0x00070)
+#define ISP3X_SELF_RESIZE_HC_OFFS_MI_SHD (ISP3X_SELF_RESIZE_BASE + 0x00074)
+#define ISP3X_SELF_RESIZE_IN_CROP_OFFSET (ISP3X_SELF_RESIZE_BASE + 0x00078)
+
+#define ISP32_SELF_SCALE_BASE 0x00001000
+#define ISP32_SELF_SCALE_CTRL (ISP32_SELF_SCALE_BASE + 0x0000)
+#define ISP32_SELF_SCALE_UPDATE (ISP32_SELF_SCALE_BASE + 0x0004)
+#define ISP32_SELF_SCALE_SRC_SIZE (ISP32_SELF_SCALE_BASE + 0x0008)
+#define ISP32_SELF_SCALE_DST_SIZE (ISP32_SELF_SCALE_BASE + 0x000c)
+#define ISP32_SELF_SCALE_HY_FAC (ISP32_SELF_SCALE_BASE + 0x0010)
+#define ISP32_SELF_SCALE_HC_FAC (ISP32_SELF_SCALE_BASE + 0x0014)
+#define ISP32_SELF_SCALE_VY_FAC (ISP32_SELF_SCALE_BASE + 0x0018)
+#define ISP32_SELF_SCALE_VC_FAC (ISP32_SELF_SCALE_BASE + 0x001c)
+#define ISP32_SELF_SCALE_HY_OFFS (ISP32_SELF_SCALE_BASE + 0x0020)
+#define ISP32_SELF_SCALE_HC_OFFS (ISP32_SELF_SCALE_BASE + 0x0024)
+#define ISP32_SELF_SCALE_PHASE_HY (ISP32_SELF_SCALE_BASE + 0x0030)
+#define ISP32_SELF_SCALE_PHASE_HC (ISP32_SELF_SCALE_BASE + 0x0034)
+#define ISP32_SELF_SCALE_PHASE_VY (ISP32_SELF_SCALE_BASE + 0x0038)
+#define ISP32_SELF_SCALE_PHASE_VC (ISP32_SELF_SCALE_BASE + 0x003c)
+#define ISP32_SELF_SCALE_HY_SIZE (ISP32_SELF_SCALE_BASE + 0x0040)
+#define ISP32_SELF_SCALE_HC_SIZE (ISP32_SELF_SCALE_BASE + 0x0044)
+#define ISP32_SELF_SCALE_HY_OFFS_MI (ISP32_SELF_SCALE_BASE + 0x0048)
+#define ISP32_SELF_SCALE_HC_OFFS_MI (ISP32_SELF_SCALE_BASE + 0x004c)
+#define ISP32_SELF_SCALE_IN_CROP_OFFSET (ISP32_SELF_SCALE_BASE + 0x0050)
+#define ISP32_SELF_SCALE_CTRL_SHD (ISP32_SELF_SCALE_BASE + 0x0080)
+#define ISP32_SELF_SCALE_SRC_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x0088)
+#define ISP32_SELF_SCALE_DST_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x008c)
+#define ISP32_SELF_SCALE_HY_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x0090)
+#define ISP32_SELF_SCALE_HC_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x0094)
+#define ISP32_SELF_SCALE_VY_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x0098)
+#define ISP32_SELF_SCALE_VC_FAC_SHD (ISP32_SELF_SCALE_BASE + 0x009c)
+#define ISP32_SELF_SCALE_HY_OFFS_SHD (ISP32_SELF_SCALE_BASE + 0x00a0)
+#define ISP32_SELF_SCALE_HC_OFFS_SHD (ISP32_SELF_SCALE_BASE + 0x00a4)
+#define ISP32_SELF_SCALE_PHASE_HY_SHD (ISP32_SELF_SCALE_BASE + 0x00b0)
+#define ISP32_SELF_SCALE_PHASE_HC_SHD (ISP32_SELF_SCALE_BASE + 0x00b4)
+#define ISP32_SELF_SCALE_PHASE_VY_SHD (ISP32_SELF_SCALE_BASE + 0x00b8)
+#define ISP32_SELF_SCALE_PHASE_VC_SHD (ISP32_SELF_SCALE_BASE + 0x00bc)
+#define ISP32_SELF_SCALE_HY_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x00c0)
+#define ISP32_SELF_SCALE_HC_SIZE_SHD (ISP32_SELF_SCALE_BASE + 0x00c4)
+#define ISP32_SELF_SCALE_HY_OFFS_MI_SHD (ISP32_SELF_SCALE_BASE + 0x00c8)
+#define ISP32_SELF_SCALE_HC_OFFS_MI_SHD (ISP32_SELF_SCALE_BASE + 0x00cc)
+#define ISP32_SELF_SCALE_IN_CROP_OFFSET_SHD (ISP32_SELF_SCALE_BASE + 0x00d0)
+
+#define ISP39_LDCV_BASE 0x00001100
+#define ISP39_LDCV_CTRL (ISP39_LDCV_BASE + 0x00000)
+#define ISP39_LDCV_BIC_TABLE0 (ISP39_LDCV_BASE + 0x00004)
+#define ISP39_LDCV_BIC_TABLE1 (ISP39_LDCV_BASE + 0x00008)
+#define ISP39_LDCV_BIC_TABLE2 (ISP39_LDCV_BASE + 0x0000c)
+#define ISP39_LDCV_BIC_TABLE3 (ISP39_LDCV_BASE + 0x00010)
+#define ISP39_LDCV_BIC_TABLE4 (ISP39_LDCV_BASE + 0x00014)
+#define ISP39_LDCV_BIC_TABLE5 (ISP39_LDCV_BASE + 0x00018)
+#define ISP39_LDCV_BIC_TABLE6 (ISP39_LDCV_BASE + 0x0001c)
+#define ISP39_LDCV_BIC_TABLE7 (ISP39_LDCV_BASE + 0x00020)
+#define ISP39_LDCV_BIC_TABLE8 (ISP39_LDCV_BASE + 0x00024)
+#define ISP39_LDCV_WR_ADDR (ISP39_LDCV_BASE + 0x00028)
+#define ISP39_LDCV_WR_STRIDE (ISP39_LDCV_BASE + 0x0002c)
+#define ISP39_LDCV_LAST_OFFSET (ISP39_LDCV_BASE + 0x00030)
+#define ISP39_LDCV_SCL_WR_ADDR (ISP39_LDCV_BASE + 0x00034)
+#define ISP39_LDCV_SCL_WR_STRIDE (ISP39_LDCV_BASE + 0x00038)
+#define ISP39_LDCV_OUT_SIZE (ISP39_LDCV_BASE + 0x0003c)
+#define ISP39_LDCV_WR_C_ADDR (ISP39_LDCV_BASE + 0x00040)
+
+#define ISP35_AI_BASE 0x00001200
+#define ISP35_AI_CTRL (ISP35_AI_BASE + 0x00000)
+#define ISP35_AI_SIGMA_Y0 (ISP35_AI_BASE + 0x00010)
+#define ISP35_AI_SIGMA_Y16 (ISP35_AI_BASE + 0x00050)
+#define ISP35_AI_PRE_NL_WR_BASE (ISP35_AI_BASE + 0x00054)
+#define ISP35_AI_PRE_NL_WR_STRIDE (ISP35_AI_BASE + 0x00058)
+#define ISP35_AI_PRE_GAIN_WR_BASE (ISP35_AI_BASE + 0x0005c)
+#define ISP35_AI_PRE_GAIN_WR_STRIDE (ISP35_AI_BASE + 0x00060)
+#define ISP35_AI_PRE_NL_PRE (ISP35_AI_BASE + 0x00064)
+#define ISP35_AI_PRE_GAIN_PARA (ISP35_AI_BASE + 0x00068)
+#define ISP35_AI_PRE_SIGMA_CURVE0 (ISP35_AI_BASE + 0x0006c)
+#define ISP35_AI_PRE_SIGMA_CURVE10 (ISP35_AI_BASE + 0x00094)
+#define ISP35_AI_PRE_NOISE0 (ISP35_AI_BASE + 0x00098)
+#define ISP35_AI_PRE_NOISE1 (ISP35_AI_BASE + 0x0009c)
+#define ISP35_AI_PRE_NOISE2 (ISP35_AI_BASE + 0x000A0)
+
+#define ISP3X_MI_BASE 0x00001400
+#define ISP3X_MI_WR_CTRL (ISP3X_MI_BASE + 0x00000)
+#define ISP3X_MI_WR_INIT (ISP3X_MI_BASE + 0x00004)
+#define ISP3X_MI_MP_WR_Y_BASE (ISP3X_MI_BASE + 0x00008)
+#define ISP3X_MI_MP_WR_Y_SIZE (ISP3X_MI_BASE + 0x0000c)
+#define ISP3X_MI_MP_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x00010)
+#define ISP3X_MI_MP_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x00014)
+#define ISP3X_MI_MP_WR_Y_IRQ_OFFS (ISP3X_MI_BASE + 0x00018)
+#define ISP3X_MI_MP_WR_CB_BASE (ISP3X_MI_BASE + 0x0001c)
+#define ISP3X_MI_MP_WR_CB_SIZE (ISP3X_MI_BASE + 0x00020)
+#define ISP3X_MI_MP_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x00024)
+#define ISP3X_MI_MP_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x00028)
+#define ISP3X_MI_MP_WR_CR_BASE (ISP3X_MI_BASE + 0x0002c)
+#define ISP3X_MI_MP_WR_CR_SIZE (ISP3X_MI_BASE + 0x00030)
+#define ISP3X_MI_MP_WR_CR_OFFS_CNT (ISP3X_MI_BASE + 0x00034)
+#define ISP3X_MI_MP_WR_CR_OFFS_CNT_START (ISP3X_MI_BASE + 0x00038)
+#define ISP3X_MI_SP_WR_Y_BASE (ISP3X_MI_BASE + 0x0003c)
+#define ISP3X_MI_SP_WR_Y_SIZE (ISP3X_MI_BASE + 0x00040)
+#define ISP3X_MI_SP_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x00044)
+#define ISP3X_MI_SP_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x00048)
+#define ISP3X_MI_SP_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x0004c)
+#define ISP3X_MI_SP_WR_CB_BASE (ISP3X_MI_BASE + 0x00050)
+#define ISP3X_MI_SP_WR_CB_SIZE (ISP3X_MI_BASE + 0x00054)
+#define ISP3X_MI_SP_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x00058)
+#define ISP3X_MI_SP_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x0005c)
+#define ISP3X_MI_SP_WR_CR_BASE (ISP3X_MI_BASE + 0x00060)
+#define ISP3X_MI_SP_WR_CR_SIZE (ISP3X_MI_BASE + 0x00064)
+#define ISP3X_MI_SP_WR_CR_OFFS_CNT (ISP3X_MI_BASE + 0x00068)
+#define ISP3X_MI_SP_WR_CR_OFFS_CNT_START (ISP3X_MI_BASE + 0x0006c)
+#define ISP3X_MI_WR_BYTE_CNT (ISP3X_MI_BASE + 0x00070)
+#define ISP3X_MI_WR_CTRL_SHD (ISP3X_MI_BASE + 0x00074)
+#define ISP3X_MI_MP_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x00078)
+#define ISP3X_MI_MP_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x0007c)
+#define ISP3X_MI_MP_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x00080)
+#define ISP3X_MI_MP_WR_Y_IRQ_OFFS_SHD (ISP3X_MI_BASE + 0x00084)
+#define ISP3X_MI_MP_WR_CB_BASE_SHD (ISP3X_MI_BASE + 0x00088)
+#define ISP3X_MI_MP_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x0008c)
+#define ISP3X_MI_MP_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x00090)
+#define ISP3X_MI_MP_WR_CR_BASE_SHD (ISP3X_MI_BASE + 0x00094)
+#define ISP3X_MI_MP_WR_CR_SIZE_SHD (ISP3X_MI_BASE + 0x00098)
+#define ISP3X_MI_MP_WR_CR_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x0009c)
+#define ISP3X_MI_SP_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x000a0)
+#define ISP3X_MI_SP_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x000a4)
+#define ISP3X_MI_SP_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x000a8)
+#define ISP3X_MI_SP_WR_CB_BASE_AD_SHD (ISP3X_MI_BASE + 0x000b0)
+#define ISP3X_MI_SP_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x000b4)
+#define ISP3X_MI_SP_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x000b8)
+#define ISP3X_MI_SP_WR_CR_BASE_AD_SHD (ISP3X_MI_BASE + 0x000bc)
+#define ISP3X_MI_SP_WR_CR_SIZE_SHD (ISP3X_MI_BASE + 0x000c0)
+#define ISP3X_MI_SP_WR_CR_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x000c4)
+#define ISP3X_MI_IMSC (ISP3X_MI_BASE + 0x000f8)
+#define ISP3X_MI_RIS (ISP3X_MI_BASE + 0x000fc)
+#define ISP3X_MI_MIS (ISP3X_MI_BASE + 0x00100)
+#define ISP3X_MI_ICR (ISP3X_MI_BASE + 0x00104)
+#define ISP3X_MI_ISR (ISP3X_MI_BASE + 0x00108)
+#define ISP3X_MI_STATUS (ISP3X_MI_BASE + 0x0010c)
+#define ISP3X_MI_STATUS_CLR (ISP3X_MI_BASE + 0x00110)
+#define ISP3X_MI_SP_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x00114)
+#define ISP3X_MI_SP_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x00118)
+#define ISP3X_MI_SP_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x0011c)
+#define ISP3X_MI_WR_PIXEL_CNT (ISP3X_MI_BASE + 0x0012c)
+#define ISP3X_MI_MP_WR_Y_BASE2 (ISP3X_MI_BASE + 0x00130)
+#define ISP3X_MI_MP_WR_CB_BASE2 (ISP3X_MI_BASE + 0x00134)
+#define ISP3X_MI_MP_WR_CR_BASE2 (ISP3X_MI_BASE + 0x00138)
+#define ISP3X_MI_SP_WR_Y_BASE2 (ISP3X_MI_BASE + 0x0013C)
+#define ISP3X_MI_SP_WR_CB_BASE2 (ISP3X_MI_BASE + 0x00140)
+#define ISP3X_MI_SP_WR_CR_BASE2 (ISP3X_MI_BASE + 0x00144)
+#define ISP3X_MI_WR_XTD_FORMAT_CTRL (ISP3X_MI_BASE + 0x00148)
+#define ISP3X_MI_WR_ID (ISP3X_MI_BASE + 0x00154)
+#define ISP3X_MI_MP_WR_Y_IRQ_OFFS2 (ISP3X_MI_BASE + 0x001E0)
+#define ISP3X_MI_MP_WR_Y_IRQ_OFFS2_SHD (ISP3X_MI_BASE + 0x001E4)
+#define ISP3X_MI_MP_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x001E8)
+#define ISP3X_MI_MP_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x001EC)
+#define ISP3X_MI_MP_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x001F0)
+#define ISP3X_MI_MP_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x001F4)
+#define ISP32_MI_MP_WR_CTRL (ISP3X_MI_BASE + 0x001F8)
+#define ISP3X_MI_BP_WR_CTRL (ISP3X_MI_BASE + 0x00200)
+#define ISP3X_MI_BP_WR_Y_BASE (ISP3X_MI_BASE + 0x00204)
+#define ISP3X_MI_BP_WR_Y_SIZE (ISP3X_MI_BASE + 0x00208)
+#define ISP3X_MI_BP_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x0020C)
+#define ISP3X_MI_BP_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x00210)
+#define ISP3X_MI_BP_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x00214)
+#define ISP3X_MI_BP_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x00218)
+#define ISP3X_MI_BP_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x0021C)
+#define ISP3X_MI_BP_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x00220)
+#define ISP3X_MI_BP_WR_CB_BASE (ISP3X_MI_BASE + 0x00224)
+#define ISP3X_MI_BP_WR_CB_SIZE (ISP3X_MI_BASE + 0x00228)
+#define ISP3X_MI_BP_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x0022C)
+#define ISP3X_MI_BP_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x00230)
+#define ISP3X_MI_BP_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x00234)
+#define ISP3X_MI_BP_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x00238)
+#define ISP3X_MI_BP_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x0023C)
+#define ISP3X_MI_BP_WR_CB_BASE_SHD (ISP3X_MI_BASE + 0x00240)
+#define ISP3X_MI_BP_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x00244)
+#define ISP3X_MI_BP_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x00248)
+#define ISP3X_MI_BP_WR_Y_BASE2 (ISP3X_MI_BASE + 0x0024C)
+#define ISP3X_MI_BP_WR_CB_BASE2 (ISP3X_MI_BASE + 0x00250)
+#define ISP32_MI_MP_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00260)
+#define ISP32_MI_MP_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x00264)
+#define ISP32_MI_SP_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00268)
+#define ISP32_MI_SP_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x0026c)
+#define ISP32_MI_BP_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00270)
+#define ISP32_MI_BP_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x00274)
+#define ISP32_MI_MPDS_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00278)
+#define ISP32_MI_MPDS_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x0027c)
+#define ISP32_MI_BPDS_WR_Y_END_ADDR (ISP3X_MI_BASE + 0x00280)
+#define ISP32_MI_BPDS_WR_CB_END_ADDR (ISP3X_MI_BASE + 0x00284)
+#define ISP32_MI_MPDS_WR_CTRL (ISP3X_MI_BASE + 0x002a0)
+#define ISP32_MI_MPDS_WR_Y_BASE (ISP3X_MI_BASE + 0x002a4)
+#define ISP32_MI_MPDS_WR_Y_SIZE (ISP3X_MI_BASE + 0x002a8)
+#define ISP32_MI_MPDS_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x002ac)
+#define ISP32_MI_MPDS_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x002b0)
+#define ISP32_MI_MPDS_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x002b4)
+#define ISP32_MI_MPDS_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x002b8)
+#define ISP32_MI_MPDS_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x002bc)
+#define ISP32_MI_MPDS_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x002c0)
+#define ISP32_MI_MPDS_WR_CB_BASE (ISP3X_MI_BASE + 0x002c4)
+#define ISP32_MI_MPDS_WR_CB_SIZE (ISP3X_MI_BASE + 0x002c8)
+#define ISP32_MI_MPDS_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x002cc)
+#define ISP32_MI_MPDS_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x002d0)
+#define ISP32_MI_MPDS_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x002d4)
+#define ISP32_MI_MPDS_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x002d8)
+#define ISP32_MI_MPDS_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x002dc)
+#define ISP32_MI_MPDS_WR_CB_BASE_SHD (ISP3X_MI_BASE + 0x002e0)
+#define ISP32_MI_MPDS_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x002e4)
+#define ISP32_MI_MPDS_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x002e8)
+#define ISP32_MI_BPDS_WR_CTRL (ISP3X_MI_BASE + 0x002f0)
+#define ISP32_MI_BPDS_WR_Y_BASE (ISP3X_MI_BASE + 0x002f4)
+#define ISP32_MI_BPDS_WR_Y_SIZE (ISP3X_MI_BASE + 0x002f8)
+#define ISP32_MI_BPDS_WR_Y_OFFS_CNT (ISP3X_MI_BASE + 0x002fc)
+#define ISP32_MI_BPDS_WR_Y_OFFS_CNT_START (ISP3X_MI_BASE + 0x00300)
+#define ISP32_MI_BPDS_WR_Y_LLENGTH (ISP3X_MI_BASE + 0x00304)
+#define ISP32_MI_BPDS_WR_Y_PIC_WIDTH (ISP3X_MI_BASE + 0x00308)
+#define ISP32_MI_BPDS_WR_Y_PIC_HEIGHT (ISP3X_MI_BASE + 0x0030c)
+#define ISP32_MI_BPDS_WR_Y_PIC_SIZE (ISP3X_MI_BASE + 0x00310)
+#define ISP32_MI_BPDS_WR_CB_BASE (ISP3X_MI_BASE + 0x00314)
+#define ISP32_MI_BPDS_WR_CB_SIZE (ISP3X_MI_BASE + 0x00318)
+#define ISP32_MI_BPDS_WR_CB_OFFS_CNT (ISP3X_MI_BASE + 0x0031c)
+#define ISP32_MI_BPDS_WR_CB_OFFS_CNT_START (ISP3X_MI_BASE + 0x00320)
+#define ISP32_MI_BPDS_WR_Y_BASE_SHD (ISP3X_MI_BASE + 0x00324)
+#define ISP32_MI_BPDS_WR_Y_SIZE_SHD (ISP3X_MI_BASE + 0x00328)
+#define ISP32_MI_BPDS_WR_Y_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x0032c)
+#define ISP32_MI_BPDS_WR_CB_BASE_SHD (ISP3X_MI_BASE + 0x00330)
+#define ISP32_MI_BPDS_WR_CB_SIZE_SHD (ISP3X_MI_BASE + 0x00334)
+#define ISP32_MI_BPDS_WR_CB_OFFS_CNT_SHD (ISP3X_MI_BASE + 0x00338)
+#define ISP3X_MI_WR_CTRL2 (ISP3X_MI_BASE + 0x00400)
+#define ISP3X_MI_WR_ID2 (ISP3X_MI_BASE + 0x00404)
+#define ISP3X_MI_RD_CTRL2 (ISP3X_MI_BASE + 0x00408)
+#define ISP3X_MI_RD_ID (ISP3X_MI_BASE + 0x0040c)
+#define ISP32_MI_WR_CTRL2_SHD (ISP3X_MI_BASE + 0x00410)
+#define ISP32_MI_WR_WRAP_CTRL (ISP3X_MI_BASE + 0x00414)
+#define ISP32_MI_WR_VFLIP_CTRL (ISP3X_MI_BASE + 0x00418)
+#define ISP3X_MI_RAW0_RD_BASE (ISP3X_MI_BASE + 0x00470)
+#define ISP3X_MI_RAW0_RD_LENGTH (ISP3X_MI_BASE + 0x00474)
+#define ISP3X_MI_RAW0_RD_BASE_SHD (ISP3X_MI_BASE + 0x00478)
+#define ISP32_MI_RAW0_RD_SIZE (ISP3X_MI_BASE + 0x0047c)
+#define ISP3X_MI_RAW1_RD_BASE (ISP3X_MI_BASE + 0x00480)
+#define ISP3X_MI_RAW1_RD_LENGTH (ISP3X_MI_BASE + 0x00484)
+#define ISP3X_MI_RAW1_RD_BASE_SHD (ISP3X_MI_BASE + 0x00488)
+#define ISP32_MI_RAW1_RD_SIZE (ISP3X_MI_BASE + 0x0048c)
+#define ISP3X_MI_RAWS_RD_BASE (ISP3X_MI_BASE + 0x00490)
+#define ISP3X_MI_RAWS_RD_LENGTH (ISP3X_MI_BASE + 0x00494)
+#define ISP3X_MI_RAWS_RD_BASE_SHD (ISP3X_MI_BASE + 0x00498)
+#define ISP32_MI_RAWS_RD_SIZE (ISP3X_MI_BASE + 0x0049c)
+#define ISP3X_MI_LUT_CAC_RD_BASE (ISP3X_MI_BASE + 0x00530)
+#define ISP3X_MI_LUT_CAC_RD_H_WSIZE (ISP3X_MI_BASE + 0x00534)
+#define ISP3X_MI_LUT_CAC_RD_V_SIZE (ISP3X_MI_BASE + 0x00538)
+#define ISP3X_MI_LUT_3D_RD_BASE (ISP3X_MI_BASE + 0x00540)
+#define ISP3X_MI_LUT_LSC_RD_BASE (ISP3X_MI_BASE + 0x00544)
+#define ISP3X_MI_LUT_LDCH_RD_BASE (ISP3X_MI_BASE + 0x00548)
+#define ISP3X_MI_LUT_3D_RD_WSIZE (ISP3X_MI_BASE + 0x00550)
+#define ISP3X_MI_LUT_LSC_RD_WSIZE (ISP3X_MI_BASE + 0x00554)
+#define ISP3X_MI_LUT_LDCH_RD_H_WSIZE (ISP3X_MI_BASE + 0x00558)
+#define ISP3X_MI_LUT_LDCH_RD_V_SIZE (ISP3X_MI_BASE + 0x0055C)
+#define ISP3X_MI_DBR_WR_BASE (ISP3X_MI_BASE + 0x00560)
+#define ISP3X_MI_DBR_WR_SIZE (ISP3X_MI_BASE + 0x00564)
+#define ISP39_W3A_WR_SIZE (ISP3X_MI_BASE + 0x00564)
+#define ISP3X_MI_DBR_WR_LENGTH (ISP3X_MI_BASE + 0x00568)
+#define ISP3X_MI_DBR_WR_BASE_SHD (ISP3X_MI_BASE + 0x0056C)
+#define ISP3X_MI_DBR_RD_BASE (ISP3X_MI_BASE + 0x00570)
+#define ISP39_AIISP_RD_BASE (ISP3X_MI_BASE + 0x00570)
+#define ISP3X_MI_DBR_RD_LENGTH (ISP3X_MI_BASE + 0x00574)
+#define ISP3X_MI_DBR_RD_BASE_SHD (ISP3X_MI_BASE + 0x00578)
+#define ISP3X_MI_3A_WR_BASE (ISP3X_MI_BASE + 0x0057C)
+#define ISP3X_MI_GAIN_WR_BASE (ISP3X_MI_BASE + 0x00580)
+#define ISP3X_MI_GAIN_WR_SIZE (ISP3X_MI_BASE + 0x00584)
+#define ISP3X_MI_GAIN_WR_LENGTH (ISP3X_MI_BASE + 0x00588)
+#define ISP3X_MI_GAIN_WR_BASE2 (ISP3X_MI_BASE + 0x0058C)
+#define ISP3X_MI_GAIN_WR_BASE_SHD (ISP3X_MI_BASE + 0x00590)
+#define ISP3X_MI_BAY3D_IIR_WR_BASE (ISP3X_MI_BASE + 0x005A0)
+#define ISP3X_MI_BAY3D_IIR_WR_SIZE (ISP3X_MI_BASE + 0x005A4)
+#define ISP3X_MI_BAY3D_IIR_WR_LENGTH (ISP3X_MI_BASE + 0x005A8)
+#define ISP3X_MI_BAY3D_IIR_WR_BASE_SHD (ISP3X_MI_BASE + 0x005AC)
+#define ISP3X_MI_BAY3D_IIR_RD_BASE (ISP3X_MI_BASE + 0x005B0)
+#define ISP3X_MI_BAY3D_IIR_RD_LENGTH (ISP3X_MI_BASE + 0x005B4)
+#define ISP3X_MI_BAY3D_IIR_RD_BASE_SHD (ISP3X_MI_BASE + 0x005B8)
+#define ISP3X_MI_BAY3D_CUR_WR_BASE (ISP3X_MI_BASE + 0x005C0)
+#define ISP3X_MI_BAY3D_CUR_WR_SIZE (ISP3X_MI_BASE + 0x005C4)
+#define ISP3X_MI_BAY3D_CUR_WR_LENGTH (ISP3X_MI_BASE + 0x005C8)
+#define ISP3X_MI_BAY3D_CUR_WR_BASE_SHD (ISP3X_MI_BASE + 0x005CC)
+#define ISP3X_MI_BAY3D_CUR_RD_BASE (ISP3X_MI_BASE + 0x005D0)
+#define ISP3X_MI_BAY3D_CUR_RD_LENGTH (ISP3X_MI_BASE + 0x005D4)
+#define ISP3X_MI_BAY3D_CUR_RD_BASE_SHD (ISP3X_MI_BASE + 0x005D8)
+#define ISP32_MI_BAY3D_CUR_RD_SIZE (ISP3X_MI_BASE + 0x005DC)
+#define ISP3X_MI_BAY3D_DS_WR_BASE (ISP3X_MI_BASE + 0x005E0)
+#define ISP3X_MI_BAY3D_DS_WR_SIZE (ISP3X_MI_BASE + 0x005E4)
+#define ISP3X_MI_BAY3D_DS_WR_LENGTH (ISP3X_MI_BASE + 0x005E8)
+#define ISP3X_MI_BAY3D_DS_WR_BASE_SHD (ISP3X_MI_BASE + 0x005EC)
+#define ISP3X_MI_BAY3D_DS_RD_BASE (ISP3X_MI_BASE + 0x005F0)
+#define ISP3X_MI_BAY3D_DS_RD_LENGTH (ISP3X_MI_BASE + 0x005F4)
+#define ISP3X_MI_BAY3D_DS_RD_BASE_SHD (ISP3X_MI_BASE + 0x005F8)
+#define ISP32L_IRLDCH_RD_BASE (ISP3X_MI_BASE + 0x00600)
+#define ISP32L_IRLDCH_RD_LENGTH (ISP3X_MI_BASE + 0x00604)
+#define ISP32L_IRLDCH_RD_H_WSIZE (ISP3X_MI_BASE + 0x00608)
+#define ISP32L_IRLDCH_RD_V_SIZE (ISP3X_MI_BASE + 0x0060C)
+#define ISP32L_IRLDCV_RD_BASE (ISP3X_MI_BASE + 0x00610)
+#define ISP32L_IRLDCV_RD_LENGTH (ISP3X_MI_BASE + 0x00614)
+#define ISP32L_IRLDCV_RD_H_WSIZE (ISP3X_MI_BASE + 0x00618)
+#define ISP32L_IRLDCV_RD_V_SIZE (ISP3X_MI_BASE + 0x0061C)
+#define ISP32L_IRLDCH_RD_BASE_SHD (ISP3X_MI_BASE + 0x00620)
+#define ISP32L_IRLDCV_RD_BASE_SHD (ISP3X_MI_BASE + 0x00624)
+#define ISP32L_AXI_CONF_RD_CTRL (ISP3X_MI_BASE + 0x00640)
+#define ISP32L_AXI_CONF_RD_BASE (ISP3X_MI_BASE + 0x00644)
+#define ISP32L_AXI_CONF_RD_H_WSIZE (ISP3X_MI_BASE + 0x00648)
+#define ISP32L_AXI_CONF_RD_V_SIZE (ISP3X_MI_BASE + 0x0064C)
+#define ISP32L_FRM_BUF_WR_BASE (ISP3X_MI_BASE + 0x00650)
+#define ISP32L_FRM_BUF_WR_SIZE (ISP3X_MI_BASE + 0x00654)
+#define ISP32L_FRM_BUF_RD_BASE (ISP3X_MI_BASE + 0x00658)
+#define ISP35_B3DLDCH_RD_BASE (ISP3X_MI_BASE + 0x00600)
+#define ISP35_B3DLDCH_RD_LENGTH (ISP3X_MI_BASE + 0x00604)
+#define ISP35_B3DLDCH_RD_HWSIZE (ISP3X_MI_BASE + 0x00608)
+#define ISP35_B3DLDCH_RD_VSIZE (ISP3X_MI_BASE + 0x0060c)
+#define ISP35_B3DLDCH_RD_BASE_SHD (ISP3X_MI_BASE + 0x00620)
+#define ISP35_B3DLDCV_RD_BASE_SHD (ISP3X_MI_BASE + 0x00628)
+#define ISP35_B3DLDCV_RD_BASE (ISP3X_MI_BASE + 0x00630)
+#define ISP35_B3DLDCV_RD_LENGTH (ISP3X_MI_BASE + 0x00634)
+#define ISP35_B3DLDCV_RD_HWSIZE (ISP3X_MI_BASE + 0x00638)
+#define ISP35_B3DLDCV_RD_VSIZE (ISP3X_MI_BASE + 0x0063C)
+
+#define ISP3X_MPFBC_BASE 0x000018C0
+#define ISP3X_MPFBC_CTRL (ISP3X_MPFBC_BASE + 0x00000)
+#define ISP3X_MPFBC_VIR_WIDTH (ISP3X_MPFBC_BASE + 0x00004)
+#define ISP3X_MPFBC_VIR_HEIGHT (ISP3X_MPFBC_BASE + 0x00008)
+#define ISP3X_MPFBC_HEAD_PTR (ISP3X_MPFBC_BASE + 0x0000c)
+#define ISP3X_MPFBC_PAYL_PTR (ISP3X_MPFBC_BASE + 0x00010)
+#define ISP3X_MPFBC_HEAD_PTR2 (ISP3X_MPFBC_BASE + 0x00014)
+#define ISP3X_MPFBC_PAYL_PTR2 (ISP3X_MPFBC_BASE + 0x00018)
+#define ISP3X_MPFBC_PAYL_WIDTH (ISP3X_MPFBC_BASE + 0x0001c)
+#define ISP3X_MPFBC_HEAD_OFFSET (ISP3X_MPFBC_BASE + 0x00020)
+#define ISP3X_MPFBC_ENC_POS (ISP3X_MPFBC_BASE + 0x00030)
+#define ISP3X_MPFBC_DEBUG (ISP3X_MPFBC_BASE + 0x00034)
+
+#define ISP3X_CSI2RX_BASE 0x00001C00
+#define ISP3X_CSI2RX_CTRL0 (ISP3X_CSI2RX_BASE + 0x00000)
+#define ISP3X_CSI2RX_CTRL1 (ISP3X_CSI2RX_BASE + 0x00004)
+#define ISP3X_CSI2RX_CTRL2 (ISP3X_CSI2RX_BASE + 0x00008)
+#define ISP32_CSI2RX_CTRL3 (ISP3X_CSI2RX_BASE + 0x0000c)
+#define ISP3X_CSI2RX_CSI2_RESETN (ISP3X_CSI2RX_BASE + 0x00010)
+#define ISP3X_CSI2RX_PHY_STATE_RO (ISP3X_CSI2RX_BASE + 0x00014)
+#define ISP3X_CSI2RX_DATA_IDS_1 (ISP3X_CSI2RX_BASE + 0x00018)
+#define ISP3X_CSI2RX_DATA_IDS_2 (ISP3X_CSI2RX_BASE + 0x0001c)
+#define ISP3X_CSI2RX_ERR_PHY (ISP3X_CSI2RX_BASE + 0x00020)
+#define ISP3X_CSI2RX_ERR_PACKET (ISP3X_CSI2RX_BASE + 0x00024)
+#define ISP3X_CSI2RX_ERR_OVERFLOW (ISP3X_CSI2RX_BASE + 0x00028)
+#define ISP3X_CSI2RX_ERR_STAT (ISP3X_CSI2RX_BASE + 0x0002c)
+#define ISP3X_CSI2RX_MASK_PHY (ISP3X_CSI2RX_BASE + 0x00030)
+#define ISP3X_CSI2RX_MASK_PACKET (ISP3X_CSI2RX_BASE + 0x00034)
+#define ISP3X_CSI2RX_MASK_OVERFLOW (ISP3X_CSI2RX_BASE + 0x00038)
+#define ISP3X_CSI2RX_MASK_STAT (ISP3X_CSI2RX_BASE + 0x0003c)
+#define ISP3X_CSI2RX_RAW_RD_CTRL (ISP3X_CSI2RX_BASE + 0x00080)
+#define ISP3X_CSI2RX_RAW_RD_LINECNT_RO (ISP3X_CSI2RX_BASE + 0x00084)
+#define ISP3X_CSI2RX_RAW_RD_PIC_SIZE (ISP3X_CSI2RX_BASE + 0x00088)
+#define ISP3X_CSI2RX_RAW2_RD_LINECNT_RO (ISP3X_CSI2RX_BASE + 0x0008c)
+#define ISP3X_CSI2RX_ISP_LINECNT_RO (ISP3X_CSI2RX_BASE + 0x000b0)
+#define ISP3X_CSI2RX_VERSION (ISP3X_CSI2RX_BASE + 0x000fc)
+
+#define ISP39_YUVME_BASE 0x00002100
+#define ISP39_YUVME_CTRL (ISP39_YUVME_BASE + 0x00000)
+#define ISP39_YUVME_PARA0 (ISP39_YUVME_BASE + 0x00004)
+#define ISP39_YUVME_PARA1 (ISP39_YUVME_BASE + 0x00008)
+#define ISP39_YUVME_PARA2 (ISP39_YUVME_BASE + 0x0000c)
+#define ISP39_YUVME_SIGMA0 (ISP39_YUVME_BASE + 0x00010)
+#define ISP39_YUVME_SIGMA1 (ISP39_YUVME_BASE + 0x00014)
+#define ISP39_YUVME_SIGMA2 (ISP39_YUVME_BASE + 0x00018)
+#define ISP39_YUVME_SIGMA3 (ISP39_YUVME_BASE + 0x0001c)
+#define ISP39_YUVME_SIGMA4 (ISP39_YUVME_BASE + 0x00020)
+#define ISP39_YUVME_SIGMA5 (ISP39_YUVME_BASE + 0x00024)
+
+#define ISP3X_LSC_BASE 0x00002200
+#define ISP3X_LSC_CTRL (ISP3X_LSC_BASE + 0x00000)
+#define ISP3X_LSC_R_TABLE_ADDR (ISP3X_LSC_BASE + 0x00004)
+#define ISP3X_LSC_GR_TABLE_ADDR (ISP3X_LSC_BASE + 0x00008)
+#define ISP3X_LSC_B_TABLE_ADDR (ISP3X_LSC_BASE + 0x0000c)
+#define ISP3X_LSC_GB_TABLE_ADDR (ISP3X_LSC_BASE + 0x00010)
+#define ISP3X_LSC_R_TABLE_DATA (ISP3X_LSC_BASE + 0x00014)
+#define ISP3X_LSC_GR_TABLE_DATA (ISP3X_LSC_BASE + 0x00018)
+#define ISP3X_LSC_B_TABLE_DATA (ISP3X_LSC_BASE + 0x0001c)
+#define ISP3X_LSC_GB_TABLE_DATA (ISP3X_LSC_BASE + 0x00020)
+#define ISP3X_LSC_XGRAD_01 (ISP3X_LSC_BASE + 0x00024)
+#define ISP3X_LSC_XGRAD_23 (ISP3X_LSC_BASE + 0x00028)
+#define ISP3X_LSC_XGRAD_45 (ISP3X_LSC_BASE + 0x0002c)
+#define ISP3X_LSC_XGRAD_67 (ISP3X_LSC_BASE + 0x00030)
+#define ISP3X_LSC_YGRAD_01 (ISP3X_LSC_BASE + 0x00034)
+#define ISP3X_LSC_YGRAD_23 (ISP3X_LSC_BASE + 0x00038)
+#define ISP3X_LSC_YGRAD_45 (ISP3X_LSC_BASE + 0x0003c)
+#define ISP3X_LSC_YGRAD_67 (ISP3X_LSC_BASE + 0x00040)
+#define ISP3X_LSC_XSIZE_01 (ISP3X_LSC_BASE + 0x00044)
+#define ISP3X_LSC_XSIZE_23 (ISP3X_LSC_BASE + 0x00048)
+#define ISP3X_LSC_XSIZE_45 (ISP3X_LSC_BASE + 0x0004c)
+#define ISP3X_LSC_XSIZE_67 (ISP3X_LSC_BASE + 0x00050)
+#define ISP3X_LSC_YSIZE_01 (ISP3X_LSC_BASE + 0x00054)
+#define ISP3X_LSC_YSIZE_23 (ISP3X_LSC_BASE + 0x00058)
+#define ISP3X_LSC_YSIZE_45 (ISP3X_LSC_BASE + 0x0005c)
+#define ISP3X_LSC_YSIZE_67 (ISP3X_LSC_BASE + 0x00060)
+#define ISP3X_LSC_TABLE_SEL (ISP3X_LSC_BASE + 0x00064)
+#define ISP3X_LSC_STATUS (ISP3X_LSC_BASE + 0x00068)
+#define ISP3X_LSC_XGRAD_89 (ISP3X_LSC_BASE + 0x00070)
+#define ISP3X_LSC_XGRAD_AB (ISP3X_LSC_BASE + 0x00074)
+#define ISP3X_LSC_XGRAD_CD (ISP3X_LSC_BASE + 0x00078)
+#define ISP3X_LSC_XGRAD_EF (ISP3X_LSC_BASE + 0x0007C)
+#define ISP3X_LSC_YGRAD_89 (ISP3X_LSC_BASE + 0x00080)
+#define ISP3X_LSC_YGRAD_AB (ISP3X_LSC_BASE + 0x00084)
+#define ISP3X_LSC_YGRAD_CD (ISP3X_LSC_BASE + 0x00088)
+#define ISP3X_LSC_YGRAD_EF (ISP3X_LSC_BASE + 0x0008C)
+#define ISP3X_LSC_XSIZE_89 (ISP3X_LSC_BASE + 0x00090)
+#define ISP3X_LSC_XSIZE_AB (ISP3X_LSC_BASE + 0x00094)
+#define ISP3X_LSC_XSIZE_CD (ISP3X_LSC_BASE + 0x00098)
+#define ISP3X_LSC_XSIZE_EF (ISP3X_LSC_BASE + 0x0009C)
+#define ISP3X_LSC_YSIZE_89 (ISP3X_LSC_BASE + 0x000A0)
+#define ISP3X_LSC_YSIZE_AB (ISP3X_LSC_BASE + 0x000A4)
+#define ISP3X_LSC_YSIZE_CD (ISP3X_LSC_BASE + 0x000A8)
+#define ISP3X_LSC_YSIZE_EF (ISP3X_LSC_BASE + 0x000AC)
+
+#define ISP3X_DEBAYER_BASE 0x00002500
+#define ISP3X_DEBAYER_CONTROL (ISP3X_DEBAYER_BASE + 0x00000)
+#define ISP3X_DEBAYER_G_INTERP (ISP3X_DEBAYER_BASE + 0x00004)
+#define ISP3X_DEBAYER_G_INTERP_FILTER1 (ISP3X_DEBAYER_BASE + 0x00008)
+#define ISP3X_DEBAYER_G_INTERP_FILTER2 (ISP3X_DEBAYER_BASE + 0x0000c)
+#define ISP3X_DEBAYER_OFFSET (ISP3X_DEBAYER_BASE + 0x00010)
+#define ISP3X_DEBAYER_C_FILTER (ISP3X_DEBAYER_BASE + 0x00014)
+#define ISP32_DEBAYER_G_INTERP_OFFSET (ISP3X_DEBAYER_BASE + 0x00010)
+#define ISP32_DEBAYER_G_FILTER_OFFSET (ISP3X_DEBAYER_BASE + 0x00014)
+#define ISP32_DEBAYER_C_FILTER_GUIDE_GAUS (ISP3X_DEBAYER_BASE + 0x00018)
+#define ISP32_DEBAYER_C_FILTER_CE_GAUS (ISP3X_DEBAYER_BASE + 0x0001c)
+#define ISP32_DEBAYER_C_FILTER_ALPHA_GAUS (ISP3X_DEBAYER_BASE + 0x00020)
+#define ISP32_DEBAYER_C_FILTER_LOG_OFFSET (ISP3X_DEBAYER_BASE + 0x00024)
+#define ISP32_DEBAYER_C_FILTER_ALPHA (ISP3X_DEBAYER_BASE + 0x00028)
+#define ISP32_DEBAYER_C_FILTER_EDGE (ISP3X_DEBAYER_BASE + 0x0002c)
+#define ISP32_DEBAYER_C_FILTER_IIR_0 (ISP3X_DEBAYER_BASE + 0x00030)
+#define ISP32_DEBAYER_C_FILTER_IIR_1 (ISP3X_DEBAYER_BASE + 0x00034)
+#define ISP32_DEBAYER_C_FILTER_BF (ISP3X_DEBAYER_BASE + 0x00038)
+#define ISP39_DEBAYER_LUMA_DX (ISP3X_DEBAYER_BASE + 0x00004)
+#define ISP39_DEBAYER_G_INTERP (ISP3X_DEBAYER_BASE + 0x00010)
+#define ISP39_DEBAYER_G_INTERP_FILTER1 (ISP3X_DEBAYER_BASE + 0x00014)
+#define ISP39_DEBAYER_G_INTERP_FILTER2 (ISP3X_DEBAYER_BASE + 0x00018)
+#define ISP39_DEBAYER_G_INTERP_OFFSET_ALPHA (ISP3X_DEBAYER_BASE + 0x0001c)
+#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET0 (ISP3X_DEBAYER_BASE + 0x00020)
+#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET1 (ISP3X_DEBAYER_BASE + 0x00024)
+#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET2 (ISP3X_DEBAYER_BASE + 0x00028)
+#define ISP39_DEBAYER_G_INTERP_DRCT_OFFSET3 (ISP3X_DEBAYER_BASE + 0x0002c)
+#define ISP39_DEBAYER_G_FILTER_MODE_OFFSET (ISP3X_DEBAYER_BASE + 0x00050)
+#define ISP39_DEBAYER_G_FILTER_FILTER (ISP3X_DEBAYER_BASE + 0x00054)
+#define ISP39_DEBAYER_G_FILTER_VSIGMA0 (ISP3X_DEBAYER_BASE + 0x00058)
+#define ISP39_DEBAYER_G_FILTER_VSIGMA1 (ISP3X_DEBAYER_BASE + 0x0005c)
+#define ISP39_DEBAYER_G_FILTER_VSIGMA2 (ISP3X_DEBAYER_BASE + 0x00060)
+#define ISP39_DEBAYER_G_FILTER_VSIGMA3 (ISP3X_DEBAYER_BASE + 0x00064)
+#define ISP39_DEBAYER_C_FILTER_GUIDE_GAUS (ISP3X_DEBAYER_BASE + 0x00070)
+#define ISP39_DEBAYER_C_FILTER_CE_GAUS (ISP3X_DEBAYER_BASE + 0x00074)
+#define ISP39_DEBAYER_C_FILTER_ALPHA_GAUS (ISP3X_DEBAYER_BASE + 0x00078)
+#define ISP39_DEBAYER_C_FILTER_LOG_OFFSET (ISP3X_DEBAYER_BASE + 0x0007c)
+#define ISP39_DEBAYER_C_FILTER_ALPHA (ISP3X_DEBAYER_BASE + 0x00080)
+#define ISP39_DEBAYER_C_FILTER_EDGE (ISP3X_DEBAYER_BASE + 0x00084)
+#define ISP39_DEBAYER_C_FILTER_IIR_0 (ISP3X_DEBAYER_BASE + 0x00088)
+#define ISP39_DEBAYER_C_FILTER_IIR_1 (ISP3X_DEBAYER_BASE + 0x0008c)
+#define ISP39_DEBAYER_C_FILTER_BF (ISP3X_DEBAYER_BASE + 0x00090)
+
+#define ISP3X_CAC_BASE 0x00002600
+#define ISP3X_CAC_CTRL (ISP3X_CAC_BASE + 0x00000)
+#define ISP3X_CAC_PSF_PARA (ISP3X_CAC_BASE + 0x00004)
+#define ISP3X_CAC_STRENGTH_CENTER (ISP3X_CAC_BASE + 0x00008)
+#define ISP3X_CAC_STRENGTH0 (ISP3X_CAC_BASE + 0x0000C)
+#define ISP3X_CAC_STRENGTH1 (ISP3X_CAC_BASE + 0x00010)
+#define ISP3X_CAC_STRENGTH2 (ISP3X_CAC_BASE + 0x00014)
+#define ISP3X_CAC_STRENGTH3 (ISP3X_CAC_BASE + 0x00018)
+#define ISP3X_CAC_STRENGTH4 (ISP3X_CAC_BASE + 0x0001C)
+#define ISP3X_CAC_STRENGTH5 (ISP3X_CAC_BASE + 0x00020)
+#define ISP3X_CAC_STRENGTH6 (ISP3X_CAC_BASE + 0x00024)
+#define ISP3X_CAC_STRENGTH7 (ISP3X_CAC_BASE + 0x00028)
+#define ISP3X_CAC_STRENGTH8 (ISP3X_CAC_BASE + 0x0002C)
+#define ISP3X_CAC_STRENGTH9 (ISP3X_CAC_BASE + 0x00030)
+#define ISP3X_CAC_STRENGTH10 (ISP3X_CAC_BASE + 0x00034)
+#define ISP32_CAC_FLAT_THED (ISP3X_CAC_BASE + 0x00038)
+#define ISP32_CAC_OFFSET (ISP3X_CAC_BASE + 0x0003c)
+#define ISP3X_CAC_PSF_CFG0 (ISP3X_CAC_BASE + 0x00040)
+#define ISP3X_CAC_PSF_CFG1 (ISP3X_CAC_BASE + 0x00044)
+#define ISP3X_CAC_PSF_CFG2 (ISP3X_CAC_BASE + 0x00048)
+#define ISP3X_CAC_PSF_CFG3 (ISP3X_CAC_BASE + 0x0004C)
+#define ISP3X_CAC_PSF_CFG4 (ISP3X_CAC_BASE + 0x00050)
+#define ISP3X_CAC_PSF_CFG5 (ISP3X_CAC_BASE + 0x00054)
+#define ISP3X_CAC_PSF_CFG6 (ISP3X_CAC_BASE + 0x00058)
+#define ISP3X_CAC_PSF_CFG7 (ISP3X_CAC_BASE + 0x0005C)
+#define ISP3X_CAC_PSF_CFG8 (ISP3X_CAC_BASE + 0x00060)
+#define ISP3X_CAC_PSF_CFG9 (ISP3X_CAC_BASE + 0x00064)
+#define ISP3X_CAC_PSF_CFG10 (ISP3X_CAC_BASE + 0x00068)
+#define ISP3X_CAC_PSF_CFG11 (ISP3X_CAC_BASE + 0x0006C)
+#define ISP3X_CAC_PSF_CFG12 (ISP3X_CAC_BASE + 0x00070)
+#define ISP3X_CAC_PSF_CFG13 (ISP3X_CAC_BASE + 0x00074)
+#define ISP3X_CAC_PSF_CFG14 (ISP3X_CAC_BASE + 0x00078)
+#define ISP3X_CAC_PSF_CFG15 (ISP3X_CAC_BASE + 0x0007C)
+#define ISP3X_CAC_RO_CNT (ISP3X_CAC_BASE + 0x00080)
+#define ISP32_CAC_EXPO_THED_B (ISP3X_CAC_BASE + 0x00080)
+#define ISP32_CAC_EXPO_THED_R (ISP3X_CAC_BASE + 0x00084)
+#define ISP32_CAC_EXPO_ADJ_B (ISP3X_CAC_BASE + 0x00088)
+#define ISP32_CAC_EXPO_ADJ_R (ISP3X_CAC_BASE + 0x0008c)
+#define ISP32_CAC_RO_CNT (ISP3X_CAC_BASE + 0x000fc)
+#define ISP33_CAC_HIGH_DIRECT (ISP3X_CAC_BASE + 0x00008)
+#define ISP33_CAC_OVER_EXPO0 (ISP3X_CAC_BASE + 0x0000c)
+#define ISP33_CAC_OVER_EXPO1 (ISP3X_CAC_BASE + 0x00010)
+#define ISP33_CAC_FLAT (ISP3X_CAC_BASE + 0x00014)
+#define ISP33_CAC_GAUSS_COEFF (ISP3X_CAC_BASE + 0x00018)
+#define ISP33_CAC_RATIO (ISP3X_CAC_BASE + 0x0001c)
+#define ISP33_CAC_WGT_COLOR_B (ISP3X_CAC_BASE + 0x00020)
+#define ISP33_CAC_WGT_COLOR_R (ISP3X_CAC_BASE + 0x00024)
+#define ISP33_CAC_WGT_COLOR_SLOPE_B (ISP3X_CAC_BASE + 0x00028)
+#define ISP33_CAC_WGT_COLOR_SLOPE_R (ISP3X_CAC_BASE + 0x0002c)
+#define ISP33_CAC_WGT_COLOR_LUMA0 (ISP3X_CAC_BASE + 0x00030)
+#define ISP33_CAC_WGT_COLOR_LUMA1 (ISP3X_CAC_BASE + 0x00034)
+#define ISP33_CAC_WGT_OVER_EXPO0 (ISP3X_CAC_BASE + 0x00038)
+#define ISP33_CAC_WGT_OVER_EXPO1 (ISP3X_CAC_BASE + 0x0003c)
+#define ISP33_CAC_WGT_CONTRAST0 (ISP3X_CAC_BASE + 0x00040)
+#define ISP33_CAC_WGT_CONTRAST1 (ISP3X_CAC_BASE + 0x00044)
+#define ISP33_CAC_WGT_CONTRAST2 (ISP3X_CAC_BASE + 0x00048)
+#define ISP33_CAC_WGT_DARK_AREA0 (ISP3X_CAC_BASE + 0x0004c)
+#define ISP33_CAC_WGT_DARK_AREA1 (ISP3X_CAC_BASE + 0x00050)
+#define ISP33_CAC_PSF_B0 (ISP3X_CAC_BASE + 0x00054)
+#define ISP33_CAC_PSF_B2 (ISP3X_CAC_BASE + 0x0005c)
+#define ISP33_CAC_PSF_R0 (ISP3X_CAC_BASE + 0x00060)
+#define ISP33_CAC_PSF_R2 (ISP3X_CAC_BASE + 0x00068)
+#define ISP33_CAC_RO_CNT (ISP3X_CAC_BASE + 0x000f8)
+#define ISP33_CAC_DEBUG (ISP3X_CAC_BASE + 0x000fc)
+
+#define ISP3X_YNR_BASE 0x00002700
+#define ISP3X_YNR_GLOBAL_CTRL (ISP3X_YNR_BASE + 0x00000)
+#define ISP3X_YNR_RNR_MAX_R (ISP3X_YNR_BASE + 0x00004)
+#define ISP3X_YNR_RNR_CENTER_COOR (ISP3X_YNR_BASE + 0x00008)
+#define ISP3X_YNR_LOCAL_GAIN_CTRL (ISP3X_YNR_BASE + 0x0000C)
+#define ISP3X_YNR_LOWNR_CTRL0 (ISP3X_YNR_BASE + 0x00010)
+#define ISP3X_YNR_LOWNR_CTRL1 (ISP3X_YNR_BASE + 0x00014)
+#define ISP3X_YNR_LOWNR_CTRL2 (ISP3X_YNR_BASE + 0x00018)
+#define ISP3X_YNR_LOWNR_CTRL3 (ISP3X_YNR_BASE + 0x0001c)
+#define ISP3X_YNR_HIGHNR_CTRL0 (ISP3X_YNR_BASE + 0x00020)
+#define ISP3X_YNR_HIGHNR_CTRL1 (ISP3X_YNR_BASE + 0x00024)
+#define ISP3X_YNR_HIGHNR_BASE_FILTER_WEIGHT (ISP3X_YNR_BASE + 0x00028)
+#define ISP3X_YNR_LOWNR_CTRL4 (ISP3X_YNR_BASE + 0x0002c)
+#define ISP3X_YNR_GAUSS1_COEFF (ISP3X_YNR_BASE + 0x00030)
+#define ISP3X_YNR_GAUSS2_COEFF (ISP3X_YNR_BASE + 0x00034)
+#define ISP3X_YNR_DIRECTION_W_0_3 (ISP3X_YNR_BASE + 0x00038)
+#define ISP3X_YNR_DIRECTION_W_4_7 (ISP3X_YNR_BASE + 0x0003c)
+#define ISP3X_YNR_SGM_DX_0_1 (ISP3X_YNR_BASE + 0x00040)
+#define ISP3X_YNR_SGM_DX_2_3 (ISP3X_YNR_BASE + 0x00044)
+#define ISP3X_YNR_SGM_DX_4_5 (ISP3X_YNR_BASE + 0x00048)
+#define ISP3X_YNR_SGM_DX_6_7 (ISP3X_YNR_BASE + 0x0004c)
+#define ISP3X_YNR_SGM_DX_8_9 (ISP3X_YNR_BASE + 0x00050)
+#define ISP3X_YNR_SGM_DX_10_11 (ISP3X_YNR_BASE + 0x00055)
+#define ISP3X_YNR_SGM_DX_12_13 (ISP3X_YNR_BASE + 0x00058)
+#define ISP3X_YNR_SGM_DX_14_15 (ISP3X_YNR_BASE + 0x0005c)
+#define ISP3X_YNR_SGM_DX_16 (ISP3X_YNR_BASE + 0x00060)
+#define ISP3X_YNR_LSGM_Y_0_1 (ISP3X_YNR_BASE + 0x00070)
+#define ISP3X_YNR_LSGM_Y_2_3 (ISP3X_YNR_BASE + 0x00074)
+#define ISP3X_YNR_LSGM_Y_4_5 (ISP3X_YNR_BASE + 0x00078)
+#define ISP3X_YNR_LSGM_Y_6_7 (ISP3X_YNR_BASE + 0x0007c)
+#define ISP3X_YNR_LSGM_Y_8_9 (ISP3X_YNR_BASE + 0x00080)
+#define ISP3X_YNR_LSGM_Y_10_11 (ISP3X_YNR_BASE + 0x00084)
+#define ISP3X_YNR_LSGM_Y_12_13 (ISP3X_YNR_BASE + 0x00088)
+#define ISP3X_YNR_LSGM_Y_14_15 (ISP3X_YNR_BASE + 0x0008c)
+#define ISP3X_YNR_LSGM_Y_16 (ISP3X_YNR_BASE + 0x00090)
+#define ISP3X_YNR_HSGM_Y_0_1 (ISP3X_YNR_BASE + 0x000a0)
+#define ISP3X_YNR_HSGM_Y_2_3 (ISP3X_YNR_BASE + 0x000a4)
+#define ISP3X_YNR_HSGM_Y_4_5 (ISP3X_YNR_BASE + 0x000a8)
+#define ISP3X_YNR_HSGM_Y_6_7 (ISP3X_YNR_BASE + 0x000ac)
+#define ISP3X_YNR_HSGM_Y_8_9 (ISP3X_YNR_BASE + 0x000b0)
+#define ISP3X_YNR_HSGM_Y_10_11 (ISP3X_YNR_BASE + 0x000b4)
+#define ISP3X_YNR_HSGM_Y_12_13 (ISP3X_YNR_BASE + 0x000b8)
+#define ISP3X_YNR_HSGM_Y_14_15 (ISP3X_YNR_BASE + 0x000bc)
+#define ISP3X_YNR_HSGM_Y_16 (ISP3X_YNR_BASE + 0x000c0)
+#define ISP3X_YNR_RNR_STRENGTH03 (ISP3X_YNR_BASE + 0x000d0)
+#define ISP3X_YNR_RNR_STRENGTH47 (ISP3X_YNR_BASE + 0x000d4)
+#define ISP3X_YNR_RNR_STRENGTH8B (ISP3X_YNR_BASE + 0x000d8)
+#define ISP3X_YNR_RNR_STRENGTHCF (ISP3X_YNR_BASE + 0x000dc)
+#define ISP3X_YNR_RNR_STRENGTH16 (ISP3X_YNR_BASE + 0x000e0)
+#define ISP32_YNR_NLM_SIGMA_GAIN (ISP3X_YNR_BASE + 0x000f0)
+#define ISP32_YNR_NLM_COE (ISP3X_YNR_BASE + 0x000f4)
+#define ISP32_YNR_NLM_WEIGHT (ISP3X_YNR_BASE + 0x000f8)
+#define ISP32_YNR_NLM_NR_WEIGHT (ISP3X_YNR_BASE + 0x000fc)
+#define ISP39_YNR_GAUSS_COEFF (ISP3X_YNR_BASE + 0x00030)
+#define ISP39_YNR_LOW_GAIN_ADJ_0_3 (ISP3X_YNR_BASE + 0x00034)
+#define ISP39_YNR_LOW_GAIN_ADJ_4_7 (ISP3X_YNR_BASE + 0x00038)
+#define ISP39_YNR_LOW_GAIN_ADJ_8 (ISP3X_YNR_BASE + 0x0003C)
+#define ISP39_YNR_SGM_DX_0_1 (ISP3X_YNR_BASE + 0x00040)
+#define ISP39_YNR_SGM_DX_2_3 (ISP3X_YNR_BASE + 0x00044)
+#define ISP39_YNR_SGM_DX_4_5 (ISP3X_YNR_BASE + 0x00048)
+#define ISP39_YNR_SGM_DX_6_7 (ISP3X_YNR_BASE + 0x0004c)
+#define ISP39_YNR_SGM_DX_8_9 (ISP3X_YNR_BASE + 0x00050)
+#define ISP39_YNR_SGM_DX_10_11 (ISP3X_YNR_BASE + 0x00054)
+#define ISP39_YNR_SGM_DX_12_13 (ISP3X_YNR_BASE + 0x00058)
+#define ISP39_YNR_SGM_DX_14_15 (ISP3X_YNR_BASE + 0x0005c)
+#define ISP39_YNR_SGM_DX_16 (ISP3X_YNR_BASE + 0x00060)
+#define ISP39_YNR_LSGM_Y_0_1 (ISP3X_YNR_BASE + 0x00070)
+#define ISP39_YNR_LSGM_Y_2_3 (ISP3X_YNR_BASE + 0x00074)
+#define ISP39_YNR_LSGM_Y_4_5 (ISP3X_YNR_BASE + 0x00078)
+#define ISP39_YNR_LSGM_Y_6_7 (ISP3X_YNR_BASE + 0x0007c)
+#define ISP39_YNR_LSGM_Y_8_9 (ISP3X_YNR_BASE + 0x00080)
+#define ISP39_YNR_LSGM_Y_10_11 (ISP3X_YNR_BASE + 0x00084)
+#define ISP39_YNR_LSGM_Y_12_13 (ISP3X_YNR_BASE + 0x00088)
+#define ISP39_YNR_LSGM_Y_14_15 (ISP3X_YNR_BASE + 0x0008c)
+#define ISP39_YNR_LSGM_Y_16 (ISP3X_YNR_BASE + 0x00090)
+#define ISP39_YNR_RNR_STRENGTH03 (ISP3X_YNR_BASE + 0x000d0)
+#define ISP39_YNR_RNR_STRENGTH47 (ISP3X_YNR_BASE + 0x000d4)
+#define ISP39_YNR_RNR_STRENGTH8B (ISP3X_YNR_BASE + 0x000d8)
+#define ISP39_YNR_RNR_STRENGTHCF (ISP3X_YNR_BASE + 0x000dc)
+#define ISP39_YNR_RNR_STRENGTH16 (ISP3X_YNR_BASE + 0x000e0)
+#define ISP39_YNR_NLM_STRONG_EDGE (ISP3X_YNR_BASE + 0x000ec)
+#define ISP39_YNR_NLM_SIGMA_GAIN (ISP3X_YNR_BASE + 0x000f0)
+#define ISP39_YNR_NLM_COE (ISP3X_YNR_BASE + 0x000f4)
+#define ISP39_YNR_NLM_WEIGHT (ISP3X_YNR_BASE + 0x000f8)
+#define ISP39_YNR_NLM_NR_WEIGHT (ISP3X_YNR_BASE + 0x000fc)
+#define ISP33_YNR_GAIN_CTRL (ISP3X_YNR_BASE + 0x00010)
+#define ISP33_YNR_GAIN_ADJ_0_2 (ISP3X_YNR_BASE + 0x00014)
+#define ISP33_YNR_RNR_MAX_R (ISP3X_YNR_BASE + 0x00020)
+#define ISP33_YNR_RNR_CENTER_COOR (ISP3X_YNR_BASE + 0x00024)
+#define ISP33_YNR_RNR_STRENGTH03 (ISP3X_YNR_BASE + 0x00028)
+#define ISP33_YNR_RNR_STRENGTH16 (ISP3X_YNR_BASE + 0x00038)
+#define ISP33_YNR_SGM_DX_0_1 (ISP3X_YNR_BASE + 0x00040)
+#define ISP33_YNR_SGM_DX_16 (ISP3X_YNR_BASE + 0x00060)
+#define ISP33_YNR_SGM_Y_0_1 (ISP3X_YNR_BASE + 0x00064)
+#define ISP33_YNR_SGM_Y_16 (ISP3X_YNR_BASE + 0x00084)
+#define ISP33_YNR_HI_SIGMA_GAIN (ISP3X_YNR_BASE + 0x000a0)
+#define ISP33_YNR_HI_GAUS_COE (ISP3X_YNR_BASE + 0x000a4)
+#define ISP33_YNR_HI_WEIGHT (ISP3X_YNR_BASE + 0x000a8)
+#define ISP33_YNR_HI_GAUS1_COE_0_2 (ISP3X_YNR_BASE + 0x000ac)
+#define ISP33_YNR_HI_GAUS1_COE_3_5 (ISP3X_YNR_BASE + 0x000b0)
+#define ISP33_YNR_HI_TEXT (ISP3X_YNR_BASE + 0x000b4)
+#define ISP33_YNR_MI_GAUS_COE (ISP3X_YNR_BASE + 0x000c0)
+#define ISP33_YNR_MI_STRG_DETAIL (ISP3X_YNR_BASE + 0x000c4)
+#define ISP33_YNR_MI_WEIGHT (ISP3X_YNR_BASE + 0x000c8)
+#define ISP33_YNR_LO_STRG_DETAIL (ISP3X_YNR_BASE + 0x000e0)
+#define ISP33_YNR_LO_LIMIT_SCALE (ISP3X_YNR_BASE + 0x000e4)
+#define ISP33_YNR_LO_WEIGHT (ISP3X_YNR_BASE + 0x000e8)
+#define ISP33_YNR_LO_TEXT_THRED (ISP3X_YNR_BASE + 0x000ec)
+#define ISP33_YNR_FUSION_WEIT_ADJ_0_3 (ISP3X_YNR_BASE + 0x000f0)
+#define ISP33_YNR_FUSION_WEIT_ADJ_8 (ISP3X_YNR_BASE + 0x000f8)
+#define ISP35_YNR_MI_TEX2WGT_SCALE_0_1_2 (ISP3X_YNR_BASE + 0x00088)
+#define ISP35_YNR_LO_TEX2WGT_SCALE_0_1_2 (ISP3X_YNR_BASE + 0x00094)
+#define ISP35_YNR_MI_GAUS_COE1 (ISP3X_YNR_BASE + 0x000d0)
+#define ISP35_YNR_DSIIR_COE (ISP3X_YNR_BASE + 0x000dc)
+
+#define ISP3X_CNR_BASE 0x00002800
+#define ISP3X_CNR_CTRL (ISP3X_CNR_BASE + 0x00000)
+#define ISP3X_CNR_EXGAIN (ISP3X_CNR_BASE + 0x00004)
+#define ISP3X_CNR_GAIN_PARA (ISP3X_CNR_BASE + 0x00008)
+#define ISP32_CNR_THUMB1 (ISP3X_CNR_BASE + 0x00008)
+#define ISP3X_CNR_GAIN_UV_PARA (ISP3X_CNR_BASE + 0x0000c)
+#define ISP32_CNR_THUMB_BF_RATIO (ISP3X_CNR_BASE + 0x0000c)
+#define ISP3X_CNR_LMED3 (ISP3X_CNR_BASE + 0x00010)
+#define ISP32_CNR_LBF_WEITD (ISP3X_CNR_BASE + 0x00010)
+#define ISP3X_CNR_LBF5_GAIN (ISP3X_CNR_BASE + 0x00014)
+#define ISP32_CNR_IIR_PARA1 (ISP3X_CNR_BASE + 0x00014)
+#define ISP3X_CNR_LBF5_WEITD0_3 (ISP3X_CNR_BASE + 0x00018)
+#define ISP32_CNR_IIR_PARA2 (ISP3X_CNR_BASE + 0x00018)
+#define ISP3X_CNR_LBF5_WEITD4 (ISP3X_CNR_BASE + 0x0001c)
+#define ISP32_CNR_GAUS_COE1 (ISP3X_CNR_BASE + 0x0001c)
+#define ISP3X_CNR_HMED3 (ISP3X_CNR_BASE + 0x00020)
+#define ISP32_CNR_GAUS_COE2 (ISP3X_CNR_BASE + 0x00020)
+#define ISP3X_CNR_HBF5 (ISP3X_CNR_BASE + 0x00024)
+#define ISP32_CNR_GAUS_RATIO (ISP3X_CNR_BASE + 0x00024)
+#define ISP3X_CNR_LBF3 (ISP3X_CNR_BASE + 0x00028)
+#define ISP32_CNR_BF_PARA1 (ISP3X_CNR_BASE + 0x00028)
+#define ISP32_CNR_BF_PARA2 (ISP3X_CNR_BASE + 0x0002C)
+#define ISP3X_CNR_SIGMA0 (ISP3X_CNR_BASE + 0x0002C)
+#define ISP3X_CNR_SIGMA1 (ISP3X_CNR_BASE + 0x00030)
+#define ISP3X_CNR_SIGMA2 (ISP3X_CNR_BASE + 0x00034)
+#define ISP3X_CNR_SIGMA3 (ISP3X_CNR_BASE + 0x00038)
+#define ISP32_CNR_SIGMA0 (ISP3X_CNR_BASE + 0x00030)
+#define ISP32_CNR_SIGMA1 (ISP3X_CNR_BASE + 0x00034)
+#define ISP32_CNR_SIGMA2 (ISP3X_CNR_BASE + 0x00038)
+#define ISP32_CNR_SIGMA3 (ISP3X_CNR_BASE + 0x0003c)
+#define ISP32_CNR_IIR_GLOBAL_GAIN (ISP3X_CNR_BASE + 0x00040)
+#define ISP39_CNR_WGT_SIGMA0 (ISP3X_CNR_BASE + 0x00044)
+#define ISP39_CNR_WGT_SIGMA1 (ISP3X_CNR_BASE + 0x00048)
+#define ISP39_CNR_WGT_SIGMA2 (ISP3X_CNR_BASE + 0x0004c)
+#define ISP39_CNR_WGT_SIGMA3 (ISP3X_CNR_BASE + 0x00050)
+#define ISP39_CNR_GAUS_X_SIGMAR0 (ISP3X_CNR_BASE + 0x00054)
+#define ISP39_CNR_GAUS_X_SIGMAR1 (ISP3X_CNR_BASE + 0x00058)
+#define ISP39_CNR_GAUS_X_SIGMAR2 (ISP3X_CNR_BASE + 0x0005c)
+#define ISP39_CNR_GAUS_Y_SIGMAR0 (ISP3X_CNR_BASE + 0x00060)
+#define ISP39_CNR_GAUS_Y_SIGMAR1 (ISP3X_CNR_BASE + 0x00064)
+#define ISP39_CNR_GAUS_Y_SIGMAR2 (ISP3X_CNR_BASE + 0x00068)
+#define ISP39_CNR_GAUS_Y_SIGMAR3 (ISP3X_CNR_BASE + 0x0006c)
+#define ISP35_CNR_IIR_SIGMAR0 (ISP3X_CNR_BASE + 0x00070)
+#define ISP35_CNR_IIR_SIGMAR3 (ISP3X_CNR_BASE + 0x0007c)
+#define ISP35_CNR_HSV_CURVE0 (ISP3X_CNR_BASE + 0x00080)
+#define ISP35_CNR_HSV_CURVE2 (ISP3X_CNR_BASE + 0x00088)
+#define ISP35_CNR_SAT_CURVE0 (ISP3X_CNR_BASE + 0x0008c)
+#define ISP35_CNR_SAT_CURVE2 (ISP3X_CNR_BASE + 0x00094)
+#define ISP35_CNR_GAIN_ADJ_CURVE0 (ISP3X_CNR_BASE + 0x00098)
+#define ISP35_CNR_GAIN_ADJ_CURVE2 (ISP3X_CNR_BASE + 0x000a0)
+
+#define ISP3X_SHARP_BASE 0x00002900
+#define ISP3X_SHARP_EN (ISP3X_SHARP_BASE + 0x00000)
+#define ISP3X_SHARP_RATIO (ISP3X_SHARP_BASE + 0x00004)
+#define ISP3X_SHARP_LUMA_DX (ISP3X_SHARP_BASE + 0x00008)
+#define ISP3X_SHARP_PBF_SIGMA_INV_0 (ISP3X_SHARP_BASE + 0x0000c)
+#define ISP3X_SHARP_PBF_SIGMA_INV_1 (ISP3X_SHARP_BASE + 0x00010)
+#define ISP3X_SHARP_PBF_SIGMA_INV_2 (ISP3X_SHARP_BASE + 0x00014)
+#define ISP3X_SHARP_BF_SIGMA_INV_0 (ISP3X_SHARP_BASE + 0x00018)
+#define ISP3X_SHARP_BF_SIGMA_INV_1 (ISP3X_SHARP_BASE + 0x0001c)
+#define ISP3X_SHARP_BF_SIGMA_INV_2 (ISP3X_SHARP_BASE + 0x00020)
+#define ISP3X_SHARP_SIGMA_SHIFT (ISP3X_SHARP_BASE + 0x00024)
+#define ISP3X_SHARP_EHF_TH_0 (ISP3X_SHARP_BASE + 0x00028)
+#define ISP3X_SHARP_EHF_TH_1 (ISP3X_SHARP_BASE + 0x0002c)
+#define ISP3X_SHARP_EHF_TH_2 (ISP3X_SHARP_BASE + 0x00030)
+#define ISP3X_SHARP_CLIP_HF_0 (ISP3X_SHARP_BASE + 0x00034)
+#define ISP3X_SHARP_CLIP_HF_1 (ISP3X_SHARP_BASE + 0x00038)
+#define ISP3X_SHARP_CLIP_HF_2 (ISP3X_SHARP_BASE + 0x0003c)
+#define ISP3X_SHARP_PBF_COEF (ISP3X_SHARP_BASE + 0x00040)
+#define ISP3X_SHARP_BF_COEF (ISP3X_SHARP_BASE + 0x00044)
+#define ISP3X_SHARP_GAUS_COEF0 (ISP3X_SHARP_BASE + 0x00048)
+#define ISP3X_SHARP_GAUS_COEF1 (ISP3X_SHARP_BASE + 0x0004C)
+#define ISP32_SHARP_GAIN (ISP3X_SHARP_BASE + 0x00050)
+#define ISP32_SHARP_GAIN_ADJUST0 (ISP3X_SHARP_BASE + 0x00054)
+#define ISP32_SHARP_GAIN_ADJUST1 (ISP3X_SHARP_BASE + 0x00058)
+#define ISP32_SHARP_GAIN_ADJUST2 (ISP3X_SHARP_BASE + 0x0005c)
+#define ISP32_SHARP_GAIN_ADJUST3 (ISP3X_SHARP_BASE + 0x00060)
+#define ISP32_SHARP_GAIN_ADJUST4 (ISP3X_SHARP_BASE + 0x00064)
+#define ISP32_SHARP_GAIN_ADJUST5 (ISP3X_SHARP_BASE + 0x00068)
+#define ISP32_SHARP_GAIN_ADJUST6 (ISP3X_SHARP_BASE + 0x0006c)
+#define ISP32_SHARP_CENTER (ISP3X_SHARP_BASE + 0x00070)
+#define ISP32_SHARP_GAIN_DIS_STRENGTH0 (ISP3X_SHARP_BASE + 0x00074)
+#define ISP32_SHARP_GAIN_DIS_STRENGTH1 (ISP3X_SHARP_BASE + 0x00078)
+#define ISP32_SHARP_GAIN_DIS_STRENGTH2 (ISP3X_SHARP_BASE + 0x0007c)
+#define ISP32_SHARP_GAIN_DIS_STRENGTH3 (ISP3X_SHARP_BASE + 0x00080)
+#define ISP32_SHARP_GAIN_DIS_STRENGTH4 (ISP3X_SHARP_BASE + 0x00084)
+#define ISP32_SHARP_GAIN_DIS_STRENGTH5 (ISP3X_SHARP_BASE + 0x00088)
+#define ISP32_SHARP_TEXTURE (ISP3X_SHARP_BASE + 0x0008c)
+#define ISP32L_SHARP_CLIP_NEG_0 (ISP3X_SHARP_BASE + 0x00090)
+#define ISP32L_SHARP_CLIP_NEG_1 (ISP3X_SHARP_BASE + 0x00094)
+#define ISP32L_SHARP_CLIP_NEG_2 (ISP3X_SHARP_BASE + 0x00098)
+#define ISP39_SHARP_ALPHA (ISP3X_SHARP_BASE + 0x00004)
+#define ISP39_SHARP_LOCAL_STRG_0 (ISP3X_SHARP_BASE + 0x00028)
+#define ISP39_SHARP_LOCAL_STRG_1 (ISP3X_SHARP_BASE + 0x0002c)
+#define ISP39_SHARP_LOCAL_STRG_2 (ISP3X_SHARP_BASE + 0x00030)
+#define ISP39_SHARP_POS_CLIP_0 (ISP3X_SHARP_BASE + 0x00034)
+#define ISP39_SHARP_POS_CLIP_1 (ISP3X_SHARP_BASE + 0x00038)
+#define ISP39_SHARP_POS_CLIP_2 (ISP3X_SHARP_BASE + 0x0003c)
+#define ISP39_SHARP_DETAILBF_COEF (ISP3X_SHARP_BASE + 0x00044)
+#define ISP3X_SHARP_IMGLPF_COEF_0 (ISP3X_SHARP_BASE + 0x00048)
+#define ISP3X_SHARP_IMGLPF_COEF_1 (ISP3X_SHARP_BASE + 0x0004C)
+#define ISP39_SHARP_CLIP_NEG_0 (ISP3X_SHARP_BASE + 0x0008c)
+#define ISP39_SHARP_CLIP_NEG_1 (ISP3X_SHARP_BASE + 0x00090)
+#define ISP39_SHARP_CLIP_NEG_2 (ISP3X_SHARP_BASE + 0x00094)
+#define ISP39_SHARP_TEXTURE0 (ISP3X_SHARP_BASE + 0x000a0)
+#define ISP39_SHARP_TEXTURE1 (ISP3X_SHARP_BASE + 0x000a4)
+#define ISP39_SHARP_TEXTURE_LUT0 (ISP3X_SHARP_BASE + 0x000a8)
+#define ISP39_SHARP_TEXTURE_LUT1 (ISP3X_SHARP_BASE + 0x000ac)
+#define ISP39_SHARP_TEXTURE_LUT2 (ISP3X_SHARP_BASE + 0x000b0)
+#define ISP39_SHARP_TEXTURE_LUT3 (ISP3X_SHARP_BASE + 0x000b4)
+#define ISP39_SHARP_TEXTURE_LUT4 (ISP3X_SHARP_BASE + 0x000b8)
+#define ISP39_SHARP_TEXTURE_LUT5 (ISP3X_SHARP_BASE + 0x000bc)
+#define ISP39_SHARP_TEXTURE2 (ISP3X_SHARP_BASE + 0x000c0)
+#define ISP39_SHARP_DETAIL_STRG_LUT0 (ISP3X_SHARP_BASE + 0x000c4)
+#define ISP39_SHARP_DETAIL_STRG_LUT1 (ISP3X_SHARP_BASE + 0x000c8)
+#define ISP39_SHARP_DETAIL_STRG_LUT2 (ISP3X_SHARP_BASE + 0x000cc)
+#define ISP39_SHARP_DETAIL_STRG_LUT3 (ISP3X_SHARP_BASE + 0x000d0)
+#define ISP39_SHARP_DETAIL_STRG_LUT4 (ISP3X_SHARP_BASE + 0x000d4)
+#define ISP39_SHARP_DETAIL_STRG_LUT5 (ISP3X_SHARP_BASE + 0x000d8)
+#define ISP39_SHARP_DETAIL_STRG_LUT6 (ISP3X_SHARP_BASE + 0x000dc)
+#define ISP39_SHARP_DETAIL_STRG_LUT7 (ISP3X_SHARP_BASE + 0x000e0)
+#define ISP39_SHARP_DETAIL_STRG_LUT8 (ISP3X_SHARP_BASE + 0x000e4)
+#define ISP33_SHARP_TEXTURE0 (ISP3X_SHARP_BASE + 0x00004)
+#define ISP33_SHARP_TEXTURE1 (ISP3X_SHARP_BASE + 0x00008)
+#define ISP33_SHARP_TEXTURE2 (ISP3X_SHARP_BASE + 0x0000c)
+#define ISP33_SHARP_TEXTURE3 (ISP3X_SHARP_BASE + 0x00010)
+#define ISP33_SHARP_TEXTURE4 (ISP3X_SHARP_BASE + 0x00014)
+#define ISP33_SHARP_HPF_KERNEL0 (ISP3X_SHARP_BASE + 0x00018)
+#define ISP33_SHARP_HPF_KERNEL1 (ISP3X_SHARP_BASE + 0x0001c)
+#define ISP33_SHARP_TEXFLT_KERNEL (ISP3X_SHARP_BASE + 0x00020)
+#define ISP33_SHARP_DETAIL0 (ISP3X_SHARP_BASE + 0x00024)
+#define ISP33_SHARP_DETAIL1 (ISP3X_SHARP_BASE + 0x00028)
+#define ISP33_SHARP_LUMA_DX (ISP3X_SHARP_BASE + 0x0002c)
+#define ISP33_SHARP_PBF_VSIGMA0 (ISP3X_SHARP_BASE + 0x00030)
+#define ISP33_SHARP_PBF_KERNEL (ISP3X_SHARP_BASE + 0x00040)
+#define ISP33_SHARP_DETAIL_KERNEL0 (ISP3X_SHARP_BASE + 0x00044)
+#define ISP33_SHARP_DETAIL_KERNEL1 (ISP3X_SHARP_BASE + 0x00048)
+#define ISP33_SHARP_DETAIL_KERNEL2 (ISP3X_SHARP_BASE + 0x0004c)
+#define ISP33_SHARP_GAIN (ISP3X_SHARP_BASE + 0x00050)
+#define ISP33_SHARP_GAIN_ADJ0 (ISP3X_SHARP_BASE + 0x00054)
+#define ISP33_SHARP_GAIN_ADJ1 (ISP3X_SHARP_BASE + 0x00058)
+#define ISP33_SHARP_GAIN_ADJ2 (ISP3X_SHARP_BASE + 0x0005c)
+#define ISP33_SHARP_GAIN_ADJ3 (ISP3X_SHARP_BASE + 0x00060)
+#define ISP33_SHARP_GAIN_ADJ4 (ISP3X_SHARP_BASE + 0x00064)
+#define ISP33_SHARP_EDGE0 (ISP3X_SHARP_BASE + 0x00068)
+#define ISP33_SHARP_EDGE1 (ISP3X_SHARP_BASE + 0x0006c)
+#define ISP33_SHARP_EDGE_KERNEL0 (ISP3X_SHARP_BASE + 0x00070)
+#define ISP33_SHARP_EDGE_KERNEL2 (ISP3X_SHARP_BASE + 0x00078)
+#define ISP33_SHARP_EDGE_WGT_VAL0 (ISP3X_SHARP_BASE + 0x0007c)
+#define ISP33_SHARP_EDGE_WGT_VAL5 (ISP3X_SHARP_BASE + 0x00090)
+#define ISP33_SHARP_LUMA_ADJ_STRG0 (ISP3X_SHARP_BASE + 0x00094)
+#define ISP33_SHARP_CENTER (ISP3X_SHARP_BASE + 0x0009c)
+#define ISP33_SHARP_OUT_LIMIT (ISP3X_SHARP_BASE + 0x000a0)
+#define ISP33_SHARP_TEX_X_INV_FIX0 (ISP3X_SHARP_BASE + 0x000a4)
+#define ISP33_SHARP_TEX_X_INV_FIX1 (ISP3X_SHARP_BASE + 0x000a8)
+#define ISP33_SHARP_TEX_X_INV_FIX2 (ISP3X_SHARP_BASE + 0x000ac)
+#define ISP33_SHARP_LOCAL_STRG0 (ISP3X_SHARP_BASE + 0x000b0)
+#define ISP33_SHARP_LOCAL_STRG1 (ISP3X_SHARP_BASE + 0x000b4)
+#define ISP33_SHARP_LOCAL_STRG2 (ISP3X_SHARP_BASE + 0x000b8)
+#define ISP33_SHARP_DETAIL_SCALE_TAB0 (ISP3X_SHARP_BASE + 0x000c0)
+#define ISP33_SHARP_DETAIL_SCALE_TAB1 (ISP3X_SHARP_BASE + 0x000c4)
+#define ISP33_SHARP_DETAIL_SCALE_TAB2 (ISP3X_SHARP_BASE + 0x000c8)
+#define ISP33_SHARP_DETAIL_SCALE_TAB3 (ISP3X_SHARP_BASE + 0x000cc)
+#define ISP33_SHARP_DETAIL_SCALE_TAB4 (ISP3X_SHARP_BASE + 0x000d0)
+#define ISP33_SHARP_DETAIL_SCALE_TAB5 (ISP3X_SHARP_BASE + 0x000d4)
+#define ISP33_SHARP_DETAIL_TEX_CLIP0 (ISP3X_SHARP_BASE + 0x000d8)
+#define ISP33_SHARP_DETAIL_TEX_CLIP1 (ISP3X_SHARP_BASE + 0x000dc)
+#define ISP33_SHARP_DETAIL_TEX_CLIP2 (ISP3X_SHARP_BASE + 0x000e0)
+#define ISP33_SHARP_DETAIL_TEX_CLIP3 (ISP3X_SHARP_BASE + 0x000e4)
+#define ISP33_SHARP_DETAIL_TEX_CLIP4 (ISP3X_SHARP_BASE + 0x000e8)
+#define ISP33_SHARP_DETAIL_TEX_CLIP5 (ISP3X_SHARP_BASE + 0x000ec)
+#define ISP33_SHARP_GRAIN_TEX_CLIP0 (ISP3X_SHARP_BASE + 0x000f0)
+#define ISP33_SHARP_GRAIN_TEX_CLIP1 (ISP3X_SHARP_BASE + 0x000f4)
+#define ISP33_SHARP_GRAIN_TEX_CLIP2 (ISP3X_SHARP_BASE + 0x000f8)
+#define ISP33_SHARP_GRAIN_TEX_CLIP3 (ISP3X_SHARP_BASE + 0x000fc)
+#define ISP33_SHARP_GRAIN_TEX_CLIP4 (ISP3X_SHARP_BASE + 0x00100)
+#define ISP33_SHARP_GRAIN_TEX_CLIP5 (ISP3X_SHARP_BASE + 0x00104)
+#define ISP33_SHARP_DETAIL_LUMA_CLIP0 (ISP3X_SHARP_BASE + 0x00108)
+#define ISP33_SHARP_DETAIL_LUMA_CLIP1 (ISP3X_SHARP_BASE + 0x0010c)
+#define ISP33_SHARP_DETAIL_LUMA_CLIP2 (ISP3X_SHARP_BASE + 0x00110)
+#define ISP33_SHARP_DETAIL_LUMA_CLIP3 (ISP3X_SHARP_BASE + 0x00114)
+#define ISP33_SHARP_DETAIL_LUMA_CLIP4 (ISP3X_SHARP_BASE + 0x00118)
+#define ISP33_SHARP_DETAIL_LUMA_CLIP5 (ISP3X_SHARP_BASE + 0x0011c)
+#define ISP33_SHARP_GRAIN_STRG (ISP3X_SHARP_BASE + 0x00120)
+#define ISP33_SHARP_HUE_ADJ_TAB0 (ISP3X_SHARP_BASE + 0x00124)
+#define ISP33_SHARP_DISATANCE_ADJ0 (ISP3X_SHARP_BASE + 0x00130)
+#define ISP33_SHARP_DISATANCE_ADJ2 (ISP3X_SHARP_BASE + 0x00138)
+#define ISP33_SHARP_NOISE_SIGMA0 (ISP3X_SHARP_BASE + 0x00148)
+#define ISP33_SHARP_NOISE_SIGMA4 (ISP3X_SHARP_BASE + 0x00158)
+#define ISP33_SHARP_LOSSTEXINHINR_STRG (ISP3X_SHARP_BASE + 0x0016c)
+#define ISP33_SHARP_NOISE_CURVE0 (ISP3X_SHARP_BASE + 0x00170)
+#define ISP33_SHARP_NOISE_CURVE8 (ISP3X_SHARP_BASE + 0x00190)
+#define ISP33_SHARP_NOISE_CLIP (ISP3X_SHARP_BASE + 0x00194)
+#define ISP35_SHARP_TEX2DETAIL_STRG0 (ISP3X_SHARP_BASE + 0x0013c)
+#define ISP35_SHARP_TEX2DETAIL_STRG2 (ISP3X_SHARP_BASE + 0x00144)
+#define ISP35_SHARP_TEX2MFDETAIL_STRG0 (ISP3X_SHARP_BASE + 0x0015c)
+#define ISP35_SHARP_TEX2MFDETAIL_STRG2 (ISP3X_SHARP_BASE + 0x00164)
+#define ISP35_SHARP_EDGEWGTFLT_KERNEL (ISP3X_SHARP_BASE + 0x00198)
+#define ISP35_SHARP_EDGE_GLOBAL_CLIP (ISP3X_SHARP_BASE + 0x001a0)
+#define ISP35_SHARP_MFDETAIL (ISP3X_SHARP_BASE + 0x001a4)
+#define ISP35_SHARP_MFDETAIL_CLIP (ISP3X_SHARP_BASE + 0x001a8)
+#define ISP35_SHARP_SATURATION_STRG0 (ISP3X_SHARP_BASE + 0x001ac)
+#define ISP35_SHARP_SATURATION_STRG2 (ISP3X_SHARP_BASE + 0x001b4)
+
+#define ISP33_BAY3D_BASE 0x00002B00
+#define ISP33_BAY3D_CTRL0 (ISP33_BAY3D_BASE + 0x00000)
+#define ISP33_BAY3D_CTRL1 (ISP33_BAY3D_BASE + 0x00004)
+#define ISP33_BAY3D_CTRL2 (ISP33_BAY3D_BASE + 0x00008)
+#define ISP33_BAY3D_CTRL3 (ISP33_BAY3D_BASE + 0x0000c)
+#define ISP33_BAY3D_TRANS0 (ISP33_BAY3D_BASE + 0x00010)
+#define ISP33_BAY3D_TRANS1 (ISP33_BAY3D_BASE + 0x00014)
+#define ISP33_BAY3D_CURHI_SIGSCL (ISP33_BAY3D_BASE + 0x00058)
+#define ISP33_BAY3D_CURHI_SIGOF (ISP33_BAY3D_BASE + 0x00068)
+#define ISP33_BAY3D_CURHISPW0 (ISP33_BAY3D_BASE + 0x00070)
+#define ISP33_BAY3D_CURHISPW1 (ISP33_BAY3D_BASE + 0x00074)
+#define ISP33_BAY3D_IIRSX0 (ISP33_BAY3D_BASE + 0x00084)
+#define ISP33_BAY3D_IIRSY0 (ISP33_BAY3D_BASE + 0x000a4)
+#define ISP33_BAY3D_PREHI_SIGSCL (ISP33_BAY3D_BASE + 0x000c4)
+#define ISP33_BAY3D_PREHI_WSCL (ISP33_BAY3D_BASE + 0x000c8)
+#define ISP33_BAY3D_PREHIWMM (ISP33_BAY3D_BASE + 0x000cc)
+#define ISP33_BAY3D_PREHISIGOF (ISP33_BAY3D_BASE + 0x000d4)
+#define ISP33_BAY3D_PREHISIGSCL (ISP33_BAY3D_BASE + 0x000d8)
+#define ISP33_BAY3D_PREHISPW0 (ISP33_BAY3D_BASE + 0x000dc)
+#define ISP33_BAY3D_PREHISPW1 (ISP33_BAY3D_BASE + 0x000e0)
+#define ISP33_BAY3D_PRELOSIGCSL (ISP33_BAY3D_BASE + 0x000e4)
+#define ISP33_BAY3D_PRELOSIGOF (ISP33_BAY3D_BASE + 0x000e8)
+#define ISP33_BAY3D_PREHI_NRCT (ISP33_BAY3D_BASE + 0x000f0)
+#define ISP33_BAY3D_TNRSX0 (ISP33_BAY3D_BASE + 0x00100)
+#define ISP33_BAY3D_TNRSY0 (ISP33_BAY3D_BASE + 0x00128)
+#define ISP33_BAY3D_HIWD0 (ISP33_BAY3D_BASE + 0x00150)
+#define ISP33_BAY3D_LOWD0 (ISP33_BAY3D_BASE + 0x0015c)
+#define ISP33_BAY3D_GF3 (ISP33_BAY3D_BASE + 0x00168)
+#define ISP33_BAY3D_GF4 (ISP33_BAY3D_BASE + 0x0016c)
+#define ISP33_BAY3D_VIIR (ISP33_BAY3D_BASE + 0x00170)
+#define ISP33_BAY3D_LFSCL (ISP33_BAY3D_BASE + 0x00174)
+#define ISP33_BAY3D_LFSCLTH (ISP33_BAY3D_BASE + 0x00178)
+#define ISP33_BAY3D_DSWGTSCL (ISP33_BAY3D_BASE + 0x0017c)
+#define ISP33_BAY3D_WGTLASTSCL (ISP33_BAY3D_BASE + 0x00180)
+#define ISP33_BAY3D_WGTSCL0 (ISP33_BAY3D_BASE + 0x00184)
+#define ISP33_BAY3D_WGTSCL1 (ISP33_BAY3D_BASE + 0x00188)
+#define ISP33_BAY3D_WGTSCL2 (ISP33_BAY3D_BASE + 0x0018c)
+#define ISP33_BAY3D_WGTOFF (ISP33_BAY3D_BASE + 0x00190)
+#define ISP33_BAY3D_WGT1OFF (ISP33_BAY3D_BASE + 0x00194)
+#define ISP33_BAY3D_SIGORG (ISP33_BAY3D_BASE + 0x00198)
+#define ISP33_BAY3D_WGTLO_L (ISP33_BAY3D_BASE + 0x0019c)
+#define ISP33_BAY3D_WGTLO_H (ISP33_BAY3D_BASE + 0x001a0)
+#define ISP33_BAY3D_STH_SCL (ISP33_BAY3D_BASE + 0x001a4)
+#define ISP33_BAY3D_STH_LIMIT (ISP33_BAY3D_BASE + 0x001a8)
+#define ISP33_BAY3D_HIKEEP (ISP33_BAY3D_BASE + 0x001ac)
+#define ISP33_BAY3D_PIXMAX (ISP33_BAY3D_BASE + 0x001b0)
+#define ISP33_BAY3D_SIGNUMTH (ISP33_BAY3D_BASE + 0x001b4)
+#define ISP33_BAY3D_MONR (ISP33_BAY3D_BASE + 0x001b8)
+#define ISP33_BAY3D_SIGSCL (ISP33_BAY3D_BASE + 0x001bc)
+#define ISP33_BAY3D_DSOFF (ISP33_BAY3D_BASE + 0x001d0)
+#define ISP33_BAY3D_DSSCL (ISP33_BAY3D_BASE + 0x001d4)
+#define ISP33_BAY3D_ME0 (ISP33_BAY3D_BASE + 0x001d8)
+#define ISP33_BAY3D_ME1 (ISP33_BAY3D_BASE + 0x001dc)
+#define ISP33_BAY3D_ME2 (ISP33_BAY3D_BASE + 0x001e0)
+#define ISP33_BAY3D_WGTMAX (ISP33_BAY3D_BASE + 0x001e4)
+#define ISP33_BAY3D_WGT1MAX (ISP33_BAY3D_BASE + 0x001e8)
+#define ISP33_BAY3D_WGTM0 (ISP33_BAY3D_BASE + 0x001ec)
+#define ISP33_BAY3D_PRELOWGT (ISP33_BAY3D_BASE + 0x0020c)
+#define ISP33_BAY3D_MIDBIG0 (ISP33_BAY3D_BASE + 0x00280)
+#define ISP33_BAY3D_MIDBIG1 (ISP33_BAY3D_BASE + 0x00284)
+#define ISP33_BAY3D_MIDBIG2 (ISP33_BAY3D_BASE + 0x00288)
+#define ISP33_BAY3D_TNRSUM (ISP33_BAY3D_BASE + 0x002d4)
+#define ISP33_BAY3D_TNRYO0 (ISP33_BAY3D_BASE + 0x002d8)
+#define ISP35_BAY3D_PREHI_SIGSCL (ISP33_BAY3D_BASE + 0x00058)
+#define ISP35_BAY3D_PREHI_SIGOF (ISP33_BAY3D_BASE + 0x00068)
+#define ISP35_BAY3D_LOCOEF0 (ISP33_BAY3D_BASE + 0x001f0)
+#define ISP35_BAY3D_LOCOEF1 (ISP33_BAY3D_BASE + 0x001f4)
+#define ISP35_BAY3D_DPC0 (ISP33_BAY3D_BASE + 0x001f8)
+#define ISP35_BAY3D_DPC1 (ISP33_BAY3D_BASE + 0x001fc)
+#define ISP35_BAY3D_MONROFF (ISP33_BAY3D_BASE + 0x0028c)
+
+#define ISP3X_BAY3D_BASE 0x00002C00
+#define ISP3X_BAY3D_CTRL (ISP3X_BAY3D_BASE + 0x00000)
+#define ISP3X_BAY3D_KALRATIO (ISP3X_BAY3D_BASE + 0x00004)
+#define ISP3X_BAY3D_GLBPK2 (ISP3X_BAY3D_BASE + 0x00008)
+#define ISP32_BAY3D_CTRL1 (ISP3X_BAY3D_BASE + 0x0000c)
+#define ISP3X_BAY3D_WGTLMT (ISP3X_BAY3D_BASE + 0x00010)
+#define ISP3X_BAY3D_SIG0_X0 (ISP3X_BAY3D_BASE + 0x00014)
+#define ISP3X_BAY3D_SIG0_X1 (ISP3X_BAY3D_BASE + 0x00018)
+#define ISP3X_BAY3D_SIG0_X2 (ISP3X_BAY3D_BASE + 0x0001C)
+#define ISP3X_BAY3D_SIG0_X3 (ISP3X_BAY3D_BASE + 0x00020)
+#define ISP3X_BAY3D_SIG0_X4 (ISP3X_BAY3D_BASE + 0x00024)
+#define ISP3X_BAY3D_SIG0_X5 (ISP3X_BAY3D_BASE + 0x00028)
+#define ISP3X_BAY3D_SIG0_X6 (ISP3X_BAY3D_BASE + 0x0002C)
+#define ISP3X_BAY3D_SIG0_X7 (ISP3X_BAY3D_BASE + 0x00030)
+#define ISP3X_BAY3D_SIG0_Y0 (ISP3X_BAY3D_BASE + 0x00034)
+#define ISP3X_BAY3D_SIG0_Y1 (ISP3X_BAY3D_BASE + 0x00038)
+#define ISP3X_BAY3D_SIG0_Y2 (ISP3X_BAY3D_BASE + 0x0003C)
+#define ISP3X_BAY3D_SIG0_Y3 (ISP3X_BAY3D_BASE + 0x00040)
+#define ISP3X_BAY3D_SIG0_Y4 (ISP3X_BAY3D_BASE + 0x00044)
+#define ISP3X_BAY3D_SIG0_Y5 (ISP3X_BAY3D_BASE + 0x00048)
+#define ISP3X_BAY3D_SIG0_Y6 (ISP3X_BAY3D_BASE + 0x0004C)
+#define ISP3X_BAY3D_SIG0_Y7 (ISP3X_BAY3D_BASE + 0x00050)
+#define ISP3X_BAY3D_SIG1_X0 (ISP3X_BAY3D_BASE + 0x00054)
+#define ISP3X_BAY3D_SIG1_X1 (ISP3X_BAY3D_BASE + 0x00058)
+#define ISP3X_BAY3D_SIG1_X2 (ISP3X_BAY3D_BASE + 0x0005C)
+#define ISP3X_BAY3D_SIG1_X3 (ISP3X_BAY3D_BASE + 0x00060)
+#define ISP3X_BAY3D_SIG1_X4 (ISP3X_BAY3D_BASE + 0x00064)
+#define ISP3X_BAY3D_SIG1_X5 (ISP3X_BAY3D_BASE + 0x00068)
+#define ISP3X_BAY3D_SIG1_X6 (ISP3X_BAY3D_BASE + 0x0006C)
+#define ISP3X_BAY3D_SIG1_X7 (ISP3X_BAY3D_BASE + 0x00070)
+#define ISP3X_BAY3D_SIG1_Y0 (ISP3X_BAY3D_BASE + 0x00074)
+#define ISP3X_BAY3D_SIG1_Y1 (ISP3X_BAY3D_BASE + 0x00078)
+#define ISP3X_BAY3D_SIG1_Y2 (ISP3X_BAY3D_BASE + 0x0007C)
+#define ISP3X_BAY3D_SIG1_Y3 (ISP3X_BAY3D_BASE + 0x00080)
+#define ISP3X_BAY3D_SIG1_Y4 (ISP3X_BAY3D_BASE + 0x00084)
+#define ISP3X_BAY3D_SIG1_Y5 (ISP3X_BAY3D_BASE + 0x00088)
+#define ISP3X_BAY3D_SIG1_Y6 (ISP3X_BAY3D_BASE + 0x0008C)
+#define ISP3X_BAY3D_SIG1_Y7 (ISP3X_BAY3D_BASE + 0x00090)
+#define ISP3X_BAY3D_SIG2_Y0 (ISP3X_BAY3D_BASE + 0x00094)
+#define ISP3X_BAY3D_SIG2_Y1 (ISP3X_BAY3D_BASE + 0x00098)
+#define ISP3X_BAY3D_SIG2_Y2 (ISP3X_BAY3D_BASE + 0x0009C)
+#define ISP3X_BAY3D_SIG2_Y3 (ISP3X_BAY3D_BASE + 0x000A0)
+#define ISP3X_BAY3D_SIG2_Y4 (ISP3X_BAY3D_BASE + 0x000A4)
+#define ISP3X_BAY3D_SIG2_Y5 (ISP3X_BAY3D_BASE + 0x000A8)
+#define ISP3X_BAY3D_SIG2_Y6 (ISP3X_BAY3D_BASE + 0x000AC)
+#define ISP3X_BAY3D_SIG2_Y7 (ISP3X_BAY3D_BASE + 0x000B0)
+#define ISP3X_BAY3D_LODIF_STAT0 (ISP3X_BAY3D_BASE + 0x000B4)
+#define ISP3X_BAY3D_LODIF_STAT1 (ISP3X_BAY3D_BASE + 0x000B8)
+#define ISP3X_BAY3D_HIDIF_STAT0 (ISP3X_BAY3D_BASE + 0x000BC)
+#define ISP3X_BAY3D_HIDIF_STAT1 (ISP3X_BAY3D_BASE + 0x000C0)
+#define ISP3X_BAY3D_MI_ST (ISP3X_BAY3D_BASE + 0x000C8)
+#define ISP3X_BAY3D_RO_CNT (ISP3X_BAY3D_BASE + 0x000CC)
+#define ISP3X_BAY3D_RO_FIFO_CUR (ISP3X_BAY3D_BASE + 0x000D0)
+#define ISP3X_BAY3D_RO_FIFO_IIR (ISP3X_BAY3D_BASE + 0x000D4)
+#define ISP3X_BAY3D_RO_FIFO_DS (ISP3X_BAY3D_BASE + 0x000D8)
+#define ISP3X_BAY3D_RO_FIFO_STATE (ISP3X_BAY3D_BASE + 0x000DC)
+#define ISP3X_BAY3D_IN_IRQ_LINECNT (ISP3X_BAY3D_BASE + 0x000E0)
+#define ISP32_BAY3D_HISIGRAT (ISP3X_BAY3D_BASE + 0x000E4)
+#define ISP32_BAY3D_HISIGOFF (ISP3X_BAY3D_BASE + 0x000E8)
+#define ISP32_BAY3D_LOSIG (ISP3X_BAY3D_BASE + 0x000EC)
+#define ISP32_BAY3D_SIGPK (ISP3X_BAY3D_BASE + 0x000F0)
+#define ISP32_BAY3D_SIGGAUS (ISP3X_BAY3D_BASE + 0x000F4)
+#define ISP32_BAY3D_WRMI (ISP3X_BAY3D_BASE + 0x000F8)
+#define ISP32_BAY3D_RDMI (ISP3X_BAY3D_BASE + 0x000FC)
+#define ISP39_BAY3D_CTRL1 (ISP3X_BAY3D_BASE + 0x00004)
+#define ISP39_BAY3D_CTRL2 (ISP3X_BAY3D_BASE + 0x00008)
+#define ISP39_BAY3D_TRANS0 (ISP3X_BAY3D_BASE + 0x0000c)
+#define ISP39_BAY3D_TRANS1 (ISP3X_BAY3D_BASE + 0x00010)
+#define ISP39_BAY3D_CURDGAIN (ISP3X_BAY3D_BASE + 0x00014)
+#define ISP39_BAY3D_CURSIG_X0 (ISP3X_BAY3D_BASE + 0x00018)
+#define ISP39_BAY3D_CURSIG_X1 (ISP3X_BAY3D_BASE + 0x0001c)
+#define ISP39_BAY3D_CURSIG_X2 (ISP3X_BAY3D_BASE + 0x00020)
+#define ISP39_BAY3D_CURSIG_X3 (ISP3X_BAY3D_BASE + 0x00024)
+#define ISP39_BAY3D_CURSIG_X4 (ISP3X_BAY3D_BASE + 0x00028)
+#define ISP39_BAY3D_CURSIG_X5 (ISP3X_BAY3D_BASE + 0x0002c)
+#define ISP39_BAY3D_CURSIG_X6 (ISP3X_BAY3D_BASE + 0x00030)
+#define ISP39_BAY3D_CURSIG_X7 (ISP3X_BAY3D_BASE + 0x00034)
+#define ISP39_BAY3D_CURSIG_Y0 (ISP3X_BAY3D_BASE + 0x00038)
+#define ISP39_BAY3D_CURSIG_Y1 (ISP3X_BAY3D_BASE + 0x0003c)
+#define ISP39_BAY3D_CURSIG_Y2 (ISP3X_BAY3D_BASE + 0x00040)
+#define ISP39_BAY3D_CURSIG_Y3 (ISP3X_BAY3D_BASE + 0x00044)
+#define ISP39_BAY3D_CURSIG_Y4 (ISP3X_BAY3D_BASE + 0x00048)
+#define ISP39_BAY3D_CURSIG_Y5 (ISP3X_BAY3D_BASE + 0x0004c)
+#define ISP39_BAY3D_CURSIG_Y6 (ISP3X_BAY3D_BASE + 0x00050)
+#define ISP39_BAY3D_CURSIG_Y7 (ISP3X_BAY3D_BASE + 0x00054)
+#define ISP39_BAY3D_CURGAIN_OFF (ISP3X_BAY3D_BASE + 0x00058)
+#define ISP39_BAY3D_CURSIG_OFF (ISP3X_BAY3D_BASE + 0x0005c)
+#define ISP39_BAY3D_CURWTH (ISP3X_BAY3D_BASE + 0x00060)
+#define ISP39_BAY3D_CURBFALP (ISP3X_BAY3D_BASE + 0x00064)
+#define ISP39_BAY3D_CURWDC0 (ISP3X_BAY3D_BASE + 0x00068)
+#define ISP39_BAY3D_CURWDC1 (ISP3X_BAY3D_BASE + 0x0006c)
+#define ISP39_BAY3D_CURWDC2 (ISP3X_BAY3D_BASE + 0x00070)
+#define ISP39_BAY3D_CURWDY0 (ISP3X_BAY3D_BASE + 0x00074)
+#define ISP39_BAY3D_CURWDY1 (ISP3X_BAY3D_BASE + 0x00078)
+#define ISP39_BAY3D_CURWDY2 (ISP3X_BAY3D_BASE + 0x0007c)
+#define ISP39_BAY3D_IIRDGAIN (ISP3X_BAY3D_BASE + 0x00080)
+#define ISP39_BAY3D_IIRSIG_X0 (ISP3X_BAY3D_BASE + 0x00084)
+#define ISP39_BAY3D_IIRSIG_X1 (ISP3X_BAY3D_BASE + 0x00088)
+#define ISP39_BAY3D_IIRSIG_X2 (ISP3X_BAY3D_BASE + 0x0008c)
+#define ISP39_BAY3D_IIRSIG_X3 (ISP3X_BAY3D_BASE + 0x00090)
+#define ISP39_BAY3D_IIRSIG_X4 (ISP3X_BAY3D_BASE + 0x00094)
+#define ISP39_BAY3D_IIRSIG_X5 (ISP3X_BAY3D_BASE + 0x00098)
+#define ISP39_BAY3D_IIRSIG_X6 (ISP3X_BAY3D_BASE + 0x0009c)
+#define ISP39_BAY3D_IIRSIG_X7 (ISP3X_BAY3D_BASE + 0x000a0)
+#define ISP39_BAY3D_IIRSIG_Y0 (ISP3X_BAY3D_BASE + 0x000a4)
+#define ISP39_BAY3D_IIRSIG_Y1 (ISP3X_BAY3D_BASE + 0x000a8)
+#define ISP39_BAY3D_IIRSIG_Y2 (ISP3X_BAY3D_BASE + 0x000ac)
+#define ISP39_BAY3D_IIRSIG_Y3 (ISP3X_BAY3D_BASE + 0x000b0)
+#define ISP39_BAY3D_IIRSIG_Y4 (ISP3X_BAY3D_BASE + 0x000b4)
+#define ISP39_BAY3D_IIRSIG_Y5 (ISP3X_BAY3D_BASE + 0x000b8)
+#define ISP39_BAY3D_IIRSIG_Y6 (ISP3X_BAY3D_BASE + 0x000bc)
+#define ISP39_BAY3D_IIRSIG_Y7 (ISP3X_BAY3D_BASE + 0x000c0)
+#define ISP39_BAY3D_IIRGAIN_OFF (ISP3X_BAY3D_BASE + 0x000c4)
+#define ISP39_BAY3D_IIRSIG_OFF (ISP3X_BAY3D_BASE + 0x000c8)
+#define ISP39_BAY3D_IIRWTH (ISP3X_BAY3D_BASE + 0x000cc)
+#define ISP39_BAY3D_IIRWDC0 (ISP3X_BAY3D_BASE + 0x000d0)
+#define ISP39_BAY3D_IIRWDC1 (ISP3X_BAY3D_BASE + 0x000d4)
+#define ISP39_BAY3D_IIRWDC2 (ISP3X_BAY3D_BASE + 0x000d8)
+#define ISP39_BAY3D_IIRWDY0 (ISP3X_BAY3D_BASE + 0x000dc)
+#define ISP39_BAY3D_IIRWDY1 (ISP3X_BAY3D_BASE + 0x000e0)
+#define ISP39_BAY3D_IIRWDY2 (ISP3X_BAY3D_BASE + 0x000e4)
+#define ISP39_BAY3D_BFCOEF (ISP3X_BAY3D_BASE + 0x000e8)
+/* BAY3D_3A00 */
+#define ISP39_BAY3D_TNRSIG_X0 (ISP3X_BAYNR_BASE + 0x00000)
+#define ISP39_BAY3D_TNRSIG_X1 (ISP3X_BAYNR_BASE + 0x00004)
+#define ISP39_BAY3D_TNRSIG_X2 (ISP3X_BAYNR_BASE + 0x00008)
+#define ISP39_BAY3D_TNRSIG_X3 (ISP3X_BAYNR_BASE + 0x0000c)
+#define ISP39_BAY3D_TNRSIG_X4 (ISP3X_BAYNR_BASE + 0x00010)
+#define ISP39_BAY3D_TNRSIG_X5 (ISP3X_BAYNR_BASE + 0x00014)
+#define ISP39_BAY3D_TNRSIG_X6 (ISP3X_BAYNR_BASE + 0x00018)
+#define ISP39_BAY3D_TNRSIG_X7 (ISP3X_BAYNR_BASE + 0x0001c)
+#define ISP39_BAY3D_TNRSIG_X8 (ISP3X_BAYNR_BASE + 0x00020)
+#define ISP39_BAY3D_TNRSIG_X9 (ISP3X_BAYNR_BASE + 0x00024)
+#define ISP39_BAY3D_TNRSIG_Y0 (ISP3X_BAYNR_BASE + 0x00028)
+#define ISP39_BAY3D_TNRSIG_Y1 (ISP3X_BAYNR_BASE + 0x0002c)
+#define ISP39_BAY3D_TNRSIG_Y2 (ISP3X_BAYNR_BASE + 0x00030)
+#define ISP39_BAY3D_TNRSIG_Y3 (ISP3X_BAYNR_BASE + 0x00034)
+#define ISP39_BAY3D_TNRSIG_Y4 (ISP3X_BAYNR_BASE + 0x00038)
+#define ISP39_BAY3D_TNRSIG_Y5 (ISP3X_BAYNR_BASE + 0x0003c)
+#define ISP39_BAY3D_TNRSIG_Y6 (ISP3X_BAYNR_BASE + 0x00040)
+#define ISP39_BAY3D_TNRSIG_Y7 (ISP3X_BAYNR_BASE + 0x00044)
+#define ISP39_BAY3D_TNRSIG_Y8 (ISP3X_BAYNR_BASE + 0x00048)
+#define ISP39_BAY3D_TNRSIG_Y9 (ISP3X_BAYNR_BASE + 0x0004c)
+#define ISP39_BAY3D_TNRHIW0 (ISP3X_BAYNR_BASE + 0x00050)
+#define ISP39_BAY3D_TNRHIW1 (ISP3X_BAYNR_BASE + 0x00054)
+#define ISP39_BAY3D_TNRHIW2 (ISP3X_BAYNR_BASE + 0x00058)
+#define ISP39_BAY3D_TNRLOW0 (ISP3X_BAYNR_BASE + 0x0005c)
+#define ISP39_BAY3D_TNRLOW1 (ISP3X_BAYNR_BASE + 0x00060)
+#define ISP39_BAY3D_TNRLOW2 (ISP3X_BAYNR_BASE + 0x00064)
+#define ISP39_BAY3D_TNRGF3 (ISP3X_BAYNR_BASE + 0x00068)
+#define ISP39_BAY3D_TNRSIGSCL (ISP3X_BAYNR_BASE + 0x0006c)
+#define ISP39_BAY3D_TNRVIIR (ISP3X_BAYNR_BASE + 0x00070)
+#define ISP39_BAY3D_TNRLFSCL (ISP3X_BAYNR_BASE + 0x00074)
+#define ISP39_BAY3D_TNRLFSCLTH (ISP3X_BAYNR_BASE + 0x00078)
+#define ISP39_BAY3D_TNRDSWGTSCL (ISP3X_BAYNR_BASE + 0x0007c)
+#define ISP39_BAY3D_TNRWLSTSCL (ISP3X_BAYNR_BASE + 0x00080)
+#define ISP39_BAY3D_TNRWGT0SCL0 (ISP3X_BAYNR_BASE + 0x00084)
+#define ISP39_BAY3D_TNRWGT1SCL1 (ISP3X_BAYNR_BASE + 0x00088)
+#define ISP39_BAY3D_TNRWGT1SCL2 (ISP3X_BAYNR_BASE + 0x0008c)
+#define ISP39_BAY3D_TNRWGTOFF (ISP3X_BAYNR_BASE + 0x00090)
+#define ISP39_BAY3D_TNRWGT1OFF (ISP3X_BAYNR_BASE + 0x00094)
+#define ISP39_BAY3D_TNRSIGORG (ISP3X_BAYNR_BASE + 0x00098)
+#define ISP39_BAY3D_TNRWLO_THL (ISP3X_BAYNR_BASE + 0x0009c)
+#define ISP39_BAY3D_TNRWLO_THH (ISP3X_BAYNR_BASE + 0x000a0)
+#define ISP39_BAY3D_TNRWHI_THL (ISP3X_BAYNR_BASE + 0x000a4)
+#define ISP39_BAY3D_TNRWHI_THH (ISP3X_BAYNR_BASE + 0x000a8)
+#define ISP39_BAY3D_TNRKEEP (ISP3X_BAYNR_BASE + 0x000ac)
+#define ISP39_BAY3D_PIXMAX (ISP3X_BAYNR_BASE + 0x000b0)
+#define ISP39_BAY3D_SIGNUMTH (ISP3X_BAYNR_BASE + 0x000b4)
+#define ISP39_BAY3D_TNRMO_STR (ISP3X_BAYNR_BASE + 0x000b8)
+#define ISP39_BAY3D_SIGSUM (ISP3X_BAYNR_BASE + 0x000d4)
+#define ISP39_BAY3D_TNRSIGYO0 (ISP3X_BAYNR_BASE + 0x000d8)
+#define ISP39_BAY3D_TNRSIGYO1 (ISP3X_BAYNR_BASE + 0x000dc)
+#define ISP39_BAY3D_TNRSIGYO2 (ISP3X_BAYNR_BASE + 0x000e0)
+#define ISP39_BAY3D_TNRSIGYO3 (ISP3X_BAYNR_BASE + 0x000e4)
+#define ISP39_BAY3D_TNRSIGYO4 (ISP3X_BAYNR_BASE + 0x000e8)
+#define ISP39_BAY3D_TNRSIGYO5 (ISP3X_BAYNR_BASE + 0x000ec)
+#define ISP39_BAY3D_TNRSIGYO6 (ISP3X_BAYNR_BASE + 0x000f0)
+#define ISP39_BAY3D_TNRSIGYO7 (ISP3X_BAYNR_BASE + 0x000f4)
+#define ISP39_BAY3D_TNRSIGYO8 (ISP3X_BAYNR_BASE + 0x000f8)
+#define ISP39_BAY3D_TNRSIGYO9 (ISP3X_BAYNR_BASE + 0x000fc)
+
+#define ISP39_RGBIR_BASE 0x00002E00
+#define ISP39_RGBIR_CTRL (ISP39_RGBIR_BASE + 0x00000)
+#define ISP39_RGBIR_THETA (ISP39_RGBIR_BASE + 0x00004)
+#define ISP39_RGBIR_DELTA (ISP39_RGBIR_BASE + 0x00008)
+#define ISP39_RGBIR_SCALE0 (ISP39_RGBIR_BASE + 0x0000c)
+#define ISP39_RGBIR_SCALE1 (ISP39_RGBIR_BASE + 0x00010)
+#define ISP39_RGBIR_SCALE2 (ISP39_RGBIR_BASE + 0x00014)
+#define ISP39_RGBIR_SCALE3 (ISP39_RGBIR_BASE + 0x00018)
+#define ISP39_RGBIR_LUMA_POINT0 (ISP39_RGBIR_BASE + 0x0001c)
+#define ISP39_RGBIR_LUMA_POINT1 (ISP39_RGBIR_BASE + 0x00020)
+#define ISP39_RGBIR_LUMA_POINT2 (ISP39_RGBIR_BASE + 0x00024)
+#define ISP39_RGBIR_LUMA_POINT3 (ISP39_RGBIR_BASE + 0x00028)
+#define ISP39_RGBIR_LUMA_POINT4 (ISP39_RGBIR_BASE + 0x0002c)
+#define ISP39_RGBIR_LUMA_POINT5 (ISP39_RGBIR_BASE + 0x00030)
+#define ISP39_RGBIR_SCALE_MAP0 (ISP39_RGBIR_BASE + 0x00034)
+#define ISP39_RGBIR_SCALE_MAP1 (ISP39_RGBIR_BASE + 0x00038)
+#define ISP39_RGBIR_SCALE_MAP2 (ISP39_RGBIR_BASE + 0x0003c)
+#define ISP39_RGBIR_SCALE_MAP3 (ISP39_RGBIR_BASE + 0x00040)
+#define ISP39_RGBIR_SCALE_MAP4 (ISP39_RGBIR_BASE + 0x00044)
+#define ISP39_RGBIR_SCALE_MAP5 (ISP39_RGBIR_BASE + 0x00048)
+
+#define ISP3X_GIC_BASE 0x00002F00
+#define ISP3X_GIC_CONTROL (ISP3X_GIC_BASE + 0x00000)
+#define ISP3X_GIC_DIFF_PARA1 (ISP3X_GIC_BASE + 0x00004)
+#define ISP3X_GIC_DIFF_PARA2 (ISP3X_GIC_BASE + 0x00008)
+#define ISP3X_GIC_DIFF_PARA3 (ISP3X_GIC_BASE + 0x0000c)
+#define ISP3X_GIC_DIFF_PARA4 (ISP3X_GIC_BASE + 0x00010)
+#define ISP3X_GIC_NOISE_PARA1 (ISP3X_GIC_BASE + 0x00014)
+#define ISP3X_GIC_NOISE_PARA2 (ISP3X_GIC_BASE + 0x00018)
+#define ISP3X_GIC_NOISE_PARA3 (ISP3X_GIC_BASE + 0x0001c)
+#define ISP3X_GIC_SIGMA_VALUE0 (ISP3X_GIC_BASE + 0x00020)
+#define ISP3X_GIC_SIGMA_VALUE1 (ISP3X_GIC_BASE + 0x00024)
+#define ISP3X_GIC_SIGMA_VALUE2 (ISP3X_GIC_BASE + 0x00028)
+#define ISP3X_GIC_SIGMA_VALUE3 (ISP3X_GIC_BASE + 0x0002c)
+#define ISP3X_GIC_SIGMA_VALUE4 (ISP3X_GIC_BASE + 0x00030)
+#define ISP3X_GIC_SIGMA_VALUE5 (ISP3X_GIC_BASE + 0x00034)
+#define ISP3X_GIC_SIGMA_VALUE6 (ISP3X_GIC_BASE + 0x00038)
+#define ISP3X_GIC_SIGMA_VALUE7 (ISP3X_GIC_BASE + 0x0003c)
+#define ISP33_GIC_MEDFLT_PARA (ISP3X_GIC_BASE + 0x00004)
+#define ISP33_GIC_MEDFLTUV_PARA (ISP3X_GIC_BASE + 0x00008)
+#define ISP33_GIC_NOISE_SCALE (ISP3X_GIC_BASE + 0x0000c)
+#define ISP33_GIC_BILAT_PARA1 (ISP3X_GIC_BASE + 0x00010)
+#define ISP33_GIC_BILAT_PARA2 (ISP3X_GIC_BASE + 0x00014)
+#define ISP33_GIC_DISWGT_COEFF (ISP3X_GIC_BASE + 0x00018)
+#define ISP33_GIC_SIGMA_Y0 (ISP3X_GIC_BASE + 0x00020)
+#define ISP33_GIC_SIGMA_Y8 (ISP3X_GIC_BASE + 0x00040)
+#define ISP33_GIC_LUMA_DX (ISP3X_GIC_BASE + 0x00044)
+#define ISP33_GIC_THRED_Y0 (ISP3X_GIC_BASE + 0x00050)
+#define ISP33_GIC_MIN_THRED_Y0 (ISP3X_GIC_BASE + 0x00060)
+#define ISP33_GIC_THRED_SCALE (ISP3X_GIC_BASE + 0x00070)
+#define ISP33_GIC_LOFLTGR_COEFF (ISP3X_GIC_BASE + 0x00074)
+#define ISP33_GIC_LOFLTGB_COEFF (ISP3X_GIC_BASE + 0x00078)
+#define ISP33_GIC_SUM_LOFLT_INV (ISP3X_GIC_BASE + 0x0007c)
+#define ISP33_GIC_LOFLTTHRED_COEFF (ISP3X_GIC_BASE + 0x00080)
+#define ISP33_GIC_GAIN (ISP3X_GIC_BASE + 0x00090)
+#define ISP33_GIC_GAIN_SLOPE (ISP3X_GIC_BASE + 0x00094)
+#define ISP33_GIC_GAIN_THRED (ISP3X_GIC_BASE + 0x00098)
+
+#define ISP3X_BLS_BASE 0x00003000
+#define ISP3X_BLS_CTRL (ISP3X_BLS_BASE + 0x00000)
+#define ISP3X_BLS_SAMPLES (ISP3X_BLS_BASE + 0x00004)
+#define ISP3X_BLS_H1_START (ISP3X_BLS_BASE + 0x00008)
+#define ISP3X_BLS_H1_STOP (ISP3X_BLS_BASE + 0x0000c)
+#define ISP3X_BLS_V1_START (ISP3X_BLS_BASE + 0x00010)
+#define ISP3X_BLS_V1_STOP (ISP3X_BLS_BASE + 0x00014)
+#define ISP3X_BLS_H2_START (ISP3X_BLS_BASE + 0x00018)
+#define ISP3X_BLS_H2_STOP (ISP3X_BLS_BASE + 0x0001c)
+#define ISP3X_BLS_V2_START (ISP3X_BLS_BASE + 0x00020)
+#define ISP3X_BLS_V2_STOP (ISP3X_BLS_BASE + 0x00024)
+#define ISP3X_BLS_A_FIXED (ISP3X_BLS_BASE + 0x00028)
+#define ISP3X_BLS_B_FIXED (ISP3X_BLS_BASE + 0x0002c)
+#define ISP3X_BLS_C_FIXED (ISP3X_BLS_BASE + 0x00030)
+#define ISP3X_BLS_D_FIXED (ISP3X_BLS_BASE + 0x00034)
+#define ISP3X_BLS_A_MEASURED (ISP3X_BLS_BASE + 0x00038)
+#define ISP3X_BLS_B_MEASURED (ISP3X_BLS_BASE + 0x0003c)
+#define ISP3X_BLS_C_MEASURED (ISP3X_BLS_BASE + 0x00040)
+#define ISP3X_BLS_D_MEASURED (ISP3X_BLS_BASE + 0x00044)
+#define ISP3X_BLS1_A_FIXED (ISP3X_BLS_BASE + 0x00048)
+#define ISP3X_BLS1_B_FIXED (ISP3X_BLS_BASE + 0x0004c)
+#define ISP3X_BLS1_C_FIXED (ISP3X_BLS_BASE + 0x00050)
+#define ISP3X_BLS1_D_FIXED (ISP3X_BLS_BASE + 0x00054)
+#define ISP32_BLS2_A_FIXED (ISP3X_BLS_BASE + 0x00058)
+#define ISP32_BLS2_B_FIXED (ISP3X_BLS_BASE + 0x0005c)
+#define ISP32_BLS2_C_FIXED (ISP3X_BLS_BASE + 0x00060)
+#define ISP32_BLS2_D_FIXED (ISP3X_BLS_BASE + 0x00064)
+#define ISP32_BLS_ISP_OB_OFFSET (ISP3X_BLS_BASE + 0x00068)
+#define ISP32_BLS_ISP_OB_PREDGAIN (ISP3X_BLS_BASE + 0x0006c)
+#define ISP32_BLS_ISP_OB_MAX (ISP3X_BLS_BASE + 0x00070)
+#define ISP35_BLS3_AB_FIXED (ISP3X_BLS_BASE + 0x00074)
+#define ISP35_BLS3_CD_FIXED (ISP3X_BLS_BASE + 0x00078)
+
+#define ISP39_EXPD_BASE 0x00003100
+#define ISP39_EXPD_K15 (ISP39_EXPD_BASE + 0x00000)
+#define ISP39_EXPD_K16 (ISP39_EXPD_BASE + 0x00004)
+#define ISP39_EXPD_K17 (ISP39_EXPD_BASE + 0x00008)
+#define ISP39_EXPD_K18 (ISP39_EXPD_BASE + 0x0000c)
+#define ISP39_EXPD_K19 (ISP39_EXPD_BASE + 0x00010)
+#define ISP39_EXPD_K20 (ISP39_EXPD_BASE + 0x00014)
+#define ISP39_EXPD_K21 (ISP39_EXPD_BASE + 0x00018)
+#define ISP39_EXPD_K22 (ISP39_EXPD_BASE + 0x0001c)
+#define ISP39_EXPD_K23 (ISP39_EXPD_BASE + 0x00020)
+#define ISP39_EXPD_K24 (ISP39_EXPD_BASE + 0x00024)
+#define ISP39_EXPD_K25 (ISP39_EXPD_BASE + 0x00028)
+#define ISP39_EXPD_K26 (ISP39_EXPD_BASE + 0x0002c)
+#define ISP39_EXPD_K27 (ISP39_EXPD_BASE + 0x00030)
+#define ISP39_EXPD_K28 (ISP39_EXPD_BASE + 0x00034)
+#define ISP39_EXPD_K29 (ISP39_EXPD_BASE + 0x00038)
+#define ISP39_EXPD_K30 (ISP39_EXPD_BASE + 0x0003c)
+#define ISP39_EXPD_K31 (ISP39_EXPD_BASE + 0x00040)
+#define ISP39_EXPD_IMAX (ISP39_EXPD_BASE + 0x00044)
+#define ISP39_EXPD_OMAX (ISP39_EXPD_BASE + 0x00048)
+#define ISP39_EXPD_CTRL (ISP39_EXPD_BASE + 0x00100)
+#define ISP39_EXPD_X00_01 (ISP39_EXPD_BASE + 0x00104)
+#define ISP39_EXPD_X02_03 (ISP39_EXPD_BASE + 0x00108)
+#define ISP39_EXPD_X04_05 (ISP39_EXPD_BASE + 0x0010C)
+#define ISP39_EXPD_X06_07 (ISP39_EXPD_BASE + 0x00110)
+#define ISP39_EXPD_X08_09 (ISP39_EXPD_BASE + 0x00114)
+#define ISP39_EXPD_X10_11 (ISP39_EXPD_BASE + 0x00118)
+#define ISP39_EXPD_X12_13 (ISP39_EXPD_BASE + 0x0011C)
+#define ISP39_EXPD_X14_15 (ISP39_EXPD_BASE + 0x00120)
+#define ISP39_EXPD_X16_17 (ISP39_EXPD_BASE + 0x00124)
+#define ISP39_EXPD_X18_19 (ISP39_EXPD_BASE + 0x00128)
+#define ISP39_EXPD_X20_21 (ISP39_EXPD_BASE + 0x0012c)
+#define ISP39_EXPD_X22_23 (ISP39_EXPD_BASE + 0x00130)
+#define ISP39_EXPD_X24_25 (ISP39_EXPD_BASE + 0x00134)
+#define ISP39_EXPD_X26_27 (ISP39_EXPD_BASE + 0x00138)
+#define ISP39_EXPD_X28_29 (ISP39_EXPD_BASE + 0x0013c)
+#define ISP39_EXPD_X30_31 (ISP39_EXPD_BASE + 0x00140)
+#define ISP39_EXPD_Y0 (ISP39_EXPD_BASE + 0x00144)
+#define ISP39_EXPD_Y1 (ISP39_EXPD_BASE + 0x00148)
+#define ISP39_EXPD_Y2 (ISP39_EXPD_BASE + 0x0014c)
+#define ISP39_EXPD_Y3 (ISP39_EXPD_BASE + 0x00150)
+#define ISP39_EXPD_Y4 (ISP39_EXPD_BASE + 0x00154)
+#define ISP39_EXPD_Y5 (ISP39_EXPD_BASE + 0x00158)
+#define ISP39_EXPD_Y6 (ISP39_EXPD_BASE + 0x0015c)
+#define ISP39_EXPD_Y7 (ISP39_EXPD_BASE + 0x00160)
+#define ISP39_EXPD_Y8 (ISP39_EXPD_BASE + 0x00164)
+#define ISP39_EXPD_Y9 (ISP39_EXPD_BASE + 0x00168)
+#define ISP39_EXPD_Y10 (ISP39_EXPD_BASE + 0x0016c)
+#define ISP39_EXPD_Y11 (ISP39_EXPD_BASE + 0x00170)
+#define ISP39_EXPD_Y12 (ISP39_EXPD_BASE + 0x00174)
+#define ISP39_EXPD_Y13 (ISP39_EXPD_BASE + 0x00178)
+#define ISP39_EXPD_Y14 (ISP39_EXPD_BASE + 0x0017c)
+#define ISP39_EXPD_Y15 (ISP39_EXPD_BASE + 0x00180)
+#define ISP39_EXPD_Y16 (ISP39_EXPD_BASE + 0x00184)
+#define ISP39_EXPD_Y17 (ISP39_EXPD_BASE + 0x00188)
+#define ISP39_EXPD_Y18 (ISP39_EXPD_BASE + 0x0018c)
+#define ISP39_EXPD_Y19 (ISP39_EXPD_BASE + 0x00190)
+#define ISP39_EXPD_Y20 (ISP39_EXPD_BASE + 0x00194)
+#define ISP39_EXPD_Y21 (ISP39_EXPD_BASE + 0x00198)
+#define ISP39_EXPD_Y22 (ISP39_EXPD_BASE + 0x0019c)
+#define ISP39_EXPD_Y23 (ISP39_EXPD_BASE + 0x001a0)
+#define ISP39_EXPD_Y24 (ISP39_EXPD_BASE + 0x001a4)
+#define ISP39_EXPD_Y25 (ISP39_EXPD_BASE + 0x001a8)
+#define ISP39_EXPD_Y26 (ISP39_EXPD_BASE + 0x001ac)
+#define ISP39_EXPD_Y27 (ISP39_EXPD_BASE + 0x001b0)
+#define ISP39_EXPD_Y28 (ISP39_EXPD_BASE + 0x001b4)
+#define ISP39_EXPD_Y29 (ISP39_EXPD_BASE + 0x001b8)
+#define ISP39_EXPD_Y30 (ISP39_EXPD_BASE + 0x001bc)
+#define ISP39_EXPD_Y31 (ISP39_EXPD_BASE + 0x001c0)
+#define ISP39_EXPD_K0 (ISP39_EXPD_BASE + 0x001c4)
+#define ISP39_EXPD_K1 (ISP39_EXPD_BASE + 0x001c8)
+#define ISP39_EXPD_K2 (ISP39_EXPD_BASE + 0x001cc)
+#define ISP39_EXPD_K3 (ISP39_EXPD_BASE + 0x001d0)
+#define ISP39_EXPD_K4 (ISP39_EXPD_BASE + 0x001d4)
+#define ISP39_EXPD_K5 (ISP39_EXPD_BASE + 0x001d8)
+#define ISP39_EXPD_K6 (ISP39_EXPD_BASE + 0x001dc)
+#define ISP39_EXPD_K7 (ISP39_EXPD_BASE + 0x001e0)
+#define ISP39_EXPD_K8 (ISP39_EXPD_BASE + 0x001e4)
+#define ISP39_EXPD_K9 (ISP39_EXPD_BASE + 0x001e8)
+#define ISP39_EXPD_K10 (ISP39_EXPD_BASE + 0x001ec)
+#define ISP39_EXPD_K11 (ISP39_EXPD_BASE + 0x001f0)
+#define ISP39_EXPD_K12 (ISP39_EXPD_BASE + 0x001f4)
+#define ISP39_EXPD_K13 (ISP39_EXPD_BASE + 0x001f8)
+#define ISP39_EXPD_K14 (ISP39_EXPD_BASE + 0x001fc)
+
+#define ISP32_EXPD_BASE 0x00003200
+#define ISP32_EXPD_CTRL (ISP32_EXPD_BASE + 0x00000)
+#define ISP32_EXPD_X00_01 (ISP32_EXPD_BASE + 0x00004)
+#define ISP32_EXPD_X02_03 (ISP32_EXPD_BASE + 0x00008)
+#define ISP32_EXPD_X04_05 (ISP32_EXPD_BASE + 0x0000C)
+#define ISP32_EXPD_X06_07 (ISP32_EXPD_BASE + 0x00010)
+#define ISP32_EXPD_X08_09 (ISP32_EXPD_BASE + 0x00014)
+#define ISP32_EXPD_X10_11 (ISP32_EXPD_BASE + 0x00018)
+#define ISP32_EXPD_X12_13 (ISP32_EXPD_BASE + 0x0001C)
+#define ISP32_EXPD_X14_15 (ISP32_EXPD_BASE + 0x00020)
+#define ISP32_EXPD_Y00_01 (ISP32_EXPD_BASE + 0x00024)
+#define ISP32_EXPD_Y02_03 (ISP32_EXPD_BASE + 0x00028)
+#define ISP32_EXPD_Y04_05 (ISP32_EXPD_BASE + 0x0002C)
+#define ISP32_EXPD_Y06_07 (ISP32_EXPD_BASE + 0x00030)
+#define ISP32_EXPD_Y08_09 (ISP32_EXPD_BASE + 0x00034)
+#define ISP32_EXPD_Y10_11 (ISP32_EXPD_BASE + 0x00038)
+#define ISP32_EXPD_Y12_13 (ISP32_EXPD_BASE + 0x0003C)
+#define ISP32_EXPD_Y14_15 (ISP32_EXPD_BASE + 0x00040)
+#define ISP32_EXPD_Y16 (ISP32_EXPD_BASE + 0x00044)
+#define ISP32_EXPD_K0 (ISP32_EXPD_BASE + 0x00048)
+#define ISP32_EXPD_K1 (ISP32_EXPD_BASE + 0x0004c)
+#define ISP32_EXPD_K2 (ISP32_EXPD_BASE + 0x00050)
+#define ISP32_EXPD_K3 (ISP32_EXPD_BASE + 0x00054)
+#define ISP32_EXPD_K4 (ISP32_EXPD_BASE + 0x00058)
+#define ISP32_EXPD_K5 (ISP32_EXPD_BASE + 0x0005C)
+#define ISP32_EXPD_K6 (ISP32_EXPD_BASE + 0x00060)
+#define ISP32_EXPD_K7 (ISP32_EXPD_BASE + 0x00064)
+#define ISP32_EXPD_K8 (ISP32_EXPD_BASE + 0x00068)
+#define ISP32_EXPD_K9 (ISP32_EXPD_BASE + 0x0006C)
+#define ISP32_EXPD_K10 (ISP32_EXPD_BASE + 0x00070)
+#define ISP32_EXPD_K11 (ISP32_EXPD_BASE + 0x00074)
+#define ISP32_EXPD_K12 (ISP32_EXPD_BASE + 0x00078)
+#define ISP32_EXPD_K13 (ISP32_EXPD_BASE + 0x0007C)
+#define ISP32_EXPD_K14 (ISP32_EXPD_BASE + 0x00080)
+#define ISP32_EXPD_K15 (ISP32_EXPD_BASE + 0x00084)
+
+#define ISP32_VSM_BASE 0x00003380
+#define ISP32_VSM_MODE (ISP32_VSM_BASE + 0x00000)
+#define ISP32_VSM_H_OFFS (ISP32_VSM_BASE + 0x00004)
+#define ISP32_VSM_V_OFFS (ISP32_VSM_BASE + 0x00008)
+#define ISP32_VSM_H_SIZE (ISP32_VSM_BASE + 0x0000C)
+#define ISP32_VSM_V_SIZE (ISP32_VSM_BASE + 0x00010)
+#define ISP32_VSM_H_SEGMENTS (ISP32_VSM_BASE + 0x00014)
+#define ISP32_VSM_V_SEGMENTS (ISP32_VSM_BASE + 0x00018)
+#define ISP32_VSM_DELTA_H (ISP32_VSM_BASE + 0x0001C)
+#define ISP32_VSM_DELTA_V (ISP32_VSM_BASE + 0x00020)
+
+#define ISP3X_DPCC0_BASE 0x00003400
+#define ISP3X_DPCC1_BASE 0x00003500
+#define ISP3X_DPCC2_BASE 0x00003600
+#define ISP3X_DPCC0_MODE (ISP3X_DPCC0_BASE + 0x00000)
+#define ISP3X_DPCC0_OUTPUT_MODE (ISP3X_DPCC0_BASE + 0x00004)
+#define ISP3X_DPCC0_SET_USE (ISP3X_DPCC0_BASE + 0x00008)
+#define ISP3X_DPCC0_METHODS_SET_1 (ISP3X_DPCC0_BASE + 0x0000c)
+#define ISP3X_DPCC0_METHODS_SET_2 (ISP3X_DPCC0_BASE + 0x00010)
+#define ISP3X_DPCC0_METHODS_SET_3 (ISP3X_DPCC0_BASE + 0x00014)
+#define ISP3X_DPCC0_LINE_THRESH_1 (ISP3X_DPCC0_BASE + 0x00018)
+#define ISP3X_DPCC0_LINE_MAD_FAC_1 (ISP3X_DPCC0_BASE + 0x0001c)
+#define ISP3X_DPCC0_PG_FAC_1 (ISP3X_DPCC0_BASE + 0x00020)
+#define ISP3X_DPCC0_RND_THRESH_1 (ISP3X_DPCC0_BASE + 0x00024)
+#define ISP3X_DPCC0_RG_FAC_1 (ISP3X_DPCC0_BASE + 0x00028)
+#define ISP3X_DPCC0_LINE_THRESH_2 (ISP3X_DPCC0_BASE + 0x0002c)
+#define ISP3X_DPCC0_LINE_MAD_FAC_2 (ISP3X_DPCC0_BASE + 0x00030)
+#define ISP3X_DPCC0_PG_FAC_2 (ISP3X_DPCC0_BASE + 0x00034)
+#define ISP3X_DPCC0_RND_THRESH_2 (ISP3X_DPCC0_BASE + 0x00038)
+#define ISP3X_DPCC0_RG_FAC_2 (ISP3X_DPCC0_BASE + 0x0003c)
+#define ISP3X_DPCC0_LINE_THRESH_3 (ISP3X_DPCC0_BASE + 0x00040)
+#define ISP3X_DPCC0_LINE_MAD_FAC_3 (ISP3X_DPCC0_BASE + 0x00044)
+#define ISP3X_DPCC0_PG_FAC_3 (ISP3X_DPCC0_BASE + 0x00048)
+#define ISP3X_DPCC0_RND_THRESH_3 (ISP3X_DPCC0_BASE + 0x0004c)
+#define ISP3X_DPCC0_RG_FAC_3 (ISP3X_DPCC0_BASE + 0x00050)
+#define ISP3X_DPCC0_RO_LIMITS (ISP3X_DPCC0_BASE + 0x00054)
+#define ISP3X_DPCC0_RND_OFFS (ISP3X_DPCC0_BASE + 0x00058)
+#define ISP3X_DPCC0_BPT_CTRL (ISP3X_DPCC0_BASE + 0x0005c)
+#define ISP3X_DPCC0_BPT_NUMBER (ISP3X_DPCC0_BASE + 0x00060)
+#define ISP3X_DPCC0_BPT_ADDR (ISP3X_DPCC0_BASE + 0x00064)
+#define ISP3X_DPCC0_BPT_DATA (ISP3X_DPCC0_BASE + 0x00068)
+#define ISP3X_DPCC0_BP_CNT (ISP3X_DPCC0_BASE + 0x0006c)
+#define ISP3X_DPCC0_PDAF_EN (ISP3X_DPCC0_BASE + 0x00070)
+#define ISP3X_DPCC0_PDAF_POINT_EN (ISP3X_DPCC0_BASE + 0x00074)
+#define ISP3X_DPCC0_PDAF_OFFSET (ISP3X_DPCC0_BASE + 0x00078)
+#define ISP3X_DPCC0_PDAF_WRAP (ISP3X_DPCC0_BASE + 0x0007c)
+#define ISP3X_DPCC0_PDAF_SCOPE (ISP3X_DPCC0_BASE + 0x00080)
+#define ISP3X_DPCC0_PDAF_POINT_0 (ISP3X_DPCC0_BASE + 0x00084)
+#define ISP3X_DPCC0_PDAF_POINT_1 (ISP3X_DPCC0_BASE + 0x00088)
+#define ISP3X_DPCC0_PDAF_POINT_2 (ISP3X_DPCC0_BASE + 0x0008c)
+#define ISP3X_DPCC0_PDAF_POINT_3 (ISP3X_DPCC0_BASE + 0x00090)
+#define ISP3X_DPCC0_PDAF_POINT_4 (ISP3X_DPCC0_BASE + 0x00094)
+#define ISP3X_DPCC0_PDAF_POINT_5 (ISP3X_DPCC0_BASE + 0x00098)
+#define ISP3X_DPCC0_PDAF_POINT_6 (ISP3X_DPCC0_BASE + 0x0009c)
+#define ISP3X_DPCC0_PDAF_POINT_7 (ISP3X_DPCC0_BASE + 0x000a0)
+#define ISP3X_DPCC0_PDAF_FORWARD_MED (ISP3X_DPCC0_BASE + 0x000a4)
+
+#define ISP3X_DPCC1_MODE (ISP3X_DPCC1_BASE + 0x00000)
+#define ISP3X_DPCC1_OUTPUT_MODE (ISP3X_DPCC1_BASE + 0x00004)
+#define ISP3X_DPCC1_SET_USE (ISP3X_DPCC1_BASE + 0x00008)
+#define ISP3X_DPCC1_METHODS_SET_1 (ISP3X_DPCC1_BASE + 0x0000c)
+#define ISP3X_DPCC1_METHODS_SET_2 (ISP3X_DPCC1_BASE + 0x00010)
+#define ISP3X_DPCC1_METHODS_SET_3 (ISP3X_DPCC1_BASE + 0x00014)
+#define ISP3X_DPCC1_LINE_THRESH_1 (ISP3X_DPCC1_BASE + 0x00018)
+#define ISP3X_DPCC1_LINE_MAD_FAC_1 (ISP3X_DPCC1_BASE + 0x0001c)
+#define ISP3X_DPCC1_PG_FAC_1 (ISP3X_DPCC1_BASE + 0x00020)
+#define ISP3X_DPCC1_RND_THRESH_1 (ISP3X_DPCC1_BASE + 0x00024)
+#define ISP3X_DPCC1_RG_FAC_1 (ISP3X_DPCC1_BASE + 0x00028)
+#define ISP3X_DPCC1_LINE_THRESH_2 (ISP3X_DPCC1_BASE + 0x0002c)
+#define ISP3X_DPCC1_LINE_MAD_FAC_2 (ISP3X_DPCC1_BASE + 0x00030)
+#define ISP3X_DPCC1_PG_FAC_2 (ISP3X_DPCC1_BASE + 0x00034)
+#define ISP3X_DPCC1_RND_THRESH_2 (ISP3X_DPCC1_BASE + 0x00038)
+#define ISP3X_DPCC1_RG_FAC_2 (ISP3X_DPCC1_BASE + 0x0003c)
+#define ISP3X_DPCC1_LINE_THRESH_3 (ISP3X_DPCC1_BASE + 0x00040)
+#define ISP3X_DPCC1_LINE_MAD_FAC_3 (ISP3X_DPCC1_BASE + 0x00044)
+#define ISP3X_DPCC1_PG_FAC_3 (ISP3X_DPCC1_BASE + 0x00048)
+#define ISP3X_DPCC1_RND_THRESH_3 (ISP3X_DPCC1_BASE + 0x0004c)
+#define ISP3X_DPCC1_RG_FAC_3 (ISP3X_DPCC1_BASE + 0x00050)
+#define ISP3X_DPCC1_RO_LIMITS (ISP3X_DPCC1_BASE + 0x00054)
+#define ISP3X_DPCC1_RND_OFFS (ISP3X_DPCC1_BASE + 0x00058)
+#define ISP3X_DPCC1_BPT_CTRL (ISP3X_DPCC1_BASE + 0x0005c)
+#define ISP3X_DPCC1_BPT_NUMBER (ISP3X_DPCC1_BASE + 0x00060)
+#define ISP3X_DPCC1_BPT_ADDR (ISP3X_DPCC1_BASE + 0x00064)
+#define ISP3X_DPCC1_BPT_DATA (ISP3X_DPCC1_BASE + 0x00068)
+#define ISP3X_DPCC1_BP_CNT (ISP3X_DPCC1_BASE + 0x0006c)
+#define ISP3X_DPCC1_PDAF_EN (ISP3X_DPCC1_BASE + 0x00070)
+#define ISP3X_DPCC1_PDAF_POINT_EN (ISP3X_DPCC1_BASE + 0x00074)
+#define ISP3X_DPCC1_PDAF_OFFSET (ISP3X_DPCC1_BASE + 0x00078)
+#define ISP3X_DPCC1_PDAF_WRAP (ISP3X_DPCC1_BASE + 0x0007c)
+#define ISP3X_DPCC1_PDAF_SCOPE (ISP3X_DPCC1_BASE + 0x00080)
+#define ISP3X_DPCC1_PDAF_POINT_0 (ISP3X_DPCC1_BASE + 0x00084)
+#define ISP3X_DPCC1_PDAF_POINT_1 (ISP3X_DPCC1_BASE + 0x00088)
+#define ISP3X_DPCC1_PDAF_POINT_2 (ISP3X_DPCC1_BASE + 0x0008c)
+#define ISP3X_DPCC1_PDAF_POINT_3 (ISP3X_DPCC1_BASE + 0x00090)
+#define ISP3X_DPCC1_PDAF_POINT_4 (ISP3X_DPCC1_BASE + 0x00094)
+#define ISP3X_DPCC1_PDAF_POINT_5 (ISP3X_DPCC1_BASE + 0x00098)
+#define ISP3X_DPCC1_PDAF_POINT_6 (ISP3X_DPCC1_BASE + 0x0009c)
+#define ISP3X_DPCC1_PDAF_POINT_7 (ISP3X_DPCC1_BASE + 0x000a0)
+#define ISP3X_DPCC1_PDAF_FORWARD_MED (ISP3X_DPCC1_BASE + 0x000a4)
+
+#define ISP3X_DPCC2_MODE (ISP3X_DPCC2_BASE + 0x00000)
+#define ISP3X_DPCC2_OUTPUT_MODE (ISP3X_DPCC2_BASE + 0x00004)
+#define ISP3X_DPCC2_SET_USE (ISP3X_DPCC2_BASE + 0x00008)
+#define ISP3X_DPCC2_METHODS_SET_1 (ISP3X_DPCC2_BASE + 0x0000c)
+#define ISP3X_DPCC2_METHODS_SET_2 (ISP3X_DPCC2_BASE + 0x00010)
+#define ISP3X_DPCC2_METHODS_SET_3 (ISP3X_DPCC2_BASE + 0x00014)
+#define ISP3X_DPCC2_LINE_THRESH_1 (ISP3X_DPCC2_BASE + 0x00018)
+#define ISP3X_DPCC2_LINE_MAD_FAC_1 (ISP3X_DPCC2_BASE + 0x0001c)
+#define ISP3X_DPCC2_PG_FAC_1 (ISP3X_DPCC2_BASE + 0x00020)
+#define ISP3X_DPCC2_RND_THRESH_1 (ISP3X_DPCC2_BASE + 0x00024)
+#define ISP3X_DPCC2_RG_FAC_1 (ISP3X_DPCC2_BASE + 0x00028)
+#define ISP3X_DPCC2_LINE_THRESH_2 (ISP3X_DPCC2_BASE + 0x0002c)
+#define ISP3X_DPCC2_LINE_MAD_FAC_2 (ISP3X_DPCC2_BASE + 0x00030)
+#define ISP3X_DPCC2_PG_FAC_2 (ISP3X_DPCC2_BASE + 0x00034)
+#define ISP3X_DPCC2_RND_THRESH_2 (ISP3X_DPCC2_BASE + 0x00038)
+#define ISP3X_DPCC2_RG_FAC_2 (ISP3X_DPCC2_BASE + 0x0003c)
+#define ISP3X_DPCC2_LINE_THRESH_3 (ISP3X_DPCC2_BASE + 0x00040)
+#define ISP3X_DPCC2_LINE_MAD_FAC_3 (ISP3X_DPCC2_BASE + 0x00044)
+#define ISP3X_DPCC2_PG_FAC_3 (ISP3X_DPCC2_BASE + 0x00048)
+#define ISP3X_DPCC2_RND_THRESH_3 (ISP3X_DPCC2_BASE + 0x0004c)
+#define ISP3X_DPCC2_RG_FAC_3 (ISP3X_DPCC2_BASE + 0x00050)
+#define ISP3X_DPCC2_RO_LIMITS (ISP3X_DPCC2_BASE + 0x00054)
+#define ISP3X_DPCC2_RND_OFFS (ISP3X_DPCC2_BASE + 0x00058)
+#define ISP3X_DPCC2_BPT_CTRL (ISP3X_DPCC2_BASE + 0x0005c)
+#define ISP3X_DPCC2_BPT_NUMBER (ISP3X_DPCC2_BASE + 0x00060)
+#define ISP3X_DPCC2_BPT_ADDR (ISP3X_DPCC2_BASE + 0x00064)
+#define ISP3X_DPCC2_BPT_DATA (ISP3X_DPCC2_BASE + 0x00068)
+#define ISP3X_DPCC2_BP_CNT (ISP3X_DPCC2_BASE + 0x0006c)
+#define ISP3X_DPCC2_PDAF_EN (ISP3X_DPCC2_BASE + 0x00070)
+#define ISP3X_DPCC2_PDAF_POINT_EN (ISP3X_DPCC2_BASE + 0x00074)
+#define ISP3X_DPCC2_PDAF_OFFSET (ISP3X_DPCC2_BASE + 0x00078)
+#define ISP3X_DPCC2_PDAF_WRAP (ISP3X_DPCC2_BASE + 0x0007c)
+#define ISP3X_DPCC2_PDAF_SCOPE (ISP3X_DPCC2_BASE + 0x00080)
+#define ISP3X_DPCC2_PDAF_POINT_0 (ISP3X_DPCC2_BASE + 0x00084)
+#define ISP3X_DPCC2_PDAF_POINT_1 (ISP3X_DPCC2_BASE + 0x00088)
+#define ISP3X_DPCC2_PDAF_POINT_2 (ISP3X_DPCC2_BASE + 0x0008c)
+#define ISP3X_DPCC2_PDAF_POINT_3 (ISP3X_DPCC2_BASE + 0x00090)
+#define ISP3X_DPCC2_PDAF_POINT_4 (ISP3X_DPCC2_BASE + 0x00094)
+#define ISP3X_DPCC2_PDAF_POINT_5 (ISP3X_DPCC2_BASE + 0x00098)
+#define ISP3X_DPCC2_PDAF_POINT_6 (ISP3X_DPCC2_BASE + 0x0009c)
+#define ISP3X_DPCC2_PDAF_POINT_7 (ISP3X_DPCC2_BASE + 0x000a0)
+#define ISP3X_DPCC2_PDAF_FORWARD_MED (ISP3X_DPCC2_BASE + 0x000a4)
+
+#define ISP3X_HDRMGE_BASE 0x00003800
+#define ISP3X_HDRMGE_CTRL (ISP3X_HDRMGE_BASE + 0x00000)
+#define ISP3X_HDRMGE_GAIN0 (ISP3X_HDRMGE_BASE + 0x00008)
+#define ISP3X_HDRMGE_GAIN1 (ISP3X_HDRMGE_BASE + 0x0000c)
+#define ISP3X_HDRMGE_GAIN2 (ISP3X_HDRMGE_BASE + 0x00010)
+#define ISP3X_HDRMGE_LIGHTZ (ISP3X_HDRMGE_BASE + 0x00014)
+#define ISP3X_HDRMGE_MS_DIFF (ISP3X_HDRMGE_BASE + 0x00018)
+#define ISP3X_HDRMGE_LM_DIFF (ISP3X_HDRMGE_BASE + 0x0001C)
+#define ISP3X_HDRMGE_DIFF_Y0 (ISP3X_HDRMGE_BASE + 0x00020)
+#define ISP3X_HDRMGE_DIFF_Y1 (ISP3X_HDRMGE_BASE + 0x00024)
+#define ISP3X_HDRMGE_DIFF_Y2 (ISP3X_HDRMGE_BASE + 0x00028)
+#define ISP3X_HDRMGE_DIFF_Y3 (ISP3X_HDRMGE_BASE + 0x0002c)
+#define ISP3X_HDRMGE_DIFF_Y4 (ISP3X_HDRMGE_BASE + 0x00030)
+#define ISP3X_HDRMGE_DIFF_Y5 (ISP3X_HDRMGE_BASE + 0x00034)
+#define ISP3X_HDRMGE_DIFF_Y6 (ISP3X_HDRMGE_BASE + 0x00038)
+#define ISP3X_HDRMGE_DIFF_Y7 (ISP3X_HDRMGE_BASE + 0x0003c)
+#define ISP3X_HDRMGE_DIFF_Y8 (ISP3X_HDRMGE_BASE + 0x00040)
+#define ISP3X_HDRMGE_DIFF_Y9 (ISP3X_HDRMGE_BASE + 0x00044)
+#define ISP3X_HDRMGE_DIFF_Y10 (ISP3X_HDRMGE_BASE + 0x00048)
+#define ISP3X_HDRMGE_DIFF_Y11 (ISP3X_HDRMGE_BASE + 0x0004c)
+#define ISP3X_HDRMGE_DIFF_Y12 (ISP3X_HDRMGE_BASE + 0x00050)
+#define ISP3X_HDRMGE_DIFF_Y13 (ISP3X_HDRMGE_BASE + 0x00054)
+#define ISP3X_HDRMGE_DIFF_Y14 (ISP3X_HDRMGE_BASE + 0x00058)
+#define ISP3X_HDRMGE_DIFF_Y15 (ISP3X_HDRMGE_BASE + 0x0005c)
+#define ISP3X_HDRMGE_DIFF_Y16 (ISP3X_HDRMGE_BASE + 0x00060)
+#define ISP3X_HDRMGE_OVER_Y0 (ISP3X_HDRMGE_BASE + 0x00070)
+#define ISP3X_HDRMGE_OVER_Y1 (ISP3X_HDRMGE_BASE + 0x00074)
+#define ISP3X_HDRMGE_OVER_Y2 (ISP3X_HDRMGE_BASE + 0x00078)
+#define ISP3X_HDRMGE_OVER_Y3 (ISP3X_HDRMGE_BASE + 0x0007c)
+#define ISP3X_HDRMGE_OVER_Y4 (ISP3X_HDRMGE_BASE + 0x00080)
+#define ISP3X_HDRMGE_OVER_Y5 (ISP3X_HDRMGE_BASE + 0x00084)
+#define ISP3X_HDRMGE_OVER_Y6 (ISP3X_HDRMGE_BASE + 0x00088)
+#define ISP3X_HDRMGE_OVER_Y7 (ISP3X_HDRMGE_BASE + 0x0008c)
+#define ISP3X_HDRMGE_OVER_Y8 (ISP3X_HDRMGE_BASE + 0x00090)
+#define ISP3X_HDRMGE_OVER_Y9 (ISP3X_HDRMGE_BASE + 0x00094)
+#define ISP3X_HDRMGE_OVER_Y10 (ISP3X_HDRMGE_BASE + 0x00098)
+#define ISP3X_HDRMGE_OVER_Y11 (ISP3X_HDRMGE_BASE + 0x0009c)
+#define ISP3X_HDRMGE_OVER_Y12 (ISP3X_HDRMGE_BASE + 0x000a0)
+#define ISP3X_HDRMGE_OVER_Y13 (ISP3X_HDRMGE_BASE + 0x000a4)
+#define ISP3X_HDRMGE_OVER_Y14 (ISP3X_HDRMGE_BASE + 0x000a8)
+#define ISP3X_HDRMGE_OVER_Y15 (ISP3X_HDRMGE_BASE + 0x000ac)
+#define ISP3X_HDRMGE_OVER_Y16 (ISP3X_HDRMGE_BASE + 0x000b0)
+#define ISP32_HDRMGE_EACH_GAIN (ISP3X_HDRMGE_BASE + 0x000b4)
+#define ISP35_HDRMGE_FORCE_LONG0 (ISP3X_HDRMGE_BASE + 0x000b8)
+#define ISP35_HDRMGE_FORCE_LONG1 (ISP3X_HDRMGE_BASE + 0x000bc)
+
+#define ISP3X_DRC_BASE 0x00003900
+#define ISP3X_DRC_CTRL0 (ISP3X_DRC_BASE + 0x00000)
+#define ISP3X_DRC_CTRL1 (ISP3X_DRC_BASE + 0x00004)
+#define ISP3X_DRC_LPRATIO (ISP3X_DRC_BASE + 0x00008)
+#define ISP3X_DRC_EXPLRATIO (ISP3X_DRC_BASE + 0x0000c)
+#define ISP3X_DRC_SIGMA (ISP3X_DRC_BASE + 0x00010)
+#define ISP3X_DRC_SPACESGM (ISP3X_DRC_BASE + 0x00014)
+#define ISP3X_DRC_RANESGM (ISP3X_DRC_BASE + 0x00018)
+#define ISP3X_DRC_BILAT (ISP3X_DRC_BASE + 0x0001c)
+#define ISP3X_DRC_GAIN_Y0 (ISP3X_DRC_BASE + 0x00020)
+#define ISP3X_DRC_GAIN_Y1 (ISP3X_DRC_BASE + 0x00024)
+#define ISP3X_DRC_GAIN_Y2 (ISP3X_DRC_BASE + 0x00028)
+#define ISP3X_DRC_GAIN_Y3 (ISP3X_DRC_BASE + 0x0002c)
+#define ISP3X_DRC_GAIN_Y4 (ISP3X_DRC_BASE + 0x00030)
+#define ISP3X_DRC_GAIN_Y5 (ISP3X_DRC_BASE + 0x00034)
+#define ISP3X_DRC_GAIN_Y6 (ISP3X_DRC_BASE + 0x00038)
+#define ISP3X_DRC_GAIN_Y7 (ISP3X_DRC_BASE + 0x0003c)
+#define ISP3X_DRC_GAIN_Y8 (ISP3X_DRC_BASE + 0x00040)
+#define ISP3X_DRC_COMPRES_Y0 (ISP3X_DRC_BASE + 0x00044)
+#define ISP3X_DRC_COMPRES_Y1 (ISP3X_DRC_BASE + 0x00048)
+#define ISP3X_DRC_COMPRES_Y2 (ISP3X_DRC_BASE + 0x0004c)
+#define ISP3X_DRC_COMPRES_Y3 (ISP3X_DRC_BASE + 0x00050)
+#define ISP3X_DRC_COMPRES_Y4 (ISP3X_DRC_BASE + 0x00054)
+#define ISP3X_DRC_COMPRES_Y5 (ISP3X_DRC_BASE + 0x00058)
+#define ISP3X_DRC_COMPRES_Y6 (ISP3X_DRC_BASE + 0x0005c)
+#define ISP3X_DRC_COMPRES_Y7 (ISP3X_DRC_BASE + 0x00060)
+#define ISP3X_DRC_COMPRES_Y8 (ISP3X_DRC_BASE + 0x00064)
+#define ISP3X_DRC_SCALE_Y0 (ISP3X_DRC_BASE + 0x00068)
+#define ISP3X_DRC_SCALE_Y1 (ISP3X_DRC_BASE + 0x0006c)
+#define ISP3X_DRC_SCALE_Y2 (ISP3X_DRC_BASE + 0x00070)
+#define ISP3X_DRC_SCALE_Y3 (ISP3X_DRC_BASE + 0x00074)
+#define ISP3X_DRC_SCALE_Y4 (ISP3X_DRC_BASE + 0x00078)
+#define ISP3X_DRC_SCALE_Y5 (ISP3X_DRC_BASE + 0x0007c)
+#define ISP3X_DRC_SCALE_Y6 (ISP3X_DRC_BASE + 0x00080)
+#define ISP3X_DRC_SCALE_Y7 (ISP3X_DRC_BASE + 0x00084)
+#define ISP3X_DRC_SCALE_Y8 (ISP3X_DRC_BASE + 0x00088)
+#define ISP3X_DRC_IIRWG_GAIN (ISP3X_DRC_BASE + 0x0008c)
+#define ISP32_DRC_LUM3X2_CTRL (ISP3X_DRC_BASE + 0x00090)
+#define ISP32_DRC_LUM3X2_GAS (ISP3X_DRC_BASE + 0x00094)
+#define ISP39_DRC_BILAT0 (ISP3X_DRC_BASE + 0x0000c)
+#define ISP39_DRC_BILAT1 (ISP3X_DRC_BASE + 0x00010)
+#define ISP39_DRC_BILAT2 (ISP3X_DRC_BASE + 0x00014)
+#define ISP39_DRC_BILAT3 (ISP3X_DRC_BASE + 0x00018)
+#define ISP39_DRC_BILAT4 (ISP3X_DRC_BASE + 0x0001c)
+#define ISP39_DRC_SFTHD_Y0 (ISP3X_DRC_BASE + 0x00090)
+#define ISP39_DRC_SFTHD_Y1 (ISP3X_DRC_BASE + 0x00094)
+#define ISP39_DRC_SFTHD_Y2 (ISP3X_DRC_BASE + 0x00098)
+#define ISP39_DRC_SFTHD_Y3 (ISP3X_DRC_BASE + 0x0009c)
+#define ISP39_DRC_SFTHD_Y4 (ISP3X_DRC_BASE + 0x000a0)
+#define ISP39_DRC_SFTHD_Y5 (ISP3X_DRC_BASE + 0x000a4)
+#define ISP39_DRC_SFTHD_Y6 (ISP3X_DRC_BASE + 0x000a8)
+#define ISP39_DRC_SFTHD_Y7 (ISP3X_DRC_BASE + 0x000ac)
+#define ISP39_DRC_SFTHD_Y8 (ISP3X_DRC_BASE + 0x000b0)
+#define ISP35_DRC_LUMA_MIX (ISP3X_DRC_BASE + 0x000b4)
+
+#define ISP3X_BAYNR_BASE 0x00003A00
+#define ISP3X_BAYNR_CTRL (ISP3X_BAYNR_BASE + 0x00000)
+#define ISP3X_BAYNR_DGAIN0 (ISP3X_BAYNR_BASE + 0x00004)
+#define ISP3X_BAYNR_DGAIN1 (ISP3X_BAYNR_BASE + 0x00008)
+#define ISP3X_BAYNR_PIXDIFF (ISP3X_BAYNR_BASE + 0x0000c)
+#define ISP3X_BAYNR_THLD (ISP3X_BAYNR_BASE + 0x00010)
+#define ISP3X_BAYNR_W1_STRENG (ISP3X_BAYNR_BASE + 0x00014)
+#define ISP3X_BAYNR_SIGMAX01 (ISP3X_BAYNR_BASE + 0x00018)
+#define ISP3X_BAYNR_SIGMAX23 (ISP3X_BAYNR_BASE + 0x0001c)
+#define ISP3X_BAYNR_SIGMAX45 (ISP3X_BAYNR_BASE + 0x00020)
+#define ISP3X_BAYNR_SIGMAX67 (ISP3X_BAYNR_BASE + 0x00024)
+#define ISP3X_BAYNR_SIGMAX89 (ISP3X_BAYNR_BASE + 0x00028)
+#define ISP3X_BAYNR_SIGMAX1011 (ISP3X_BAYNR_BASE + 0x0002c)
+#define ISP3X_BAYNR_SIGMAX1213 (ISP3X_BAYNR_BASE + 0x00030)
+#define ISP3X_BAYNR_SIGMAX1415 (ISP3X_BAYNR_BASE + 0x00034)
+#define ISP3X_BAYNR_SIGMAY01 (ISP3X_BAYNR_BASE + 0x00038)
+#define ISP3X_BAYNR_SIGMAY23 (ISP3X_BAYNR_BASE + 0x0003c)
+#define ISP3X_BAYNR_SIGMAY45 (ISP3X_BAYNR_BASE + 0x00040)
+#define ISP3X_BAYNR_SIGMAY67 (ISP3X_BAYNR_BASE + 0x00044)
+#define ISP3X_BAYNR_SIGMAY89 (ISP3X_BAYNR_BASE + 0x00048)
+#define ISP3X_BAYNR_SIGMAY1011 (ISP3X_BAYNR_BASE + 0x0004c)
+#define ISP3X_BAYNR_SIGMAY1213 (ISP3X_BAYNR_BASE + 0x00050)
+#define ISP3X_BAYNR_SIGMAY1415 (ISP3X_BAYNR_BASE + 0x00054)
+#define ISP3X_BAYNR_WRIT_D (ISP3X_BAYNR_BASE + 0x00058)
+#define ISP3X_BAYNR_LG_OFF (ISP3X_BAYNR_BASE + 0x0005c)
+#define ISP3X_BAYNR_DAT_MAX (ISP3X_BAYNR_BASE + 0x00060)
+#define ISP32_BAYNR_SIGOFF (ISP3X_BAYNR_BASE + 0x00064)
+#define ISP32_BAYNR_GAINX03 (ISP3X_BAYNR_BASE + 0x00068)
+#define ISP32_BAYNR_GAINX47 (ISP3X_BAYNR_BASE + 0x0006c)
+#define ISP32_BAYNR_GAINX811 (ISP3X_BAYNR_BASE + 0x00070)
+#define ISP32_BAYNR_GAINX1215 (ISP3X_BAYNR_BASE + 0x00074)
+#define ISP32_BAYNR_GAINY01 (ISP3X_BAYNR_BASE + 0x00078)
+#define ISP32_BAYNR_GAINX23 (ISP3X_BAYNR_BASE + 0x0007c)
+#define ISP32_BAYNR_GAINX45 (ISP3X_BAYNR_BASE + 0x00080)
+#define ISP32_BAYNR_GAINX67 (ISP3X_BAYNR_BASE + 0x00084)
+#define ISP32_BAYNR_GAINX89 (ISP3X_BAYNR_BASE + 0x00088)
+#define ISP32_BAYNR_GAINX1011 (ISP3X_BAYNR_BASE + 0x0008c)
+#define ISP32_BAYNR_GAINX1213 (ISP3X_BAYNR_BASE + 0x00090)
+#define ISP32_BAYNR_GAINX1415 (ISP3X_BAYNR_BASE + 0x00094)
+
+#define ISP33_ENH_BASE 0x00003A00
+#define ISP33_ENH_CTRL (ISP33_ENH_BASE + 0x00000)
+#define ISP33_ENH_IIR_FLT (ISP33_ENH_BASE + 0x00004)
+#define ISP33_ENH_BILAT_FLT3X3 (ISP33_ENH_BASE + 0x00008)
+#define ISP33_ENH_BILAT_FLT5X5 (ISP33_ENH_BASE + 0x0000c)
+#define ISP33_ENH_GLOBAL_STRG (ISP33_ENH_BASE + 0x00010)
+#define ISP33_ENH_LUMA_LUT0 (ISP33_ENH_BASE + 0x00014)
+#define ISP33_ENH_LUMA_LUT8 (ISP33_ENH_BASE + 0x00034)
+#define ISP33_ENH_DETAIL_IDX0 (ISP33_ENH_BASE + 0x00038)
+#define ISP33_ENH_DETAIL_IDX2 (ISP33_ENH_BASE + 0x00040)
+#define ISP33_ENH_DETAIL_POWER (ISP33_ENH_BASE + 0x00044)
+#define ISP33_ENH_DETAIL_VALUE0 (ISP33_ENH_BASE + 0x00048)
+#define ISP33_ENH_PRE_FRAME (ISP33_ENH_BASE + 0x0007c)
+#define ISP33_ENH_IIR0 (ISP33_ENH_BASE + 0x00080)
+#define ISP33_ENH_IIR9 (ISP33_ENH_BASE + 0x000a4)
+#define ISP33_ENH_IIR_RW (ISP33_ENH_BASE + 0x000a8)
+#define ISP33_ENH_ERR_FLAG (ISP33_ENH_BASE + 0x000fc)
+
+#define ISP3X_LDCH_BASE 0x00003B00
+#define ISP3X_LDCH_STS (ISP3X_LDCH_BASE + 0x00000)
+#define ISP32_LDCH_BIC_TABLE0 (ISP3X_LDCH_BASE + 0x00004)
+#define ISP32_LDCH_BIC_TABLE1 (ISP3X_LDCH_BASE + 0x00008)
+#define ISP32_LDCH_BIC_TABLE2 (ISP3X_LDCH_BASE + 0x0000c)
+#define ISP32_LDCH_BIC_TABLE3 (ISP3X_LDCH_BASE + 0x00010)
+#define ISP32_LDCH_BIC_TABLE4 (ISP3X_LDCH_BASE + 0x00014)
+#define ISP32_LDCH_BIC_TABLE5 (ISP3X_LDCH_BASE + 0x00018)
+#define ISP32_LDCH_BIC_TABLE6 (ISP3X_LDCH_BASE + 0x0001c)
+#define ISP32_LDCH_BIC_TABLE7 (ISP3X_LDCH_BASE + 0x00020)
+#define ISP32_LDCH_BIC_TABLE8 (ISP3X_LDCH_BASE + 0x00024)
+#define ISP39_LDCH_OUT_SIZE (ISP3X_LDCH_BASE + 0x00028)
+#define ISP35_B3DLDC_CTRL (ISP3X_LDCH_BASE + 0x00080)
+#define ISP35_B3DLDC_WR_ADDR (ISP3X_LDCH_BASE + 0x000a8)
+#define ISP35_B3DLDC_WR_STRIDE (ISP3X_LDCH_BASE + 0x000ac)
+#define ISP35_B3DLDC_FFFF_OFF (ISP3X_LDCH_BASE + 0x000b0)
+#define ISP35_B3DLDC_ADR_STS (ISP3X_LDCH_BASE + 0x000e0)
+#define ISP35_B3DLDC_EXTBOUND1 (ISP3X_LDCH_BASE + 0x000e8)
+
+#define ISP3X_DHAZ_BASE 0x00003C00
+#define ISP3X_DHAZ_CTRL (ISP3X_DHAZ_BASE + 0x00000)
+#define ISP3X_DHAZ_ADP0 (ISP3X_DHAZ_BASE + 0x00004)
+#define ISP3X_DHAZ_ADP1 (ISP3X_DHAZ_BASE + 0x00008)
+#define ISP3X_DHAZ_ADP2 (ISP3X_DHAZ_BASE + 0x0000c)
+#define ISP3X_DHAZ_ADP_TMAX (ISP3X_DHAZ_BASE + 0x00010)
+#define ISP3X_DHAZ_ADP_HIST0 (ISP3X_DHAZ_BASE + 0x00014)
+#define ISP3X_DHAZ_ADP_HIST1 (ISP3X_DHAZ_BASE + 0x00018)
+#define ISP3X_DHAZ_ENHANCE (ISP3X_DHAZ_BASE + 0x0001c)
+#define ISP3X_DHAZ_IIR0 (ISP3X_DHAZ_BASE + 0x00020)
+#define ISP3X_DHAZ_IIR1 (ISP3X_DHAZ_BASE + 0x00024)
+#define ISP3X_DHAZ_SOFT_CFG0 (ISP3X_DHAZ_BASE + 0x00028)
+#define ISP3X_DHAZ_SOFT_CFG1 (ISP3X_DHAZ_BASE + 0x0002c)
+#define ISP3X_DHAZ_BF_SIGMA (ISP3X_DHAZ_BASE + 0x00030)
+#define ISP3X_DHAZ_BF_WET (ISP3X_DHAZ_BASE + 0x00034)
+#define ISP3X_DHAZ_ENH_CURVE0 (ISP3X_DHAZ_BASE + 0x00038)
+#define ISP3X_DHAZ_ENH_CURVE1 (ISP3X_DHAZ_BASE + 0x0003c)
+#define ISP3X_DHAZ_ENH_CURVE2 (ISP3X_DHAZ_BASE + 0x00040)
+#define ISP3X_DHAZ_ENH_CURVE3 (ISP3X_DHAZ_BASE + 0x00044)
+#define ISP3X_DHAZ_ENH_CURVE4 (ISP3X_DHAZ_BASE + 0x00048)
+#define ISP3X_DHAZ_ENH_CURVE5 (ISP3X_DHAZ_BASE + 0x0004c)
+#define ISP3X_DHAZ_ENH_CURVE6 (ISP3X_DHAZ_BASE + 0x00050)
+#define ISP3X_DHAZ_ENH_CURVE7 (ISP3X_DHAZ_BASE + 0x00054)
+#define ISP3X_DHAZ_ENH_CURVE8 (ISP3X_DHAZ_BASE + 0x00058)
+#define ISP3X_DHAZ_GAUS (ISP3X_DHAZ_BASE + 0x0005c)
+#define ISP3X_DHAZ_GAIN_IDX0 (ISP3X_DHAZ_BASE + 0x00060)
+#define ISP3X_DHAZ_GAIN_IDX1 (ISP3X_DHAZ_BASE + 0x00064)
+#define ISP3X_DHAZ_GAIN_IDX2 (ISP3X_DHAZ_BASE + 0x00068)
+#define ISP3X_DHAZ_GAIN_IDX3 (ISP3X_DHAZ_BASE + 0x0006C)
+#define ISP3X_DHAZ_GAIN_LUT0 (ISP3X_DHAZ_BASE + 0x00070)
+#define ISP3X_DHAZ_GAIN_LUT1 (ISP3X_DHAZ_BASE + 0x00074)
+#define ISP3X_DHAZ_GAIN_LUT2 (ISP3X_DHAZ_BASE + 0x00078)
+#define ISP3X_DHAZ_GAIN_LUT3 (ISP3X_DHAZ_BASE + 0x0007C)
+#define ISP3X_DHAZ_GAIN_LUT4 (ISP3X_DHAZ_BASE + 0x00080)
+#define ISP3X_DHAZ_GAIN_LUT5 (ISP3X_DHAZ_BASE + 0x00084)
+#define ISP3X_DHAZ_GAIN_LUT6 (ISP3X_DHAZ_BASE + 0x00088)
+#define ISP3X_DHAZ_GAIN_LUT7 (ISP3X_DHAZ_BASE + 0x0008C)
+#define ISP3X_DHAZ_GAIN_LUT8 (ISP3X_DHAZ_BASE + 0x00090)
+#define ISP3X_DHAZ_SUMH_RD (ISP3X_DHAZ_BASE + 0x0009C)
+#define ISP3X_DHAZ_ADT_WR0 (ISP3X_DHAZ_BASE + 0x000A0)
+#define ISP3X_DHAZ_ADT_WR1 (ISP3X_DHAZ_BASE + 0x000A4)
+#define ISP3X_DHAZ_HIST_WR0 (ISP3X_DHAZ_BASE + 0x000A8)
+#define ISP3X_DHAZ_HIST_WR1 (ISP3X_DHAZ_BASE + 0x000AC)
+#define ISP3X_DHAZ_HIST_WR2 (ISP3X_DHAZ_BASE + 0x000B0)
+#define ISP3X_DHAZ_HIST_WR3 (ISP3X_DHAZ_BASE + 0x000B4)
+#define ISP3X_DHAZ_HIST_WR4 (ISP3X_DHAZ_BASE + 0x000B8)
+#define ISP3X_DHAZ_HIST_WR5 (ISP3X_DHAZ_BASE + 0x000BC)
+#define ISP3X_DHAZ_HIST_WR6 (ISP3X_DHAZ_BASE + 0x000C0)
+#define ISP3X_DHAZ_HIST_WR7 (ISP3X_DHAZ_BASE + 0x000C4)
+#define ISP3X_DHAZ_HIST_WR8 (ISP3X_DHAZ_BASE + 0x000C8)
+#define ISP3X_DHAZ_HIST_WR9 (ISP3X_DHAZ_BASE + 0x000CC)
+#define ISP3X_DHAZ_HIST_WR10 (ISP3X_DHAZ_BASE + 0x000D0)
+#define ISP3X_DHAZ_HIST_WR11 (ISP3X_DHAZ_BASE + 0x000D4)
+#define ISP3X_DHAZ_HIST_WR12 (ISP3X_DHAZ_BASE + 0x000D8)
+#define ISP3X_DHAZ_HIST_WR13 (ISP3X_DHAZ_BASE + 0x000DC)
+#define ISP3X_DHAZ_HIST_WR14 (ISP3X_DHAZ_BASE + 0x000E0)
+#define ISP3X_DHAZ_HIST_WR15 (ISP3X_DHAZ_BASE + 0x000E4)
+#define ISP3X_DHAZ_HIST_WR16 (ISP3X_DHAZ_BASE + 0x000E8)
+#define ISP3X_DHAZ_HIST_WR17 (ISP3X_DHAZ_BASE + 0x000EC)
+#define ISP3X_DHAZ_HIST_WR18 (ISP3X_DHAZ_BASE + 0x000F0)
+#define ISP3X_DHAZ_HIST_WR19 (ISP3X_DHAZ_BASE + 0x000F4)
+#define ISP3X_DHAZ_HIST_WR20 (ISP3X_DHAZ_BASE + 0x000F8)
+#define ISP3X_DHAZ_HIST_WR21 (ISP3X_DHAZ_BASE + 0x000FC)
+#define ISP3X_DHAZ_CTRL_SHD (ISP3X_DHAZ_BASE + 0x00100)
+#define ISP3X_DHAZ_ADP_RD0 (ISP3X_DHAZ_BASE + 0x00104)
+#define ISP3X_DHAZ_ADP_RD1 (ISP3X_DHAZ_BASE + 0x00108)
+#define ISP3X_DHAZ_HIST_REG0 (ISP3X_DHAZ_BASE + 0x00110)
+#define ISP3X_DHAZ_HIST_REG1 (ISP3X_DHAZ_BASE + 0x00114)
+#define ISP3X_DHAZ_HIST_REG2 (ISP3X_DHAZ_BASE + 0x00118)
+#define ISP3X_DHAZ_HIST_REG3 (ISP3X_DHAZ_BASE + 0x0011C)
+#define ISP3X_DHAZ_HIST_REG4 (ISP3X_DHAZ_BASE + 0x00120)
+#define ISP3X_DHAZ_HIST_REG5 (ISP3X_DHAZ_BASE + 0x00124)
+#define ISP3X_DHAZ_HIST_REG6 (ISP3X_DHAZ_BASE + 0x00128)
+#define ISP3X_DHAZ_HIST_REG7 (ISP3X_DHAZ_BASE + 0x0012C)
+#define ISP3X_DHAZ_HIST_REG8 (ISP3X_DHAZ_BASE + 0x00130)
+#define ISP3X_DHAZ_HIST_REG9 (ISP3X_DHAZ_BASE + 0x00134)
+#define ISP3X_DHAZ_HIST_REG10 (ISP3X_DHAZ_BASE + 0x00138)
+#define ISP3X_DHAZ_HIST_REG11 (ISP3X_DHAZ_BASE + 0x0013C)
+#define ISP3X_DHAZ_HIST_REG12 (ISP3X_DHAZ_BASE + 0x00140)
+#define ISP3X_DHAZ_HIST_REG13 (ISP3X_DHAZ_BASE + 0x00144)
+#define ISP3X_DHAZ_HIST_REG14 (ISP3X_DHAZ_BASE + 0x00148)
+#define ISP3X_DHAZ_HIST_REG15 (ISP3X_DHAZ_BASE + 0x0014C)
+#define ISP3X_DHAZ_HIST_REG16 (ISP3X_DHAZ_BASE + 0x00150)
+#define ISP3X_DHAZ_HIST_REG17 (ISP3X_DHAZ_BASE + 0x00154)
+#define ISP3X_DHAZ_HIST_REG18 (ISP3X_DHAZ_BASE + 0x00158)
+#define ISP3X_DHAZ_HIST_REG19 (ISP3X_DHAZ_BASE + 0x0015C)
+#define ISP3X_DHAZ_HIST_REG20 (ISP3X_DHAZ_BASE + 0x00160)
+#define ISP3X_DHAZ_HIST_REG21 (ISP3X_DHAZ_BASE + 0x00164)
+#define ISP3X_DHAZ_HIST_REG22 (ISP3X_DHAZ_BASE + 0x00168)
+#define ISP3X_DHAZ_HIST_REG23 (ISP3X_DHAZ_BASE + 0x0016C)
+#define ISP3X_DHAZ_HIST_REG24 (ISP3X_DHAZ_BASE + 0x00170)
+#define ISP3X_DHAZ_HIST_REG25 (ISP3X_DHAZ_BASE + 0x00174)
+#define ISP3X_DHAZ_HIST_REG26 (ISP3X_DHAZ_BASE + 0x00178)
+#define ISP3X_DHAZ_HIST_REG27 (ISP3X_DHAZ_BASE + 0x0017C)
+#define ISP3X_DHAZ_HIST_REG28 (ISP3X_DHAZ_BASE + 0x00180)
+#define ISP3X_DHAZ_HIST_REG29 (ISP3X_DHAZ_BASE + 0x00184)
+#define ISP3X_DHAZ_HIST_REG30 (ISP3X_DHAZ_BASE + 0x00188)
+#define ISP3X_DHAZ_HIST_REG31 (ISP3X_DHAZ_BASE + 0x0018C)
+#define ISP32_DHAZ_ENH_LUMA0 (ISP3X_DHAZ_BASE + 0x00190)
+#define ISP32_DHAZ_ENH_LUMA1 (ISP3X_DHAZ_BASE + 0x00194)
+#define ISP32_DHAZ_ENH_LUMA2 (ISP3X_DHAZ_BASE + 0x00198)
+#define ISP32_DHAZ_ENH_LUMA3 (ISP3X_DHAZ_BASE + 0x0019c)
+#define ISP32_DHAZ_ENH_LUMA4 (ISP3X_DHAZ_BASE + 0x001a0)
+#define ISP32_DHAZ_ENH_LUMA5 (ISP3X_DHAZ_BASE + 0x001a4)
+#define ISP32L_DHAZ_STAB_FRAME (ISP3X_DHAZ_BASE + 0x001f8)
+#define ISP32L_DHAZ_PRE_FRAME (ISP3X_DHAZ_BASE + 0x001fc)
+#define ISP39_DHAZ_ENHANCE (ISP3X_DHAZ_BASE + 0x00014)
+#define ISP39_DHAZ_IIR0 (ISP3X_DHAZ_BASE + 0x00018)
+#define ISP39_DHAZ_IIR1 (ISP3X_DHAZ_BASE + 0x0001c)
+#define ISP39_DHAZ_SOFT_CFG0 (ISP3X_DHAZ_BASE + 0x00020)
+#define ISP39_DHAZ_SOFT_CFG1 (ISP3X_DHAZ_BASE + 0x00024)
+#define ISP39_DHAZ_BF_SIGMA (ISP3X_DHAZ_BASE + 0x00028)
+#define ISP39_DHAZ_BF_WET (ISP3X_DHAZ_BASE + 0x0002c)
+#define ISP39_DHAZ_ENH_CURVE0 (ISP3X_DHAZ_BASE + 0x00030)
+#define ISP39_DHAZ_ENH_CURVE1 (ISP3X_DHAZ_BASE + 0x00034)
+#define ISP39_DHAZ_ENH_CURVE2 (ISP3X_DHAZ_BASE + 0x00038)
+#define ISP39_DHAZ_ENH_CURVE3 (ISP3X_DHAZ_BASE + 0x0003c)
+#define ISP39_DHAZ_ENH_CURVE4 (ISP3X_DHAZ_BASE + 0x00040)
+#define ISP39_DHAZ_ENH_CURVE5 (ISP3X_DHAZ_BASE + 0x00044)
+#define ISP39_DHAZ_GAUS (ISP3X_DHAZ_BASE + 0x00048)
+#define ISP39_DHAZ_ENH_LUMA0 (ISP3X_DHAZ_BASE + 0x0004c)
+#define ISP39_DHAZ_ENH_LUMA1 (ISP3X_DHAZ_BASE + 0x00050)
+#define ISP39_DHAZ_ENH_LUMA2 (ISP3X_DHAZ_BASE + 0x00054)
+#define ISP39_DHAZ_ENH_LUMA3 (ISP3X_DHAZ_BASE + 0x00058)
+#define ISP39_DHAZ_ENH_LUMA4 (ISP3X_DHAZ_BASE + 0x0005c)
+#define ISP39_DHAZ_ENH_LUMA5 (ISP3X_DHAZ_BASE + 0x00060)
+#define ISP39_DHAZ_ADP_WR0 (ISP3X_DHAZ_BASE + 0x00064)
+#define ISP39_DHAZ_ADP_WR1 (ISP3X_DHAZ_BASE + 0x00068)
+#define ISP39_DHAZ_DDR_SIZE (ISP3X_DHAZ_BASE + 0x0006c)
+#define ISP39_DHAZ_GAIN_IDX0 (ISP3X_DHAZ_BASE + 0x00080)
+#define ISP39_DHAZ_GAIN_IDX1 (ISP3X_DHAZ_BASE + 0x00084)
+#define ISP39_DHAZ_GAIN_IDX2 (ISP3X_DHAZ_BASE + 0x00088)
+#define ISP39_DHAZ_GAIN_IDX3 (ISP3X_DHAZ_BASE + 0x0008c)
+#define ISP39_DHAZ_GAIN_LUT0 (ISP3X_DHAZ_BASE + 0x00090)
+#define ISP39_DHAZ_GAIN_LUT1 (ISP3X_DHAZ_BASE + 0x00094)
+#define ISP39_DHAZ_GAIN_LUT2 (ISP3X_DHAZ_BASE + 0x00098)
+#define ISP39_DHAZ_GAIN_LUT3 (ISP3X_DHAZ_BASE + 0x0009c)
+#define ISP39_DHAZ_GAIN_LUT4 (ISP3X_DHAZ_BASE + 0x000a0)
+#define ISP39_DHAZ_GAIN_LUT5 (ISP3X_DHAZ_BASE + 0x000a4)
+#define ISP39_DHAZ_GAIN_FUSE (ISP3X_DHAZ_BASE + 0x000a8)
+#define ISP39_DHAZ_ADP_HF (ISP3X_DHAZ_BASE + 0x00100)
+#define ISP39_DHAZ_BLOCK_SIZE (ISP3X_DHAZ_BASE + 0x00104)
+#define ISP39_DHAZ_THUMB_SIZE (ISP3X_DHAZ_BASE + 0x00108)
+#define ISP39_DHAZ_HIST_CFG (ISP3X_DHAZ_BASE + 0x0010c)
+#define ISP39_DHAZ_HIST_GAIN (ISP3X_DHAZ_BASE + 0x00110)
+#define ISP39_DHAZ_BLEND_WET0 (ISP3X_DHAZ_BASE + 0x00114)
+#define ISP39_DHAZ_BLEND_WET1 (ISP3X_DHAZ_BASE + 0x00118)
+#define ISP39_DHAZ_BLEND_WET2 (ISP3X_DHAZ_BASE + 0x0011c)
+#define ISP39_DHAZ_BLEND_WET3 (ISP3X_DHAZ_BASE + 0x00120)
+#define ISP39_DHAZ_BLEND_WET4 (ISP3X_DHAZ_BASE + 0x00124)
+#define ISP39_DHAZ_BLEND_WET5 (ISP3X_DHAZ_BASE + 0x00128)
+#define ISP39_DHAZ_HIST_IIR0 (ISP3X_DHAZ_BASE + 0x0012c)
+#define ISP39_DHAZ_HIST_IIR1 (ISP3X_DHAZ_BASE + 0x00130)
+#define ISP39_DHAZ_HIST_IIR2 (ISP3X_DHAZ_BASE + 0x00134)
+#define ISP39_DHAZ_HIST_IIR3 (ISP3X_DHAZ_BASE + 0x00138)
+#define ISP39_DHAZ_HIST_IIR4 (ISP3X_DHAZ_BASE + 0x0013c)
+#define ISP39_DHAZ_HIST_IIR5 (ISP3X_DHAZ_BASE + 0x00140)
+#define ISP39_DHAZ_HIST_IIR6 (ISP3X_DHAZ_BASE + 0x00144)
+#define ISP39_DHAZ_HIST_IIR7 (ISP3X_DHAZ_BASE + 0x00148)
+#define ISP39_DHAZ_HIST_RW (ISP3X_DHAZ_BASE + 0x0014c)
+#define ISP39_DHAZ_CTRL_SHD (ISP3X_DHAZ_BASE + 0x00180)
+#define ISP39_DHAZ_ADP_RD0 (ISP3X_DHAZ_BASE + 0x00184)
+#define ISP39_DHAZ_ADP_RD1 (ISP3X_DHAZ_BASE + 0x00188)
+#define ISP39_DHAZ_LINE_CNT (ISP3X_DHAZ_BASE + 0x0018c)
+
+#define ISP33_HIST_BASE 0x00003C00
+#define ISP33_HIST_CTRL (ISP33_HIST_BASE + 0x00000)
+#define ISP33_HIST_HF_STAT (ISP33_HIST_BASE + 0x00004)
+#define ISP33_HIST_BLOCK_SIZE (ISP33_HIST_BASE + 0x00008)
+#define ISP33_HIST_THUMB_SIZE (ISP33_HIST_BASE + 0x0000c)
+#define ISP33_HIST_MAP0 (ISP33_HIST_BASE + 0x00010)
+#define ISP33_HIST_MAP1 (ISP33_HIST_BASE + 0x00014)
+#define ISP33_HIST_IIR (ISP33_HIST_BASE + 0x00018)
+#define ISP33_HIST_POS_ALPHA0 (ISP33_HIST_BASE + 0x0001c)
+#define ISP33_HIST_POS_ALPHA4 (ISP33_HIST_BASE + 0x0002c)
+#define ISP33_HIST_NEG_ALPHA0 (ISP33_HIST_BASE + 0x00030)
+#define ISP33_HIST_NEG_ALPHA4 (ISP33_HIST_BASE + 0x00040)
+#define ISP33_HIST_IIR0 (ISP33_HIST_BASE + 0x00080)
+#define ISP33_HIST_RW (ISP33_HIST_BASE + 0x000a0)
+#define ISP33_HIST_STAB (ISP33_HIST_BASE + 0x000a4)
+#define ISP33_HIST_UV_SCL (ISP33_HIST_BASE + 0x000a8)
+#define ISP33_HIST_ERR_FLAG (ISP33_HIST_BASE + 0x000fc)
+
+#define ISP3X_3DLUT_BASE 0x00003E00
+#define ISP3X_3DLUT_CTRL (ISP3X_3DLUT_BASE + 0x00000)
+#define ISP3X_3DLUT_UPDATE (ISP3X_3DLUT_BASE + 0x00004)
+
+#define ISP33_HSV_BASE 0x00003E00
+#define ISP33_HSV_CTRL (ISP33_HSV_BASE + 0x00000)
+#define ISP33_HSV_UPDATE (ISP33_HSV_BASE + 0x00004)
+#define ISP33_HSV_1DLUT (ISP33_HSV_BASE + 0x00008)
+#define ISP33_HSV_2DLUT (ISP33_HSV_BASE + 0x0000c)
+#define ISP35_HSV_MODE_CTRL (ISP33_HSV_BASE + 0x00004)
+#define ISP35_HSV_1DLUT (ISP33_HSV_BASE + 0x0000c)
+#define ISP35_HSV_2DLUT0 (ISP33_HSV_BASE + 0x00010)
+#define ISP35_HSV_2DLUT1 (ISP33_HSV_BASE + 0x00014)
+#define ISP35_HSV_2DLUT2 (ISP33_HSV_BASE + 0x00018)
+
+#define ISP35_AWBSYNC_BASE 0x00003E80
+#define ISP35_AWBSYNC_CTRL (ISP35_AWBSYNC_BASE + 0x00000)
+#define ISP35_AWBSYNC_SCL (ISP35_AWBSYNC_BASE + 0x00004)
+#define ISP35_AWBSYNC_SUMVAL_MIN (ISP35_AWBSYNC_BASE + 0x00008)
+#define ISP35_AWBSYNC_SUMVAL_MAX (ISP35_AWBSYNC_BASE + 0x0000C)
+#define ISP35_AWBSYNC_WIN0_OFFS (ISP35_AWBSYNC_BASE + 0x00010)
+#define ISP35_AWBSYNC_WIN0_RD_COOR (ISP35_AWBSYNC_BASE + 0x00014)
+#define ISP35_AWBSYNC_WIN1_OFFS (ISP35_AWBSYNC_BASE + 0x00018)
+#define ISP35_AWBSYNC_WIN1_RD_COOR (ISP35_AWBSYNC_BASE + 0x0001C)
+#define ISP35_AWBSYNC_WIN2_OFFS (ISP35_AWBSYNC_BASE + 0x00020)
+#define ISP35_AWBSYNC_WIN2_RD_COOR (ISP35_AWBSYNC_BASE + 0x00024)
+#define ISP35_AWBSYNC_WIN0_SUMR (ISP35_AWBSYNC_BASE + 0x00030)
+#define ISP35_AWBSYNC_WIN0_SUMG (ISP35_AWBSYNC_BASE + 0x00034)
+#define ISP35_AWBSYNC_WIN0_SUMB (ISP35_AWBSYNC_BASE + 0x00038)
+#define ISP35_AWBSYNC_WIN0_SUMP (ISP35_AWBSYNC_BASE + 0x0003C)
+#define ISP35_AWBSYNC_WIN1_SUMR (ISP35_AWBSYNC_BASE + 0x00040)
+#define ISP35_AWBSYNC_WIN1_SUMG (ISP35_AWBSYNC_BASE + 0x00044)
+#define ISP35_AWBSYNC_WIN1_SUMB (ISP35_AWBSYNC_BASE + 0x00048)
+#define ISP35_AWBSYNC_WIN1_SUMP (ISP35_AWBSYNC_BASE + 0x0004C)
+#define ISP35_AWBSYNC_WIN2_SUMR (ISP35_AWBSYNC_BASE + 0x00050)
+#define ISP35_AWBSYNC_WIN2_SUMG (ISP35_AWBSYNC_BASE + 0x00054)
+#define ISP35_AWBSYNC_WIN2_SUMB (ISP35_AWBSYNC_BASE + 0x00058)
+#define ISP35_AWBSYNC_WIN2_SUMP (ISP35_AWBSYNC_BASE + 0x0005C)
+#define ISP35_AWBSYNC_DBG0 (ISP35_AWBSYNC_BASE + 0x00060)
+
+#define ISP3X_GAIN_BASE 0x00003F00
+#define ISP3X_GAIN_CTRL (ISP3X_GAIN_BASE + 0x00000)
+#define ISP3X_GAIN_G0 (ISP3X_GAIN_BASE + 0x00004)
+#define ISP3X_GAIN_G1_G2 (ISP3X_GAIN_BASE + 0x00008)
+#define ISP3X_GAIN_FIFO_STATUS (ISP3X_GAIN_BASE + 0x0000C)
+
+#define ISP39_COMMON3A_BASE 0x00004000
+#define ISP39_W3A_CTRL0 (ISP39_COMMON3A_BASE + 0x00000)
+#define ISP39_W3A_CTRL1 (ISP39_COMMON3A_BASE + 0x00004)
+#define ISP39_W3A_INT_EN (ISP39_COMMON3A_BASE + 0x00010)
+#define ISP39_W3A_INT_STAT (ISP39_COMMON3A_BASE + 0x00014)
+#define ISP39_W3A_INT_MASK (ISP39_COMMON3A_BASE + 0x00018)
+#define ISP39_W3A_AEBIG_ADDR (ISP39_COMMON3A_BASE + 0x00020)
+#define ISP39_W3A_AE0_ADDR (ISP39_COMMON3A_BASE + 0x00024)
+#define ISP39_W3A_AF_ADDR (ISP39_COMMON3A_BASE + 0x00030)
+#define ISP39_W3A_AWB_ADDR (ISP39_COMMON3A_BASE + 0x00034)
+#define ISP39_W3A_PDAF_ADDR (ISP39_COMMON3A_BASE + 0x00038)
+#define ISP39_W3A_AEBIG_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00040)
+#define ISP39_W3A_AE0_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00044)
+#define ISP39_W3A_AF_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00050)
+#define ISP39_W3A_AWB_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00054)
+#define ISP39_W3A_PDAF_ADDR_SHD (ISP39_COMMON3A_BASE + 0x00058)
+#define ISP39_VI3A_CTRL0 (ISP39_COMMON3A_BASE + 0x00080)
+#define ISP39_VI3A_CTRL1 (ISP39_COMMON3A_BASE + 0x00084)
+#define ISP39_VI3A_INT_EN (ISP39_COMMON3A_BASE + 0x00090)
+#define ISP39_VI3A_INT_STAT (ISP39_COMMON3A_BASE + 0x00094)
+#define ISP39_VI3A_INT_MASK (ISP39_COMMON3A_BASE + 0x00098)
+#define ISP39_VI3A_BLS_FIXED_0 (ISP39_COMMON3A_BASE + 0x000a0)
+#define ISP39_VI3A_BLS_FIXED_1 (ISP39_COMMON3A_BASE + 0x000a4)
+#define ISP39_VI3A_GAIN_0 (ISP39_COMMON3A_BASE + 0x000a8)
+#define ISP39_VI3A_GAIN_1 (ISP39_COMMON3A_BASE + 0x000ac)
+#define ISP39_W3A_DBG0 (ISP39_COMMON3A_BASE + 0x000f0)
+
+#define ISP3X_RAWAE_LITE_BASE 0x00004500
+#define ISP3X_RAWAE_LITE_CTRL (ISP3X_RAWAE_LITE_BASE + 0x00000)
+#define ISP3X_RAWAE_LITE_BLK_SIZ (ISP3X_RAWAE_LITE_BASE + 0x00004)
+#define ISP3X_RAWAE_LITE_OFFSET (ISP3X_RAWAE_LITE_BASE + 0x00008)
+#define ISP3X_RAWAE_LITE_RO_MEAN (ISP3X_RAWAE_LITE_BASE + 0x00010)
+#define ISP3X_RAWAE_LITE_RO_DBG1 (ISP3X_RAWAE_LITE_BASE + 0x00074)
+#define ISP3X_RAWAE_LITE_RO_DBG2 (ISP3X_RAWAE_LITE_BASE + 0x00078)
+
+#define ISP3X_RAWAE_BIG1_BASE 0x00004400
+#define ISP3X_RAWAE_BIG2_BASE 0x00004600
+#define ISP3X_RAWAE_BIG3_BASE 0x00004700
+#define ISP3X_RAWAE_BIG_CTRL 0x00000
+#define ISP3X_RAWAE_BIG_BLK_SIZE 0x00004
+#define ISP3X_RAWAE_BIG_OFFSET 0x00008
+#define ISP3X_RAWAE_BIG_RAM_CTRL 0x0000c
+#define ISP3X_RAWAE_BIG_WND1_SIZE 0x00010
+#define ISP3X_RAWAE_BIG_WND1_OFFSET 0x00014
+#define ISP3X_RAWAE_BIG_WND2_SIZE 0x00018
+#define ISP3X_RAWAE_BIG_WND2_OFFSET 0x0001c
+#define ISP3X_RAWAE_BIG_WND3_SIZE 0x00020
+#define ISP3X_RAWAE_BIG_WND3_OFFSET 0x00024
+#define ISP3X_RAWAE_BIG_WND4_SIZE 0x00028
+#define ISP3X_RAWAE_BIG_WND4_OFFSET 0x0002c
+#define ISP3X_RAWAE_BIG_WND1_SUMR 0x00030
+#define ISP3X_RAWAE_BIG_WND2_SUMR 0x00034
+#define ISP3X_RAWAE_BIG_WND3_SUMR 0x00038
+#define ISP3X_RAWAE_BIG_WND4_SUMR 0x0003c
+#define ISP3X_RAWAE_BIG_WND1_SUMG 0x00040
+#define ISP3X_RAWAE_BIG_WND2_SUMG 0x00044
+#define ISP3X_RAWAE_BIG_WND3_SUMG 0x00048
+#define ISP3X_RAWAE_BIG_WND4_SUMG 0x0004c
+#define ISP3X_RAWAE_BIG_WND1_SUMB 0x00050
+#define ISP3X_RAWAE_BIG_WND2_SUMB 0x00054
+#define ISP3X_RAWAE_BIG_WND3_SUMB 0x00058
+#define ISP3X_RAWAE_BIG_WND4_SUMB 0x0005c
+#define ISP3X_RAWAE_BIG_RO_DBG1 0x00060
+#define ISP3X_RAWAE_BIG_RO_DBG2 0x00064
+#define ISP3X_RAWAE_BIG_RO_DBG3 0x00068
+#define ISP3X_RAWAE_BIG_RO_MEAN_BASE_ADDR 0x00080
+
+#define ISP3X_RAWHIST_LITE_BASE 0x00004900
+#define ISP3X_RAWHIST_LITE_CTRL (ISP3X_RAWHIST_LITE_BASE + 0x00000)
+#define ISP3X_RAWHIST_LITE_SIZE (ISP3X_RAWHIST_LITE_BASE + 0x00004)
+#define ISP3X_RAWHIST_LITE_OFFS (ISP3X_RAWHIST_LITE_BASE + 0x00008)
+#define ISP3X_RAWHIST_LITE_RAM_CTRL (ISP3X_RAWHIST_LITE_BASE + 0x0000c)
+#define ISP3X_RAWHIST_LITE_RAW2Y_CC (ISP3X_RAWHIST_LITE_BASE + 0x00010)
+#define ISP3X_RAWHIST_LITE_DBG1 (ISP3X_RAWHIST_LITE_BASE + 0x00020)
+#define ISP3X_RAWHIST_LITE_DBG2 (ISP3X_RAWHIST_LITE_BASE + 0x00024)
+#define ISP3X_RAWHIST_LITE_DBG3 (ISP3X_RAWHIST_LITE_BASE + 0x00028)
+#define ISP3X_RAWHIST_LITE_WEIGHT (ISP3X_RAWHIST_LITE_BASE + 0x00040)
+#define ISP3X_RAWHIST_LITE_RO_BASE_BIN (ISP3X_RAWHIST_LITE_BASE + 0x00080)
+
+#define ISP3X_RAWHIST_BIG1_BASE 0x00004800
+#define ISP3X_RAWHIST_BIG2_BASE 0x00004A00
+#define ISP3X_RAWHIST_BIG3_BASE 0x00004B00
+#define ISP3X_RAWHIST_BIG_CTRL 0x00000
+#define ISP3X_RAWHIST_BIG_SIZE 0x00004
+#define ISP3X_RAWHIST_BIG_OFFS 0x00008
+#define ISP3X_RAWHIST_BIG_HRAM_CTRL 0x0000C
+#define ISP3X_RAWHIST_BIG_RAW2Y_CC 0x00010
+#define ISP3X_RAWHIST_BIG_WRAM_CTRL 0x00014
+#define ISP3X_RAWHIST_BIG_DBG1 0x00020
+#define ISP3X_RAWHIST_BIG_DBG2 0x00024
+#define ISP3X_RAWHIST_BIG_DBG3 0x00028
+#define ISP3X_RAWHIST_BIG_WEIGHT_BASE 0x00040
+#define ISP3X_RAWHIST_BIG_RO_BASE_BIN 0x00080
+
+#define ISP3X_RAWAF_BASE 0x00004D00
+#define ISP3X_RAWAF_CTRL (ISP3X_RAWAF_BASE + 0x00000)
+#define ISP3X_RAWAF_OFFSET_WINA (ISP3X_RAWAF_BASE + 0x00004)
+#define ISP3X_RAWAF_SIZE_WINA (ISP3X_RAWAF_BASE + 0x00008)
+#define ISP3X_RAWAF_OFFSET_WINB (ISP3X_RAWAF_BASE + 0x0000c)
+#define ISP3X_RAWAF_SIZE_WINB (ISP3X_RAWAF_BASE + 0x00010)
+#define ISP3X_RAWAF_INT_LINE (ISP3X_RAWAF_BASE + 0x00014)
+#define ISP32L_RAWAF_CTRL1 (ISP3X_RAWAF_BASE + 0x00018)
+#define ISP3X_RAWAF_THRES (ISP3X_RAWAF_BASE + 0x0001c)
+#define ISP3X_RAWAF_VAR_SHIFT (ISP3X_RAWAF_BASE + 0x00020)
+#define ISP3X_RAWAF_HVIIR_VAR_SHIFT (ISP3X_RAWAF_BASE + 0x00024)
+#define ISP3X_RAWAF_SUM_B (ISP3X_RAWAF_BASE + 0x00028)
+#define ISP3X_RAWAF_LUM_B (ISP3X_RAWAF_BASE + 0x00030)
+#define ISP3X_RAWAF_GAMMA_Y0 (ISP3X_RAWAF_BASE + 0x00034)
+#define ISP3X_RAWAF_GAMMA_Y1 (ISP3X_RAWAF_BASE + 0x00038)
+#define ISP3X_RAWAF_GAMMA_Y2 (ISP3X_RAWAF_BASE + 0x0003c)
+#define ISP3X_RAWAF_GAMMA_Y3 (ISP3X_RAWAF_BASE + 0x00040)
+#define ISP3X_RAWAF_GAMMA_Y4 (ISP3X_RAWAF_BASE + 0x00044)
+#define ISP3X_RAWAF_GAMMA_Y5 (ISP3X_RAWAF_BASE + 0x00048)
+#define ISP3X_RAWAF_GAMMA_Y6 (ISP3X_RAWAF_BASE + 0x0004c)
+#define ISP3X_RAWAF_GAMMA_Y7 (ISP3X_RAWAF_BASE + 0x00050)
+#define ISP3X_RAWAF_GAMMA_Y8 (ISP3X_RAWAF_BASE + 0x00054)
+#define ISP3X_RAWAF_INT_STATE (ISP3X_RAWAF_BASE + 0x00058)
+#define ISP3X_RAWAF_HIIR_THRESH (ISP3X_RAWAF_BASE + 0x0005c)
+#define ISP3X_RAWAF_H1_IIR1_COE01 (ISP3X_RAWAF_BASE + 0x00060)
+#define ISP3X_RAWAF_H1_IIR1_COE23 (ISP3X_RAWAF_BASE + 0x00064)
+#define ISP3X_RAWAF_H1_IIR1_COE45 (ISP3X_RAWAF_BASE + 0x00068)
+#define ISP3X_RAWAF_H_CURVEL (ISP3X_RAWAF_BASE + 0x0006C)
+#define ISP3X_RAWAF_H1_IIR2_COE01 (ISP3X_RAWAF_BASE + 0x00070)
+#define ISP3X_RAWAF_H1_IIR2_COE23 (ISP3X_RAWAF_BASE + 0x00074)
+#define ISP3X_RAWAF_H1_IIR2_COE45 (ISP3X_RAWAF_BASE + 0x00078)
+#define ISP3X_RAWAF_H_CURVEH (ISP3X_RAWAF_BASE + 0x0007C)
+#define ISP3X_RAWAF_H2_IIR1_COE01 (ISP3X_RAWAF_BASE + 0x00080)
+#define ISP3X_RAWAF_H2_IIR1_COE23 (ISP3X_RAWAF_BASE + 0x00084)
+#define ISP3X_RAWAF_H2_IIR1_COE45 (ISP3X_RAWAF_BASE + 0x00088)
+#define ISP3X_RAWAF_V_CURVEL (ISP3X_RAWAF_BASE + 0x0008C)
+#define ISP3X_RAWAF_H2_IIR2_COE01 (ISP3X_RAWAF_BASE + 0x00090)
+#define ISP3X_RAWAF_H2_IIR2_COE23 (ISP3X_RAWAF_BASE + 0x00094)
+#define ISP3X_RAWAF_H2_IIR2_COE45 (ISP3X_RAWAF_BASE + 0x00098)
+#define ISP3X_RAWAF_V_CURVEH (ISP3X_RAWAF_BASE + 0x0009C)
+#define ISP3X_RAWAF_V_IIR_COE0 (ISP3X_RAWAF_BASE + 0x000A0)
+#define ISP3X_RAWAF_V_IIR_COE1 (ISP3X_RAWAF_BASE + 0x000A4)
+#define ISP3X_RAWAF_V_IIR_COE2 (ISP3X_RAWAF_BASE + 0x000A8)
+#define ISP3X_RAWAF_V_IIR_COE3 (ISP3X_RAWAF_BASE + 0x000AC)
+#define ISP3X_RAWAF_V_IIR_COE4 (ISP3X_RAWAF_BASE + 0x000B0)
+#define ISP3X_RAWAF_V_IIR_COE5 (ISP3X_RAWAF_BASE + 0x000B4)
+#define ISP3X_RAWAF_V_IIR_COE6 (ISP3X_RAWAF_BASE + 0x000B8)
+#define ISP3X_RAWAF_V_IIR_COE7 (ISP3X_RAWAF_BASE + 0x000BC)
+#define ISP3X_RAWAF_V_IIR_COE8 (ISP3X_RAWAF_BASE + 0x000C0)
+#define ISP3X_RAWAF_V_FIR_COE0 (ISP3X_RAWAF_BASE + 0x000C4)
+#define ISP3X_RAWAF_V_FIR_COE1 (ISP3X_RAWAF_BASE + 0x000C8)
+#define ISP3X_RAWAF_V_FIR_COE2 (ISP3X_RAWAF_BASE + 0x000CC)
+#define ISP32_RAWAF_V_FIR_COE0 (ISP3X_RAWAF_BASE + 0x000b0)
+#define ISP32_RAWAF_V_FIR_COE1 (ISP3X_RAWAF_BASE + 0x000b4)
+#define ISP32_RAWAF_V_FIR_COE2 (ISP3X_RAWAF_BASE + 0x000b8)
+#define ISP32_RAWAF_GAUS_COE03 (ISP3X_RAWAF_BASE + 0x000c0)
+#define ISP32_RAWAF_GAUS_COE47 (ISP3X_RAWAF_BASE + 0x000c4)
+#define ISP32_RAWAF_GAUS_COE8 (ISP3X_RAWAF_BASE + 0x000c8)
+#define ISP3X_RAWAF_HIGHLIT_THRESH (ISP3X_RAWAF_BASE + 0x000D0)
+#define ISP3X_RAWAF_HIGHLIT_CNT_WINB (ISP3X_RAWAF_BASE + 0x000D8)
+#define ISP3X_RAWAF_RAM_DATA (ISP3X_RAWAF_BASE + 0x000E0)
+#define ISP32L_RAWAF_CORING_H (ISP3X_RAWAF_BASE + 0x000AC)
+#define ISP32L_RAWAF_CORING_V (ISP3X_RAWAF_BASE + 0x000BC)
+#define ISP39_RAWAF_HIGHLIT_CNT_WINB (ISP3X_RAWAF_BASE + 0x0001C)
+#define ISP39_RAWAF_H1IIR_SUMB (ISP3X_RAWAF_BASE + 0x00020)
+#define ISP39_RAWAF_H2IIR_SUMB (ISP3X_RAWAF_BASE + 0x00024)
+#define ISP39_RAWAF_V1IIR_SUMB (ISP3X_RAWAF_BASE + 0x00028)
+#define ISP39_RAWAF_V2IIR_SUMB (ISP3X_RAWAF_BASE + 0x0002c)
+#define ISP39_RAWAF_HVIIR_VAR_SHIFT (ISP3X_RAWAF_BASE + 0x000cc)
+#define ISP39_RAWAF_THRES (ISP3X_RAWAF_BASE + 0x000d8)
+
+#define ISP3X_RAWAWB_BASE 0x00005000
+#define ISP3X_RAWAWB_CTRL (ISP3X_RAWAWB_BASE + 0x0000)
+#define ISP3X_RAWAWB_BLK_CTRL (ISP3X_RAWAWB_BASE + 0x0004)
+#define ISP3X_RAWAWB_WIN_OFFS (ISP3X_RAWAWB_BASE + 0x0008)
+#define ISP3X_RAWAWB_WIN_SIZE (ISP3X_RAWAWB_BASE + 0x000c)
+#define ISP3X_RAWAWB_LIMIT_RG_MAX (ISP3X_RAWAWB_BASE + 0x0010)
+#define ISP3X_RAWAWB_LIMIT_BY_MAX (ISP3X_RAWAWB_BASE + 0x0014)
+#define ISP3X_RAWAWB_LIMIT_RG_MIN (ISP3X_RAWAWB_BASE + 0x0018)
+#define ISP3X_RAWAWB_LIMIT_BY_MIN (ISP3X_RAWAWB_BASE + 0x001c)
+#define ISP3X_RAWAWB_WEIGHT_CURVE_CTRL (ISP3X_RAWAWB_BASE + 0x0020)
+#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03 (ISP3X_RAWAWB_BASE + 0x0024)
+#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47 (ISP3X_RAWAWB_BASE + 0x0028)
+#define ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8 (ISP3X_RAWAWB_BASE + 0x002c)
+#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03 (ISP3X_RAWAWB_BASE + 0x0030)
+#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47 (ISP3X_RAWAWB_BASE + 0x0034)
+#define ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8 (ISP3X_RAWAWB_BASE + 0x0038)
+#define ISP3X_RAWAWB_PRE_WBGAIN_INV (ISP3X_RAWAWB_BASE + 0x003c)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_0 (ISP3X_RAWAWB_BASE + 0x0040)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_0 (ISP3X_RAWAWB_BASE + 0x0044)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_0 (ISP3X_RAWAWB_BASE + 0x0048)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_0 (ISP3X_RAWAWB_BASE + 0x004c)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_0 (ISP3X_RAWAWB_BASE + 0x0050)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_0 (ISP3X_RAWAWB_BASE + 0x0054)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_0 (ISP3X_RAWAWB_BASE + 0x0058)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_0 (ISP3X_RAWAWB_BASE + 0x005c)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_1 (ISP3X_RAWAWB_BASE + 0x0060)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_1 (ISP3X_RAWAWB_BASE + 0x0064)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_1 (ISP3X_RAWAWB_BASE + 0x0068)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_1 (ISP3X_RAWAWB_BASE + 0x006c)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_1 (ISP3X_RAWAWB_BASE + 0x0070)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_1 (ISP3X_RAWAWB_BASE + 0x0074)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_1 (ISP3X_RAWAWB_BASE + 0x0078)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_1 (ISP3X_RAWAWB_BASE + 0x007c)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_2 (ISP3X_RAWAWB_BASE + 0x0080)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_2 (ISP3X_RAWAWB_BASE + 0x0084)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_2 (ISP3X_RAWAWB_BASE + 0x0088)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_2 (ISP3X_RAWAWB_BASE + 0x008c)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_2 (ISP3X_RAWAWB_BASE + 0x0090)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_2 (ISP3X_RAWAWB_BASE + 0x0094)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_2 (ISP3X_RAWAWB_BASE + 0x0098)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_2 (ISP3X_RAWAWB_BASE + 0x009c)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_3 (ISP3X_RAWAWB_BASE + 0x00a0)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_3 (ISP3X_RAWAWB_BASE + 0x00a4)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_3 (ISP3X_RAWAWB_BASE + 0x00a8)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_3 (ISP3X_RAWAWB_BASE + 0x00ac)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_3 (ISP3X_RAWAWB_BASE + 0x00b0)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_3 (ISP3X_RAWAWB_BASE + 0x00b4)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_3 (ISP3X_RAWAWB_BASE + 0x00b8)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_3 (ISP3X_RAWAWB_BASE + 0x00bc)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_4 (ISP3X_RAWAWB_BASE + 0x00c0)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_4 (ISP3X_RAWAWB_BASE + 0x00c4)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_4 (ISP3X_RAWAWB_BASE + 0x00c8)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_4 (ISP3X_RAWAWB_BASE + 0x00cc)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_4 (ISP3X_RAWAWB_BASE + 0x00d0)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE12_4 (ISP3X_RAWAWB_BASE + 0x00d4)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_4 (ISP3X_RAWAWB_BASE + 0x00d8)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_4 (ISP3X_RAWAWB_BASE + 0x00dc)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_5 (ISP3X_RAWAWB_BASE + 0x00e0)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_5 (ISP3X_RAWAWB_BASE + 0x00e4)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_5 (ISP3X_RAWAWB_BASE + 0x00e8)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_5 (ISP3X_RAWAWB_BASE + 0x00ec)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_5 (ISP3X_RAWAWB_BASE + 0x00f0)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE10_5 (ISP3X_RAWAWB_BASE + 0x00f4)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_5 (ISP3X_RAWAWB_BASE + 0x00f8)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_5 (ISP3X_RAWAWB_BASE + 0x00fc)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX0_6 (ISP3X_RAWAWB_BASE + 0x0100)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX1_6 (ISP3X_RAWAWB_BASE + 0x0104)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX2_6 (ISP3X_RAWAWB_BASE + 0x0108)
+#define ISP3X_RAWAWB_UV_DETC_VERTEX3_6 (ISP3X_RAWAWB_BASE + 0x010c)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE01_6 (ISP3X_RAWAWB_BASE + 0x0110)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE10_6 (ISP3X_RAWAWB_BASE + 0x0114)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE23_6 (ISP3X_RAWAWB_BASE + 0x0118)
+#define ISP3X_RAWAWB_UV_DETC_ISLOPE30_6 (ISP3X_RAWAWB_BASE + 0x011c)
+#define ISP3X_RAWAWB_YUV_RGB2ROTY_0 (ISP3X_RAWAWB_BASE + 0x0120)
+#define ISP3X_RAWAWB_YUV_RGB2ROTY_1 (ISP3X_RAWAWB_BASE + 0x0124)
+#define ISP3X_RAWAWB_YUV_RGB2ROTU_0 (ISP3X_RAWAWB_BASE + 0x0128)
+#define ISP3X_RAWAWB_YUV_RGB2ROTU_1 (ISP3X_RAWAWB_BASE + 0x012c)
+#define ISP3X_RAWAWB_YUV_RGB2ROTV_0 (ISP3X_RAWAWB_BASE + 0x0130)
+#define ISP3X_RAWAWB_YUV_RGB2ROTV_1 (ISP3X_RAWAWB_BASE + 0x0134)
+#define ISP3X_RAWAWB_YUV_X_COOR_Y_0 (ISP3X_RAWAWB_BASE + 0x0140)
+#define ISP3X_RAWAWB_YUV_X_COOR_U_0 (ISP3X_RAWAWB_BASE + 0x0144)
+#define ISP3X_RAWAWB_YUV_X_COOR_V_0 (ISP3X_RAWAWB_BASE + 0x0148)
+#define ISP3X_RAWAWB_YUV_X1X2_DIS_0 (ISP3X_RAWAWB_BASE + 0x014c)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0 (ISP3X_RAWAWB_BASE + 0x0150)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0 (ISP3X_RAWAWB_BASE + 0x0154)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0 (ISP3X_RAWAWB_BASE + 0x0158)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0 (ISP3X_RAWAWB_BASE + 0x015c)
+#define ISP3X_RAWAWB_YUV_X_COOR_Y_1 (ISP3X_RAWAWB_BASE + 0x0160)
+#define ISP3X_RAWAWB_YUV_X_COOR_U_1 (ISP3X_RAWAWB_BASE + 0x0164)
+#define ISP3X_RAWAWB_YUV_X_COOR_V_1 (ISP3X_RAWAWB_BASE + 0x0168)
+#define ISP3X_RAWAWB_YUV_X1X2_DIS_1 (ISP3X_RAWAWB_BASE + 0x016c)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1 (ISP3X_RAWAWB_BASE + 0x0170)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1 (ISP3X_RAWAWB_BASE + 0x0174)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1 (ISP3X_RAWAWB_BASE + 0x0178)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1 (ISP3X_RAWAWB_BASE + 0x017c)
+#define ISP3X_RAWAWB_YUV_X_COOR_Y_2 (ISP3X_RAWAWB_BASE + 0x0180)
+#define ISP3X_RAWAWB_YUV_X_COOR_U_2 (ISP3X_RAWAWB_BASE + 0x0184)
+#define ISP3X_RAWAWB_YUV_X_COOR_V_2 (ISP3X_RAWAWB_BASE + 0x0188)
+#define ISP3X_RAWAWB_YUV_X1X2_DIS_2 (ISP3X_RAWAWB_BASE + 0x018c)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2 (ISP3X_RAWAWB_BASE + 0x0190)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2 (ISP3X_RAWAWB_BASE + 0x0194)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2 (ISP3X_RAWAWB_BASE + 0x0198)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2 (ISP3X_RAWAWB_BASE + 0x019c)
+#define ISP3X_RAWAWB_YUV_X_COOR_Y_3 (ISP3X_RAWAWB_BASE + 0x01a0)
+#define ISP3X_RAWAWB_YUV_X_COOR_U_3 (ISP3X_RAWAWB_BASE + 0x01a4)
+#define ISP3X_RAWAWB_YUV_X_COOR_V_3 (ISP3X_RAWAWB_BASE + 0x01a8)
+#define ISP3X_RAWAWB_YUV_X1X2_DIS_3 (ISP3X_RAWAWB_BASE + 0x01ac)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3 (ISP3X_RAWAWB_BASE + 0x01b0)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3 (ISP3X_RAWAWB_BASE + 0x01b4)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3 (ISP3X_RAWAWB_BASE + 0x01b8)
+#define ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3 (ISP3X_RAWAWB_BASE + 0x01bc)
+#define ISP3X_RAWAWB_RGB2XY_WT01 (ISP3X_RAWAWB_BASE + 0x01fc)
+#define ISP3X_RAWAWB_RGB2XY_WT2 (ISP3X_RAWAWB_BASE + 0x0200)
+#define ISP3X_RAWAWB_RGB2XY_MAT0_XY (ISP3X_RAWAWB_BASE + 0x0204)
+#define ISP3X_RAWAWB_RGB2XY_MAT1_XY (ISP3X_RAWAWB_BASE + 0x0208)
+#define ISP3X_RAWAWB_RGB2XY_MAT2_XY (ISP3X_RAWAWB_BASE + 0x020c)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_0 (ISP3X_RAWAWB_BASE + 0x0210)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_0 (ISP3X_RAWAWB_BASE + 0x0214)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_0 (ISP3X_RAWAWB_BASE + 0x0218)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_0 (ISP3X_RAWAWB_BASE + 0x021c)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_1 (ISP3X_RAWAWB_BASE + 0x0228)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_1 (ISP3X_RAWAWB_BASE + 0x022c)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_1 (ISP3X_RAWAWB_BASE + 0x0230)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_1 (ISP3X_RAWAWB_BASE + 0x0234)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_2 (ISP3X_RAWAWB_BASE + 0x0240)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_2 (ISP3X_RAWAWB_BASE + 0x0244)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_2 (ISP3X_RAWAWB_BASE + 0x0248)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_2 (ISP3X_RAWAWB_BASE + 0x024c)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_3 (ISP3X_RAWAWB_BASE + 0x0258)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_3 (ISP3X_RAWAWB_BASE + 0x025c)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_3 (ISP3X_RAWAWB_BASE + 0x0260)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_3 (ISP3X_RAWAWB_BASE + 0x0264)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_4 (ISP3X_RAWAWB_BASE + 0x0270)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_4 (ISP3X_RAWAWB_BASE + 0x0274)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_4 (ISP3X_RAWAWB_BASE + 0x0278)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_4 (ISP3X_RAWAWB_BASE + 0x027c)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_5 (ISP3X_RAWAWB_BASE + 0x0288)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_5 (ISP3X_RAWAWB_BASE + 0x028c)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_5 (ISP3X_RAWAWB_BASE + 0x0290)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_5 (ISP3X_RAWAWB_BASE + 0x0294)
+#define ISP3X_RAWAWB_XY_DETC_NOR_X_6 (ISP3X_RAWAWB_BASE + 0x02a0)
+#define ISP3X_RAWAWB_XY_DETC_NOR_Y_6 (ISP3X_RAWAWB_BASE + 0x02a4)
+#define ISP3X_RAWAWB_XY_DETC_BIG_X_6 (ISP3X_RAWAWB_BASE + 0x02a8)
+#define ISP3X_RAWAWB_XY_DETC_BIG_Y_6 (ISP3X_RAWAWB_BASE + 0x02ac)
+#define ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP3X_RAWAWB_BASE + 0x02b8)
+#define ISP3X_RAWAWB_MULTIWINDOW0_OFFS (ISP3X_RAWAWB_BASE + 0x02bc)
+#define ISP3X_RAWAWB_MULTIWINDOW0_SIZE (ISP3X_RAWAWB_BASE + 0x02c0)
+#define ISP3X_RAWAWB_MULTIWINDOW1_OFFS (ISP3X_RAWAWB_BASE + 0x02c4)
+#define ISP3X_RAWAWB_MULTIWINDOW1_SIZE (ISP3X_RAWAWB_BASE + 0x02c8)
+#define ISP3X_RAWAWB_MULTIWINDOW2_OFFS (ISP3X_RAWAWB_BASE + 0x02cc)
+#define ISP3X_RAWAWB_MULTIWINDOW2_SIZE (ISP3X_RAWAWB_BASE + 0x02d0)
+#define ISP3X_RAWAWB_MULTIWINDOW3_OFFS (ISP3X_RAWAWB_BASE + 0x02d4)
+#define ISP3X_RAWAWB_MULTIWINDOW3_SIZE (ISP3X_RAWAWB_BASE + 0x02d8)
+#define ISP3X_RAWAWB_EXC_WP_REGION0_XU (ISP3X_RAWAWB_BASE + 0x02fc)
+#define ISP3X_RAWAWB_EXC_WP_REGION0_YV (ISP3X_RAWAWB_BASE + 0x0300)
+#define ISP3X_RAWAWB_EXC_WP_REGION1_XU (ISP3X_RAWAWB_BASE + 0x0304)
+#define ISP3X_RAWAWB_EXC_WP_REGION1_YV (ISP3X_RAWAWB_BASE + 0x0308)
+#define ISP3X_RAWAWB_EXC_WP_REGION2_XU (ISP3X_RAWAWB_BASE + 0x030c)
+#define ISP3X_RAWAWB_EXC_WP_REGION2_YV (ISP3X_RAWAWB_BASE + 0x0310)
+#define ISP3X_RAWAWB_EXC_WP_REGION3_XU (ISP3X_RAWAWB_BASE + 0x0314)
+#define ISP3X_RAWAWB_EXC_WP_REGION3_YV (ISP3X_RAWAWB_BASE + 0x0318)
+#define ISP3X_RAWAWB_EXC_WP_REGION4_XU (ISP3X_RAWAWB_BASE + 0x031c)
+#define ISP3X_RAWAWB_EXC_WP_REGION4_YV (ISP3X_RAWAWB_BASE + 0x0320)
+#define ISP3X_RAWAWB_EXC_WP_REGION5_XU (ISP3X_RAWAWB_BASE + 0x0324)
+#define ISP3X_RAWAWB_EXC_WP_REGION5_YV (ISP3X_RAWAWB_BASE + 0x0328)
+#define ISP3X_RAWAWB_EXC_WP_REGION6_XU (ISP3X_RAWAWB_BASE + 0x032c)
+#define ISP3X_RAWAWB_EXC_WP_REGION6_YV (ISP3X_RAWAWB_BASE + 0x0330)
+#define ISP32_RAWAWB_EXC_WP_WEIGHT0_3 (ISP3X_RAWAWB_BASE + 0x0334)
+#define ISP32_RAWAWB_EXC_WP_WEIGHT4_6 (ISP3X_RAWAWB_BASE + 0x0338)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_0 (ISP3X_RAWAWB_BASE + 0x0340)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_0 (ISP3X_RAWAWB_BASE + 0x0348)
+#define ISP3X_RAWAWB_WP_NUM_NOR_0 (ISP3X_RAWAWB_BASE + 0x034c)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_0 (ISP3X_RAWAWB_BASE + 0x0350)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_0 (ISP3X_RAWAWB_BASE + 0x0358)
+#define ISP3X_RAWAWB_WP_NUM_BIG_0 (ISP3X_RAWAWB_BASE + 0x035c)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_1 (ISP3X_RAWAWB_BASE + 0x0370)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_1 (ISP3X_RAWAWB_BASE + 0x0378)
+#define ISP3X_RAWAWB_WP_NUM_NOR_1 (ISP3X_RAWAWB_BASE + 0x037c)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_1 (ISP3X_RAWAWB_BASE + 0x0380)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_1 (ISP3X_RAWAWB_BASE + 0x0388)
+#define ISP3X_RAWAWB_WP_NUM_BIG_1 (ISP3X_RAWAWB_BASE + 0x038c)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_2 (ISP3X_RAWAWB_BASE + 0x03a0)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_2 (ISP3X_RAWAWB_BASE + 0x03a8)
+#define ISP3X_RAWAWB_WP_NUM_NOR_2 (ISP3X_RAWAWB_BASE + 0x03ac)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_2 (ISP3X_RAWAWB_BASE + 0x03b0)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_2 (ISP3X_RAWAWB_BASE + 0x03b8)
+#define ISP3X_RAWAWB_WP_NUM_BIG_2 (ISP3X_RAWAWB_BASE + 0x03bc)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_3 (ISP3X_RAWAWB_BASE + 0x03d0)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_3 (ISP3X_RAWAWB_BASE + 0x03d8)
+#define ISP3X_RAWAWB_WP_NUM_NOR_3 (ISP3X_RAWAWB_BASE + 0x03dc)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_3 (ISP3X_RAWAWB_BASE + 0x03e0)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_3 (ISP3X_RAWAWB_BASE + 0x03e8)
+#define ISP3X_RAWAWB_WP_NUM_BIG_3 (ISP3X_RAWAWB_BASE + 0x03ec)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_4 (ISP3X_RAWAWB_BASE + 0x0400)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_4 (ISP3X_RAWAWB_BASE + 0x0408)
+#define ISP3X_RAWAWB_WP_NUM_NOR_4 (ISP3X_RAWAWB_BASE + 0x040c)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_4 (ISP3X_RAWAWB_BASE + 0x0410)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_4 (ISP3X_RAWAWB_BASE + 0x0418)
+#define ISP3X_RAWAWB_WP_NUM_BIG_4 (ISP3X_RAWAWB_BASE + 0x041c)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_5 (ISP3X_RAWAWB_BASE + 0x0430)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_5 (ISP3X_RAWAWB_BASE + 0x0438)
+#define ISP3X_RAWAWB_WP_NUM_NOR_5 (ISP3X_RAWAWB_BASE + 0x043c)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_5 (ISP3X_RAWAWB_BASE + 0x0440)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_5 (ISP3X_RAWAWB_BASE + 0x0448)
+#define ISP3X_RAWAWB_WP_NUM_BIG_5 (ISP3X_RAWAWB_BASE + 0x044c)
+#define ISP3X_RAWAWB_SUM_RGAIN_NOR_6 (ISP3X_RAWAWB_BASE + 0x0460)
+#define ISP3X_RAWAWB_SUM_BGAIN_NOR_6 (ISP3X_RAWAWB_BASE + 0x0468)
+#define ISP3X_RAWAWB_WP_NUM_NOR_6 (ISP3X_RAWAWB_BASE + 0x046c)
+#define ISP3X_RAWAWB_SUM_RGAIN_BIG_6 (ISP3X_RAWAWB_BASE + 0x0470)
+#define ISP3X_RAWAWB_SUM_BGAIN_BIG_6 (ISP3X_RAWAWB_BASE + 0x0478)
+#define ISP3X_RAWAWB_WP_NUM_BIG_6 (ISP3X_RAWAWB_BASE + 0x047c)
+#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x0490)
+#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x0498)
+#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x049c)
+#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04a0)
+#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04a8)
+#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW0 (ISP3X_RAWAWB_BASE + 0x04ac)
+#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04c0)
+#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04c8)
+#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04cc)
+#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04d0)
+#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04d8)
+#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW1 (ISP3X_RAWAWB_BASE + 0x04dc)
+#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04f0)
+#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04f8)
+#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x04fc)
+#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x0500)
+#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x0508)
+#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW2 (ISP3X_RAWAWB_BASE + 0x050c)
+#define ISP3X_RAWAWB_SUM_R_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0520)
+#define ISP3X_RAWAWB_SUM_B_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0528)
+#define ISP3X_RAWAWB_WP_NM_NOR_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x052c)
+#define ISP3X_RAWAWB_SUM_R_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0530)
+#define ISP3X_RAWAWB_SUM_B_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x0538)
+#define ISP3X_RAWAWB_WP_NM_BIG_MULTIWINDOW3 (ISP3X_RAWAWB_BASE + 0x053c)
+#define ISP3X_RAWAWB_SUM_R_EXC0 (ISP3X_RAWAWB_BASE + 0x05e0)
+#define ISP3X_RAWAWB_SUM_B_EXC0 (ISP3X_RAWAWB_BASE + 0x05e8)
+#define ISP3X_RAWAWB_WP_NM_EXC0 (ISP3X_RAWAWB_BASE + 0x05ec)
+#define ISP3X_RAWAWB_SUM_R_EXC1 (ISP3X_RAWAWB_BASE + 0x05f0)
+#define ISP3X_RAWAWB_SUM_B_EXC1 (ISP3X_RAWAWB_BASE + 0x05f8)
+#define ISP3X_RAWAWB_WP_NM_EXC1 (ISP3X_RAWAWB_BASE + 0x05fc)
+#define ISP3X_RAWAWB_SUM_R_EXC2 (ISP3X_RAWAWB_BASE + 0x0600)
+#define ISP3X_RAWAWB_SUM_B_EXC2 (ISP3X_RAWAWB_BASE + 0x0608)
+#define ISP3X_RAWAWB_WP_NM_EXC2 (ISP3X_RAWAWB_BASE + 0x060c)
+#define ISP3X_RAWAWB_SUM_R_EXC3 (ISP3X_RAWAWB_BASE + 0x0610)
+#define ISP3X_RAWAWB_SUM_B_EXC3 (ISP3X_RAWAWB_BASE + 0x0618)
+#define ISP3X_RAWAWB_WP_NM_EXC3 (ISP3X_RAWAWB_BASE + 0x061c)
+#define ISP3X_RAWAWB_Y_HIST01 (ISP3X_RAWAWB_BASE + 0x0620)
+#define ISP3X_RAWAWB_Y_HIST23 (ISP3X_RAWAWB_BASE + 0x0624)
+#define ISP3X_RAWAWB_Y_HIST45 (ISP3X_RAWAWB_BASE + 0x0628)
+#define ISP3X_RAWAWB_Y_HIST67 (ISP3X_RAWAWB_BASE + 0x062c)
+#define ISP3X_RAWAWB_WPNUM2_0 (ISP3X_RAWAWB_BASE + 0x0630)
+#define ISP3X_RAWAWB_WPNUM2_1 (ISP3X_RAWAWB_BASE + 0x0634)
+#define ISP3X_RAWAWB_WPNUM2_2 (ISP3X_RAWAWB_BASE + 0x0638)
+#define ISP3X_RAWAWB_WPNUM2_3 (ISP3X_RAWAWB_BASE + 0x063c)
+#define ISP3X_RAWAWB_WPNUM2_4 (ISP3X_RAWAWB_BASE + 0x0640)
+#define ISP3X_RAWAWB_WPNUM2_5 (ISP3X_RAWAWB_BASE + 0x0644)
+#define ISP3X_RAWAWB_WPNUM2_6 (ISP3X_RAWAWB_BASE + 0x0648)
+#define ISP3X_RAWAWB_RAM_CTRL (ISP3X_RAWAWB_BASE + 0x0650)
+#define ISP3X_RAWAWB_WRAM_CTRL (ISP3X_RAWAWB_BASE + 0x0654)
+#define ISP3X_RAWAWB_WRAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0660)
+#define ISP3X_RAWAWB_RAM_DATA_BASE (ISP3X_RAWAWB_BASE + 0x0700)
+#define ISP32L_RAWAWB_WIN_WEIGHT_0 (ISP3X_RAWAWB_BASE + 0x0660)
+#define ISP32L_RAWAWB_WIN_WEIGHT_1 (ISP3X_RAWAWB_BASE + 0x0664)
+#define ISP32L_RAWAWB_WIN_WEIGHT_2 (ISP3X_RAWAWB_BASE + 0x0668)
+#define ISP32L_RAWAWB_WIN_WEIGHT_3 (ISP3X_RAWAWB_BASE + 0x066c)
+#define ISP32L_RAWAWB_WIN_WEIGHT_4 (ISP3X_RAWAWB_BASE + 0x0670)
+#define ISP33_RAWAWB_CCM_COEFF0_R (ISP3X_RAWAWB_BASE + 0x01c0)
+#define ISP33_RAWAWB_CCM_COEFF1_R (ISP3X_RAWAWB_BASE + 0x01c4)
+#define ISP33_RAWAWB_CCM_COEFF0_G (ISP3X_RAWAWB_BASE + 0x01c8)
+#define ISP33_RAWAWB_CCM_COEFF1_G (ISP3X_RAWAWB_BASE + 0x01cc)
+#define ISP33_RAWAWB_CCM_COEFF0_B (ISP3X_RAWAWB_BASE + 0x01d0)
+#define ISP33_RAWAWB_CCM_COEFF1_B (ISP3X_RAWAWB_BASE + 0x01d4)
+
+#define ISP35_AIAWB_BASE 0x00005a00
+#define ISP35_AIAWB_CTRL0 (ISP35_AIAWB_BASE + 0x0000)
+#define ISP35_AIAWB_CTRL1 (ISP35_AIAWB_BASE + 0x0004)
+#define ISP35_AIAWB_WIN_OFFS (ISP35_AIAWB_BASE + 0x0008)
+#define ISP35_AIAWB_WIN_SIZE (ISP35_AIAWB_BASE + 0x000c)
+#define ISP35_AIAWB_FLT_COE0 (ISP35_AIAWB_BASE + 0x0010)
+#define ISP35_AIAWB_FLT_COE1 (ISP35_AIAWB_BASE + 0x0014)
+#define ISP35_AIAWB_WBGAIN_INV0 (ISP35_AIAWB_BASE + 0x0018)
+#define ISP35_AIAWB_WBGAIN_INV1 (ISP35_AIAWB_BASE + 0x001c)
+#define ISP35_AIAWB_MATRIX_SCALE (ISP35_AIAWB_BASE + 0x0020)
+#define ISP35_AIAWB_MATRIX_ROT0 (ISP35_AIAWB_BASE + 0x0024)
+#define ISP35_AIAWB_MATRIX_ROT1 (ISP35_AIAWB_BASE + 0x0028)
+#define ISP35_AIAWB_WR_BASE (ISP35_AIAWB_BASE + 0x0030)
+#define ISP35_AIAWB_WR_BASE_SHD (ISP35_AIAWB_BASE + 0x0034)
+#define ISP35_AIAWB_WR_BASE_VIR (ISP35_AIAWB_BASE + 0x0038)
+
+/* VI_ISP_PATH */
+#define ISP3X_RAWAE3_SEL(x) (((x) & 3) << 16)
+#define ISP3X_RAWAF_SEL(x) (((x) & 3) << 18)
+#define ISP3X_RAWAWB_SEL(x) (((x) & 3) << 20)
+#define ISP3X_RAWAE012_SEL(x) (((x) & 3) << 22)
+#define ISP3X_LSC_CFG_SEL(x) (((x) & 3) << 24)
+#define ISP32_BNR2AWB_SEL BIT(26)
+#define ISP32_DRC2AWB_SEL BIT(27)
+#define ISP32L_BNR2AF_SEL BIT(28)
+
+/* VI_ICCL */
+#define ISP32_BRSZ_CLK_ENABLE BIT(13)
+
+/* VI_ISP_CLK_CTRL */
+#define ISP3X_CLK_RSZM BIT(26)
+#define ISP3X_CLK_RSZS BIT(29)
+
+/* SWS_CFG */
+#define ISP32L_ISP2ENC_CNT_MUX BIT(0)
+#define ISP33_PP_ENC_PIPE_EN BIT(1)
+#define ISP3X_SW_ACK_FRM_PRO_DIS BIT(3)
+#define ISP33_SW_ISP2ENC_PATH_EN BIT(5)
+#define ISP3X_3A_DDR_WRITE_EN BIT(24)
+#define ISP3X_SW_MIPI2ISP_FIFO_DIS BIT(25)
+#define ISP3X_SW_3D_DBR_START_MODE BIT(26)
+
+/* CMSK */
+#define ISP3X_SW_CMSK_EN BIT(0)
+#define ISP3X_SW_CMSK_EN_MP BIT(1)
+#define ISP3X_SW_CMSK_EN_SP BIT(2)
+#define ISP3X_SW_CMSK_EN_BP BIT(3)
+#define ISP3X_SW_CMSK_BLKSIZE(x) (((x) & 3) << 4)
+
+#define ISP32_SW_CMSK_EN_PATH GENMASK(3, 0)
+#define ISP32_SW_CMSK_EN_PATH_SHD GENMASK(11, 8)
+
+#define ISP3X_SW_CMSK_FORCE_UPD BIT(31)
+
+#define ISP3X_SW_CMSK_ORDER_MODE BIT(6)
+
+#define ISP3X_SW_CMSK_YUV(x, y, z) (((x) & 0xff) | ((y) & 0xff) << 8 | ((z) & 0xff) << 16)
+
+/* ISP CTRL0 */
+#define ISP32_MIR_ENABLE BIT(5)
+#define ISP3X_SW_CGC_YUV_LIMIT BIT(28)
+#define ISP3X_SW_CGC_RATIO_EN BIT(29)
+#define ISP35_ISP_CFG_UPD_FE BIT(31)
+
+/* ISP CTRL1 */
+#define ISP35_BAYER_UPD_FE_EN BIT(0)
+#define ISP35_BAYER_PAT_FE(x) (((x) & 0x3) << 1)
+#define ISP39_YUVME_FST_FRAME BIT(18)
+#define ISP32_SHP_FST_FRAME BIT(19)
+#define ISP3X_YNR_FST_FRAME BIT(23)
+#define ISP3X_ADRC_FST_FRAME BIT(24)
+#define ISP3X_DHAZ_FST_FRAME BIT(25)
+#define ISP3X_CNR_FST_FRAME BIT(26)
+#define ISP3X_RAW3D_FST_FRAME BIT(27)
+#define ISP3X_BIGMODE_FORCE_EN BIT(28)
+#define ISP3X_BIGMODE_MANUAL BIT(29)
+
+#define ISP33_GIC_FST_FRAME BIT(22)
+#define ISP33_ENH_FST_FRAME BIT(24)
+#define ISP33_YHIST_FST_FRAME BIT(25)
+
+/* ISP ACQ_H_OFFS */
+#define ISP3X_SENSOR_MODE(x) (((x) & 3) << 30)
+#define ISP3X_SENSOR_INDEX(x) (((x) & 3) << 28)
+#define ISP3X_ACQ_H_OFFS(x) ((x) & 0x7fff)
+
+#define ISP32L_SENSOR_MODE(x) (((x) & 7) << 20)
+#define ISP32L_SENSOR_FORCE_INDEX(x) (((x) & 0xf) << 24)
+
+/* isp interrupt */
+#define ISP3X_OFF BIT(0)
+#define ISP3X_FRAME BIT(1)
+#define ISP3X_DATA_LOSS BIT(2)
+#define ISP3X_PIC_SIZE_ERROR BIT(3)
+#define ISP3X_SIAWB_DONE BIT(4)
+#define ISP3X_FRAME_IN BIT(5)
+#define ISP3X_V_START BIT(6)
+#define ISP3X_H_START BIT(7)
+#define ISP3X_FLASH_ON BIT(8)
+#define ISP3X_FLASH_OFF BIT(9)
+#define ISP3X_SHUTTER_ON BIT(10)
+#define ISP3X_SHUTTER_OFF BIT(11)
+#define ISP3X_AFM_SUM_OF BIT(12)
+#define ISP3X_AFM_LUM_OF BIT(13)
+#define ISP3X_SIAF_FIN BIT(14)
+#define ISP3X_SIHST_RDY BIT(15)
+#define ISP39_LDCV_END BIT(15)
+#define ISP3X_LSC_LUT_ERR BIT(16)
+#define ISP3X_FLASH_CAP BIT(17)
+#define ISP3X_EXP_END BIT(18)
+#define ISP39_AIISP_LINECNT_DONE BIT(18)
+#define ISP3X_HDR_DONE BIT(20)
+#define ISP3X_DHAZ_DONE BIT(21)
+#define ISP3X_GIAN_ERR BIT(22)
+#define ISP3X_OUT_FRM_END BIT(23)
+#define ISP3X_OUT_FRM_HALF BIT(24)
+#define ISP3X_OUT_FRM_QUARTER BIT(25)
+#define ISP3X_BAY3D_IN_DONE BIT(26)
+#define ISP3X_BAY3D_IN_LINECNT_DONE BIT(27)
+#define ISP3X_BAY3D_POST_ST BIT(28)
+#define ISP3X_BAY3D_FRM_END BIT(29)
+#define ISP3X_FETCH_LUT_END BIT(30)
+
+/* isp3a interrupt */
+#define ISP3X_3A_RAWAE_BIG BIT(0)
+#define ISP3X_3A_RAWAE_CH0 BIT(1)
+#define ISP3X_3A_RAWAE_CH1 BIT(2)
+#define ISP3X_3A_RAWAE_CH2 BIT(3)
+#define ISP3X_3A_RAWHIST_BIG BIT(4)
+#define ISP3X_3A_RAWHIST_CH0 BIT(5)
+#define ISP3X_3A_RAWHIST_CH1 BIT(6)
+#define ISP3X_3A_RAWHIST_CH2 BIT(7)
+#define ISP3X_3A_RAWAF_SUM BIT(8)
+#define ISP3X_3A_RAWAF_LUM BIT(9)
+#define ISP35_AWBSYNC_DONE BIT(9)
+#define ISP3X_3A_RAWAF BIT(10)
+#define ISP3X_3A_RAWAWB BIT(11)
+#define ISP3X_3A_DDR_DONE BIT(12)
+#define ISP35_W3A_ERR BIT(13)
+#define ISP35_AIAWB_DONE BIT(14)
+
+#define ISP3X_ISP_OUT_LINE(a) ((a) & 0x3fff)
+#define ISP3X_ISP_OUT_FRM_CNT(a) (((a) >> 14) & 0x3)
+
+#define ISP33_ISP2ENC_FRM_CNT(a) ((a) & 0xff)
+
+#define ISP32_YNR_LUMA_RDBK_ST BIT(0)
+#define ISP32_YNR_LUMA_RDBK_OFFS(a) (((a) & 0x3fff) << 16)
+#define ISP32_YNR_LUMA_RDBK_RDY BIT(31)
+
+#define ISP39_SLICE_ST BIT(0)
+#define ISP39_SLICE_EN BIT(1)
+#define ISP39_OUT_LINE(a) (((a) >> 16) & 0x3fff)
+#define ISP39_SLICE_DONE BIT(31)
+
+#define ISP39_AIISP_RD_LINECNT(x) ((x) >> 16)
+#define ISP39_AIISP_WR_LINECNT(x) ((x) & 0xffff)
+
+/* DUAL CROP */
+#define ISP3X_DUAL_CROP_FBC_MODE BIT(8)
+
+/* GAMMA OUT */
+#define ISP3X_GAMMA_OUT_EN BIT(0)
+#define ISP3X_GAMMA_OUT_EQU_SEGM BIT(1)
+#define ISP3X_GAMMA_OUT_FINALX4_DENSE BIT(2)
+
+/* RESIZE */
+#define ISP3X_SCL_HPHASE_EN BIT(10)
+#define ISP3X_SCL_CLIP_EN BIT(11)
+#define ISP3X_SCL_IN_CLIP_EN BIT(12)
+#define ISP32_SCL_CLIP_EN BIT(13)
+#define ISP32_SCL_IN_CLIP_EN BIT(14)
+
+#define ISP32_SCALE_AVG_H_EN BIT(8)
+#define ISP32_SCALE_AVG_V_EN BIT(9)
+
+#define ISP32_SCALE_FORCE_UPD BIT(4)
+#define ISP32_SCALE_GEN_UPD BIT(5)
+
+#define ISP32_SCALE_BIL_FACTOR BIT(12)
+#define ISP32_SCALE_AVE_FACTOR BIT(16)
+
+/* LDCV */
+#define ISP39_LDCV_EN BIT(0)
+#define ISP39_LDCV_OUTPUT_YUV400 0
+#define ISP39_LDCV_OUTPUT_YUYV BIT(2)
+#define ISP39_LDCV_OUTPUT_YUV422 BIT(3)
+#define ISP39_LDCV_OUTPUT_YUV420 GENMASK(3, 2)
+#define ISP39_LDCV_UV_SWAP BIT(4)
+#define ISP39_LDCV_LUT_MODE(x) (((x) & 0x3) << 24)
+#define ISP39_LDCV_FORCE_UPD BIT(26)
+#define ISP39_LDCV_MAP_ERROR BIT(28)
+#define ISP39_LDCV_WORKING BIT(30)
+#define ISP39_LDCV_EN_SHD BIT(31)
+
+/* AI */
+#define ISP35_AIISP_EN BIT(0)
+#define ISP35_AIISP_ST BIT(1)
+#define ISP35_AIISP_RAW12_MSB BIT(2)
+#define ISP35_AIISP_HDR_EN BIT(3)
+#define ISP35_AIISP_GIAN_MODE(x) (((x) & 0x3) << 4)
+#define ISP35_NPU_CURVE_EN BIT(6)
+#define ISP35_AIPRE_IIR_EN BIT(8)
+#define ISP35_AIPRE_IIR2DDR_EN BIT(9)
+#define ISP35_AIPRE_GAIN_EN BIT(10)
+#define ISP35_AIPRE_GIAN2DDR_EN BIT(11)
+#define ISP35_AIPRE_YRAW_SEL BIT(12)
+#define ISP35_AIPRE_NL_DDR_MODE BIT(13)
+#define ISP35_AIPRE_GAIN_BYPASS BIT(14)
+#define ISP35_AIPRE_GAIN_MODE BIT(15)
+#define ISP35_AIPRE_NARMAP_INV BIT(16)
+#define ISP35_AIPRE_LUMA2GAIN_DIS BIT(17)
+#define ISP35_AIPRE_ITS_FORCE_UPD BIT(24)
+
+/* MI_WR_CTRL */
+#define ISP3X_MI_SP_WR_OUTPUT_MASK GENMASK(30, 28)
+
+/* mi interrupt */
+#define ISP3X_MI_MP_FRAME BIT(0)
+#define ISP3X_MI_SP_FRAME BIT(1)
+#define ISP3X_MI_MBLK_LINE BIT(2)
+#define ISP3X_MI_FILL_MP_Y BIT(3)
+#define ISP3X_MI_WRAP_MP_Y BIT(4)
+#define ISP3X_MI_WRAP_MP_CB BIT(5)
+#define ISP3X_MI_WRAP_MP_CR BIT(6)
+#define ISP3X_MI_WRAP_SP_Y BIT(7)
+#define ISP3X_MI_WRAP_SP_CB BIT(8)
+#define ISP3X_MI_WARP_SP_CR BIT(9)
+#define ISP3X_MI_FILL_MP_Y2 BIT(10)
+#define ISP3X_MI_DMA_READY BIT(11)
+#define ISP3X_MI_Y12Y_FRAME BIT(12)
+#define ISP3X_MI_Y12C_FRAME BIT(13)
+#define ISP3X_MI_ALL_FRAME BIT(14)
+#define ISP3X_MI_DBR_WR_FRAME BIT(20)
+#define ISP3X_MI_GAIN_WR_FRAME BIT(21)
+#define ISP3X_MI_BAY3D_IIR_FRAME BIT(22)
+#define ISP3X_MI_BAY3D_CUR_FRAME BIT(23)
+#define ISP3X_MI_BAY3D_DS_FRAME BIT(24)
+#define ISP3X_MI_BP_FRAME BIT(25)
+#define ISP3X_MI_WRAP_BP_Y BIT(26)
+#define ISP3X_MI_WRAP_BP_CB BIT(27)
+#define ISP32_MI_MPDS_FRAME BIT(28)
+#define ISP32_MI_BPDS_FRAME BIT(29)
+#define ISP3X_MI_BUS_ERR BIT(30)
+#define ISP3X_MI_MPFBC_FRAME BIT(31)
+
+/* MI_WR_XTD_FORMAT_CTRL */
+#define ISP3X_MI_XTD_FORMAT_MP_UV_SWAP BIT(0)
+#define ISP3X_MI_XTD_FORMAT_SP_UV_SWAP BIT(1)
+
+/* MI_WR_CTRL2 */
+#define ISP3X_MPSELF_UPD BIT(4)
+#define ISP3X_SPSELF_UPD BIT(5)
+#define ISP3X_BPSELF_UPD BIT(6)
+#define ISP3X_BAY3D_RDSELF_UPD BIT(7)
+#define ISP3X_DBR_ENABLE BIT(8)
+#define ISP3X_MIMUX_RAW_ALIGN BIT(9)
+#define ISP3X_DBR_WR_AUTO_UPD BIT(10)
+#define ISP3X_DBR_RDSELF_UPD BIT(11)
+#define ISP3X_GAIN_WR_PINGPONG BIT(12)
+#define ISP3X_GAIN_WR_AUTO_UPD BIT(13)
+#define ISP3X_BAY3D_IIR_WR_AUTO_UPD BIT(16)
+#define ISP3X_BAY3D_CUR_WR_AUTO_UPD BIT(17)
+#define ISP3X_BAY3D_DS_WR_AUTO_UPD BIT(18)
+#define ISP3X_DBR_WRSELF_UPD BIT(20)
+#define ISP3X_GAINSELF_UPD BIT(21)
+#define ISP3X_BAY3D_IIRSELF_UPD BIT(22)
+#define ISP3X_BAY3D_CURSELF_UPD BIT(23)
+#define ISP3X_BAY3D_DSSELF_UPD BIT(24)
+#define ISP32_MPDSSELF_FORCE_UPD BIT(25)
+#define ISP32_BPDSSELF_FORCE_UPD BIT(26)
+#define ISP3X_DBR_ST_MODE BIT(30)
+#define ISP3X_DBR_ST BIT(31)
+
+/* MI_RD_CTRL2 */
+#define ISP3X_RAWX_RD_BURST_MASK GENMASK(23, 22)
+#define ISP3X_RAWX_WR_BURST_MASK GENMASK(21, 20)
+#define ISP3X_RAWX_RD_GROP_MASK GENMASK(19, 18)
+#define ISP3X_RAWX_WR_GROP_MASK GENMASK(17, 16)
+#define ISP39_AIISP_ST BIT(8)
+#define ISP39_AIISP_EN BIT(9)
+#define ISP3X_RAWX_WR_GROP_MODE(x) (((x) & 0x3) << 16)
+#define ISP3X_RAWX_RD_GROP_MODE(x) (((x) & 0x3) << 18)
+#define ISP3X_RAWX_WR_BURST_LEN(x) (((x) & 0x3) << 20)
+#define ISP3X_RAWX_RD_BURST_LEN(x) (((x) & 0x3) << 22)
+#define ISP35_MI_PWR_DIS BIT(25)
+#define ISP3X_MI_NEW_WR_BURST_DIS BIT(31)
+
+/* WR_OUTPUT_FORMAT */
+#define ISP32_MI_OUTPUT_MASK GENMASK(10, 8)
+#define ISP32_MI_OUTPUT_YUV400 0
+#define ISP32_MI_OUTPUT_YUV420 BIT(28)
+#define ISP32_MI_OUTPUT_YUV422 BIT(9)
+#define ISP35_MI_MP_TILE BIT(12)
+#define ISP35_MI_SP_TILE BIT(13)
+
+/* MI_WR_CTRL2_SHD */
+#define ISP32_BP_EN_IN_SHD BIT(4)
+#define ISP32_DBR_WR_EN_IN_SHD BIT(5)
+#define ISP32_GAIN_WR_EN_IN_SHD BIT(6)
+#define ISP32_BAY3D_CUR_WR_EN_IN_SHD BIT(8)
+#define ISP32_BAY3D_IIR_WR_EN_IN_SHD BIT(9)
+#define ISP32_BAY3D_DS_WR_EN_IN_SHD BIT(10)
+#define ISP32_MPDS_EN_IN_SHD BIT(12)
+#define ISP32_BPDS_EN_IN_SHD BIT(13)
+#define ISP32_BP_EN_OUT_SHD BIT(20)
+#define ISP32_DBR_WR_EN_OUT_SHD BIT(21)
+#define ISP32_GAIN_WR_EN_OUT_SHD BIT(22)
+#define ISP32_BAY3D_CUR_WR_EN_OUT_SHD BIT(24)
+#define ISP32_BAY3D_IIR_WR_EN_OUT_SHD BIT(25)
+#define ISP32_BAY3D_DS_WR_EN_OUT_SHD BIT(26)
+#define ISP32_MPDS_EN_OUT_SHD BIT(28)
+#define ISP32_BPDS_EN_OUT_SHD BIT(29)
+
+/* BP_WR_CTRL */
+#define ISP3X_BP_ENABLE BIT(0)
+#define ISP3X_BP_AUTO_UPD BIT(1)
+#define ISP3X_BP_PINGPONG BIT(2)
+#define ISP3X_BP_FORMAT_PLA 0
+#define ISP3X_BP_FORMAT_SPLA BIT(4)
+#define ISP3X_BP_FORMAT_INT BIT(5)
+#define ISP3X_BP_FORMAT_MASK GENMASK(5, 4)
+#define ISP3X_BP_OUTPUT_YUV400 0
+#define ISP3X_BP_OUTPUT_YUV420 BIT(8)
+#define ISP3X_BP_OUTPUT_YUV422 BIT(9)
+#define ISP3X_BP_OUTPUT_MASK GENMASK(10, 8)
+
+/* MPDS/BPDS WR_CTRL */
+#define ISP32_DS_ENABLE BIT(0)
+#define ISP32_DS_AUTO_UPD BIT(1)
+#define ISP32_DS_FORMAT_PLA 0
+#define ISP32_DS_FORMAT_SPLA BIT(4)
+#define ISP32_DS_FORMAT_INT BIT(5)
+#define ISP32_DS_FORMAT_MASK GENMASK(5, 4)
+#define ISP32_DS_OUTPUT_YUV400 0
+#define ISP32_DS_OUTPUT_YUV420 BIT(8)
+#define ISP32_DS_OUTPUT_YUV422 BIT(9)
+#define ISP32_DS_OUTPUT_MASK GENMASK(10, 8)
+#define ISP32_DS_RAM_CLK_DIS BIT(30)
+#define ISP32_DS_DS_DIS BIT(31)
+
+/* WRAP_CTRL */
+#define ISP32_MP_WR_INIT_OFFSET_EN BIT(0)
+#define ISP32_SP_WR_INIT_OFFSET_EN BIT(1)
+#define ISP32_BP_WR_INIT_OFFSET_EN BIT(2)
+#define ISP32_MPDS_WR_INIT_OFFSET_EN BIT(4)
+#define ISP32_BPDS_WR_INIT_OFFSET_EN BIT(5)
+#define ISP32_MP_DYNAMIC_UPD_ADDR BIT(8)
+#define ISP32_SP_DYNAMIC_UPD_ADDR BIT(9)
+#define ISP32_BP_DYNAMIC_UPD_ADDR BIT(10)
+#define ISP32_MPDS_DYNAMIC_UPD_ADDR BIT(11)
+#define ISP32_BPDS_DYNAMIC_UPD_ADDR BIT(12)
+#define ISP32_MP_WR_FRMEND_UPD_DIS BIT(24)
+#define ISP32_SP_WR_FRMEND_UPD_DIS BIT(25)
+#define ISP32_BP_WR_FRMEND_UPD_DIS BIT(26)
+#define ISP32_MPDS_WR_FRMEND_UPD_DIS BIT(27)
+#define ISP32_BPDS_WR_FRMEND_UPD_DIS BIT(28)
+
+/* VFLIP_CTRL */
+#define ISP32_MP_WR_V_FLIP BIT(0)
+#define ISP32_SP_WR_V_FLIP BIT(1)
+#define ISP32_BP_WR_V_FLIP BIT(2)
+#define ISP32_MPDS_WR_V_FLIP BIT(4)
+#define ISP32_BPDS_WR_V_FIIP BIT(5)
+
+/* MPFBC */
+#define ISP3X_MPFBC_YUV_MASK GENMASK(2, 1)
+#define ISP3X_MPFBC_EN BIT(0)
+#define ISP3X_MPFBC_YUV420 0
+#define ISP3X_MPFBC_YUV422 BIT(1)
+#define ISP3X_MPFBC_PINGPONG_EN BIT(4)
+#define ISP3X_MPFBC_UNCOMPRESSED BIT(5)
+#define ISP3X_MPFBC_SPARSE_MODE BIT(6)
+#define ISP3X_MPFBC_FROM_SCL BIT(7)
+#define ISP3X_SEPERATE_YUV_CFG BIT(8)
+#define ISP3X_MP_YUV_MODE BIT(9)
+#define ISP3X_SP_YUV_MODE BIT(10)
+#define ISP3X_BP_YUV_MODE BIT(11)
+#define ISP3X_HEAD_OFFSET_EN BIT(12)
+#define ISP3X_HEAD_OUT_OPT_DIS BIT(29)
+#define ISP3X_MPFBC_WORKING BIT(30)
+#define ISP3X_MPFBC_FORCE_UPD BIT(31)
+#define ISP3X_MPFBC_EN_SHD BIT(31)
+
+/* AXI_CONFIG_RD_CTRL */
+#define ISP32L_AXI_CONF_RD_ST BIT(0)
+#define ISP32L_AXI_CONF_RD_ST_MODE BIT(1)
+#define ISP32L_AXI_CONF_RD_CLEAR BIT(4)
+#define ISP32L_AXI_CONF_RD_DIS BIT(7)
+#define ISP32L_WR_FRM_BUF_EN BIT(8)
+#define ISP32L_RD_FRM_BUF_EN BIT(9)
+#define ISP32L_WR_FRM_BUF_EN_SHD BIT(10)
+#define ISP32L_RD_FRM_BUF_EN_SHD BIT(11)
+#define ISP32L_FRM_BUF_FORCE_UPD BIT(16)
+#define ISP32L_WR_FRM_BUF_ERROR BIT(28)
+#define ISP32L_FRM_BUF_RW_CONFLICT BIT(29)
+#define ISP32L_AXI_CONF_FAIL BIT(30)
+#define ISP32L_AXI_CONF_RD_DONE BIT(31)
+
+/* CSI2RX */
+#define ISP3X_RXSELF_FORCE_UPD BIT(31)
+#define ISP35_RXS_FORCE_UPD BIT(31)
+#define ISP35_RX0_FORCE_UPD BIT(30)
+#define ISP3X_CSI_RAW_RD_UNCOMPACT BIT(3)
+#define ISP3X_CSI_RAW_RD_ALIGN BIT(4)
+
+/* DEBAYER */
+
+/* CAC */
+#define ISP3X_CAC_EN BIT(0)
+#define ISP3X_CAC_BYPASS BIT(1)
+#define ISP3X_CAC_CLEAR BIT(2)
+#define ISP3X_CAC_CENTER_EN BIT(3)
+#define ISP3X_CAC_LUT_EN BIT(4)
+#define ISP3X_CAC_LUT_MODE(x) (((x) & 0x3) << 24)
+
+/* CNR */
+#define ISP3X_CNR_THUMB_MIX_CUR_EN BIT(4)
+
+#define ISP3X_CNR_GLOBAL_GAIN_ALPHA_MAX GENMASK(15, 12)
+
+/* YNR */
+#define ISP3X_YNR_THUMB_MIX_CUR_EN BIT(24)
+#define ISP3X_YNR_EN_SHD BIT(31)
+
+/* BLS */
+#define ISP32_BLS_BLS2_EN BIT(5)
+#define ISP35_BLS_BLS3_EN BIT(6)
+
+/* BAY3D */
+#define ISP32_BAY3D_BWSAVING(a) (((a) & 0x1) << 13)
+
+#define ISP35_BAY3D_1ST_IIR_RD BIT(16)
+
+/* GIC */
+
+/* LDCH */
+#define ISP3X_LDCH_EN BIT(0)
+#define ISP3X_LDCH_LUT_MODE(x) (((x) & 0x3) << 24)
+#define ISP3X_LDCH_MAP_ERR BIT(29)
+#define ISP3X_LDCH_FORCE_UPD BIT(31)
+
+#define ISP35_B3DLDC_EN BIT(0)
+#define ISP35_B3DLDC_MAP_ERR BIT(12)
+#define ISP35_B3DLDC_LUT_MODE(x) (((x) & 0x3) << 24)
+#define ISP35_B3DLDC_FORCE_UPD BIT(26)
+
+#define ISP35_B3DLDHC_LUT_FRM_END BIT(8)
+#define ISP35_B3DLDCH_MAP_ERR BIT(29)
+
+/* DHAZ */
+#define ISP3X_DHAZ_ENMUX BIT(0)
+#define ISP3X_DHAZ_DC_EN BIT(4)
+#define ISP3X_DHAZ_HIST_EN BIT(8)
+#define ISP3X_DHAZ_HPARA_EN BIT(12)
+#define ISP3X_DHAZ_AIR_LC_EN BIT(16)
+#define ISP3X_DHAZ_ENHANCE_EN BIT(20)
+#define ISP3X_DHAZ_CKG_DIS BIT(24)
+#define ISP3X_DHAZ_SOFT_WR_EN BIT(25)
+#define ISP3X_DHAZ_ROUND_EN BIT(26)
+
+#define ISP39_DHAZ_IIR_RD_ID(x) ((x) & 0xff)
+#define ISP39_DHAZ_IIR_RD_P BIT(8)
+#define ISP39_DHAZ_IIR_RDATA_VAL BIT(9)
+#define ISP39_DHAZ_IIR_WR_ID(x) (((x) & 0xff) << 16)
+#define ISP39_DHAZ_IIR_WR_CLEAR BIT(24)
+
+#define ISP33_IIR_RD_ID(x) ((x) & 0x3f)
+#define ISP33_IIR_RD_P BIT(8)
+#define ISP33_IIR_RDATA_VAL BIT(9)
+#define ISP33_IIR_WR_ID(x) (((x) & 0x3f) << 16)
+#define ISP33_IIR_WR_CLEAR BIT(24)
+
+/* HDRTMO */
+
+/* HDRDRC */
+#define ISP3X_DRC_WEIPRE_FRAME_MASK GENMASK(23, 16)
+
+#define ISP3X_DRC_IIR_WEIGHT_MASK GENMASK(22, 16)
+
+#define ISP39_ADRC_CMPS_BYP_EN BIT(2)
+
+/* HDRMGE */
+
+/* RAWNR */
+
+/* EXPD */
+#define ISP32_EXPD_EN BIT(0)
+#define ISP32_EXPD_K_SHIFT(a) (((a) & 0xf) << 4)
+#define ISP32_EXPD_MODE(a) (((a) & 0x3) << 8)
+#define ISP39_EXPD_INPUT_16 BIT(8)
+
+#define ISP32_EXPD_DATA(a, b) ((a) | (b) << 16)
+
+/* GAIN */
+#define ISP3X_GAIN_2DDR_EN BIT(24)
+#define ISP3X_GAIN_2DDR_MODE(a) (((a) & 0x3) << 25)
+
+/* DPCC */
+#define ISP3X_DPCC_WORKING BIT(30)
+
+/* CCM */
+#define ISP3X_CCM_HIGHY_ADJ_DIS BIT(1)
+#define ISP32_CCM_ENH_ADJ_EN BIT(2)
+#define ISP32_CCM_ASYM_ADJ_EN BIT(3)
+#define ISP39_CCM_SAT_DECAY_EN BIT(4)
+
+/* 3DLUT */
+#define ISP3X_3DLUT_EN BIT(0)
+#define ISP3X_3DLUT_LUT_MODE(x) (((x) & 0x3) << 24)
+#define ISP3X_3DLUT_LUT_ERR BIT(29)
+
+#define ISP35_HSV_FIX_RW_CONFLICT BIT(8)
+#define ISP35_HSV_AHB_CFG_LUT_EN BIT(9)
+#define ISP35_HSV_TBL_CLR BIT(30)
+
+/* AWBSYNC */
+#define ISP35_AWBSYNC_FRM_PROT BIT(1)
+
+/* DEBAYER */
+
+/* LSC */
+#define ISP3X_LSC_ACTIVE_TABLE BIT(1)
+#define ISP3X_LSC_TABLE_ADDRESS_0 0
+#define ISP3X_LSC_TABLE_ADDRESS_153 153
+
+#define ISP3X_LSC_LUT_EN BIT(1)
+#define ISP3X_LSC_SECTOR_16X16 BIT(2)
+#define ISP3X_LSC_PRE_RD_ST_MODE BIT(4)
+
+/* CNR */
+#define ISP35_CNR_UV_DIS BIT(6)
+
+/* COMMON3A */
+#define ISP39_W3A_EN BIT(0)
+#define ISP39_W3A_PDAF_EN BIT(1)
+#define ISP39_W3A_3A_HOLD_DIS BIT(2)
+#define ISP39_W3A_PDAF2DDR_HOLD_DIS BIT(3)
+#define ISP39_W3A_AUTO_CLR_EN BIT(4)
+#define ISP39_W3A_CLK_GATING_DIS BIT(5)
+#define ISP35_W3A_B3DNROUT_ILG_BYPASS BIT(8)
+#define ISP35_W3A_RAWLSC_SEL BIT(9)
+#define ISP35_W3A_FORCE_UPD_F BIT(30)
+#define ISP39_W3A_FORCE_UPD BIT(31)
+
+#define ISP39_W3A_INT_AEBIG BIT(0)
+#define ISP39_W3A_INT_AE0 BIT(1)
+#define ISP39_W3A_INT_AF BIT(4)
+#define ISP39_W3A_INI_AWB BIT(5)
+#define ISP39_W3A_INT_PDAF BIT(6)
+#define ISP39_W3A_INT_ERR BIT(16)
+
+#define ISP39_W3A_INT_ERR_MASK GENMASK(31, 16)
+#define ISP39_W3A_INT_AEBIG_OVF BIT(16)
+#define ISP39_W3A_INT_AE0_OVF BIT(17)
+#define ISP39_W3A_INT_AF_HIIR_OVF BIT(20)
+#define ISP39_W3A_INT_AF_VIIR_OVF BIT(21)
+#define ISP39_W3A_INT_AF_AEHGL_OVF BIT(22)
+#define ISP39_W3A_INT_AWB_OVF BIT(23)
+#define ISP39_W3A_INT_PDAF_OVF BIT(24)
+#define ISP39_W3A_INT_WCFIFO_WR_ERR BIT(30)
+#define ISP39_W3A_INT_WCFIFO_RD_ERR BIT(31)
+
+/* RAWAE */
+#define ISP3X_RAWAE_LITE_EN BIT(0)
+#define ISP3X_RAWAE_LITE_WNDNUM BIT(1)
+
+#define ISP3X_RAWAE_BIG_EN BIT(0)
+#define ISP3X_RAWAE_BIG_WND0_NUM(x) (((x) & 0x3) << 1)
+#define ISP3X_RAWAE_BIG_WND1_EN BIT(4)
+#define ISP3X_RAWAE_BIG_WND2_EN BIT(5)
+#define ISP3X_RAWAE_BIG_WND3_EN BIT(6)
+#define ISP3X_RAWAE_BIG_WND4_EN BIT(7)
+
+/* RAWHIST */
+#define ISP3X_RAWHIST_EN BIT(0)
+#define ISP3X_RAWHIST_STEPSIZE(x) (((x) & 0x7) << 1)
+#define ISP3X_RAWHIST_MODE(x) (((x) & 0x7) << 8)
+#define ISP3X_RAWHIST_WATERLINE(x) (((x) & 0xfff) << 12)
+#define ISP3X_RAWHIST_DATASEL(x) (((x) & 0x7) << 24)
+#define ISP3X_RAWHIST_WND_NUM(x) (((x) & 0x3) << 28)
+
+#define ISP3X_RAWHIST_RAM_EN BIT(31)
+
+/* RAWAF */
+#define ISP3X_RAWAF_EN BIT(0)
+#define ISP3X_RAWAF_GAMMA_EN BIT(1)
+#define ISP3X_RAWAF_GAUS_EN BIT(2)
+#define ISP3X_RAWAF_V1_FIR BIT(3)
+#define ISP3X_RAWAF_HIIR_EN BIT(4)
+#define ISP3X_RAWAF_VIIR_EN BIT(5)
+#define ISP3X_RAWAF_ACCU_8BIT BIT(6)
+#define ISP3X_RAWAF_LDG_EN BIT(7)
+#define ISP3X_RAWAF_H1_FV BIT(8)
+#define ISP3X_RAWAF_H2_FV BIT(9)
+#define ISP3X_RAWAF_V1_FV BIT(10)
+#define ISP3X_RAWAF_V2_FV BIT(11)
+#define ISP3X_RAWAF_AE_MODE BIT(12)
+#define ISP3X_RAWAF_Y_MODE BIT(13)
+
+#define ISP3X_RAWAF_INELINE0(x) ((x) & 0xf)
+#define ISP3X_RAWAF_INTLINE0_EN BIT(27)
+
+/* RAWAWB */
+#define ISP32_RAWAWB_2DDR_PATH_EN BIT(23)
+#define ISP32_RAWAWB_2DDR_PATH_DS BIT(27)
+#define ISP32_RAWAWB_2DDR_PATH_ERR BIT(29)
+
+#define ISP35_RAWAWB_BNR_BE_SEL BIT(10)
+
+#define ISP33_RAWAWB_WRAM_CLR BIT(31)
+
+/* AIAWB */
+#define ISP35_AIAWB_EN BIT(0)
+#define ISP35_AIAWB_FRMEND_UPD_DIS BIT(28)
+#define ISP35_AIAWB_SYS_UPD_DIS BIT(29)
+#define ISP35_AIAWB_SELF_UPD BIT(30)
+
+#endif /* _RKISP2_REGS_V3X_H */
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs.h
new file mode 100644
index 000000000000..6848f5539734
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs.h
@@ -0,0 +1,1736 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Rockchip isp2 driver
+ *
+ * Copyright (C) 2026 Rockchip Electronics Co., Ltd.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * - Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _RKISP2_REGS_H
+#define _RKISP2_REGS_H
+
+#include "rkisp2-regs-v2x.h"
+#include "rkisp2-regs-v3x.h"
+
+#define RKISP2_CIF_ISP_PACK_4BYTE(a, b, c, d) \
+ (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
+ ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
+
+#define RKISP2_CIF_ISP_PACK_2SHORT(a, b) \
+ (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
+
+/* GRF */
+#define RKISP2_GRF_VI_CON0 0x430
+#define RKISP2_ISP_CIF_DATA_WIDTH_MASK 0x60006000
+#define RKISP2_ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
+#define RKISP2_ISP_CIF_DATA_WIDTH_10B (BIT(13) | 3 << 29)
+#define RKISP2_ISP_CIF_DATA_WIDTH_12B (2 << 13 | 3 << 29)
+
+/* ISP_CTRL */
+#define RKISP2_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_ITU656 (1 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_ITU601 (2 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601 (3 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_DATA_MODE (4 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656 (5 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656 (6 << 1)
+#define RKISP2_CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
+#define RKISP2_CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
+#define RKISP2_CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
+#define RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
+#define RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
+#define RKISP2_CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
+#define RKISP2_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
+#define RKISP2_CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(12)
+#define RKISP2_CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA BIT(13)
+#define RKISP2_CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA BIT(14)
+
+/* ISP_ACQ_PROP */
+#define RKISP2_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
+#define RKISP2_CIF_ISP_ACQ_PROP_HSYNC_LOW BIT(1)
+#define RKISP2_CIF_ISP_ACQ_PROP_VSYNC_LOW BIT(2)
+#define RKISP2_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
+#define RKISP2_CIF_ISP_ACQ_PROP_BAYER_PAT_GRBG (1 << 3)
+#define RKISP2_CIF_ISP_ACQ_PROP_BAYER_PAT_GBRG (2 << 3)
+#define RKISP2_CIF_ISP_ACQ_PROP_BAYER_PAT_BGGR (3 << 3)
+#define RKISP2_CIF_ISP_ACQ_PROP_BAYER_PAT(pat) ((pat) << 3)
+#define RKISP2_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
+#define RKISP2_CIF_ISP_ACQ_PROP_YCRYCB (1 << 7)
+#define RKISP2_CIF_ISP_ACQ_PROP_CBYCRY (2 << 7)
+#define RKISP2_CIF_ISP_ACQ_PROP_CRYCBY (3 << 7)
+#define RKISP2_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
+#define RKISP2_CIF_ISP_ACQ_PROP_FIELD_SEL_EVEN (1 << 9)
+#define RKISP2_CIF_ISP_ACQ_PROP_FIELD_SEL_ODD (2 << 9)
+#define RKISP2_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
+#define RKISP2_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO (1 << 12)
+#define RKISP2_CIF_ISP_ACQ_PROP_IN_SEL_10B_MSB (2 << 12)
+#define RKISP2_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO (3 << 12)
+#define RKISP2_CIF_ISP_ACQ_PROP_IN_SEL_8B_MSB (4 << 12)
+#define RKISP2_CIF_ISP_ACQ_PROP_DMA_RGB BIT(15)
+#define RKISP2_CIF_ISP_ACQ_PROP_DMA_YUV BIT(16)
+
+/* VI_DPCL */
+#define RKISP2_CIF_VI_DPCL_DMA_JPEG (0 << 0)
+#define RKISP2_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
+#define RKISP2_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
+#define RKISP2_CIF_VI_DPCL_CHAN_MODE_MP (1 << 2)
+#define RKISP2_CIF_VI_DPCL_CHAN_MODE_SP (2 << 2)
+#define RKISP2_CIF_VI_DPCL_CHAN_MODE_MPSP (3 << 2)
+#define RKISP2_CIF_VI_DPCL_DMA_SW_SPMUX (0 << 4)
+#define RKISP2_CIF_VI_DPCL_DMA_SW_SI (1 << 4)
+#define RKISP2_CIF_VI_DPCL_DMA_SW_IE (2 << 4)
+#define RKISP2_CIF_VI_DPCL_DMA_SW_JPEG (3 << 4)
+#define RKISP2_CIF_VI_DPCL_DMA_SW_ISP (4 << 4)
+#define RKISP2_CIF_VI_DPCL_IF_SEL_PARALLEL (0 << 8)
+#define RKISP2_CIF_VI_DPCL_IF_SEL_SMIA (1 << 8)
+#define RKISP2_CIF_VI_DPCL_IF_SEL_MIPI (2 << 8)
+#define RKISP2_CIF_VI_DPCL_DMA_IE_MUX_DMA BIT(10)
+#define RKISP2_CIF_VI_DPCL_DMA_SP_MUX_DMA BIT(11)
+
+/* ISP_IMSC - ISP_MIS - ISP_RIS - ISP_ICR - ISP_ISR */
+#define RKISP2_CIF_ISP_OFF BIT(0)
+#define RKISP2_CIF_ISP_FRAME BIT(1)
+#define RKISP2_CIF_ISP_DATA_LOSS BIT(2)
+#define RKISP2_CIF_ISP_PIC_SIZE_ERROR BIT(3)
+#define RKISP2_CIF_ISP_AWB_DONE BIT(4)
+#define RKISP2_CIF_ISP_FRAME_IN BIT(5)
+#define RKISP2_CIF_ISP_V_START BIT(6)
+#define RKISP2_CIF_ISP_H_START BIT(7)
+#define RKISP2_CIF_ISP_FLASH_ON BIT(8)
+#define RKISP2_CIF_ISP_FLASH_OFF BIT(9)
+#define RKISP2_CIF_ISP_SHUTTER_ON BIT(10)
+#define RKISP2_CIF_ISP_SHUTTER_OFF BIT(11)
+#define RKISP2_CIF_ISP_AFM_SUM_OF BIT(12)
+#define RKISP2_CIF_ISP_AFM_LUM_OF BIT(13)
+#define RKISP2_CIF_ISP_AFM_FIN BIT(14)
+#define RKISP2_CIF_ISP_HIST_MEASURE_RDY BIT(15)
+#define RKISP2_CIF_ISP_FLASH_CAP BIT(17)
+#define RKISP2_CIF_ISP_EXP_END BIT(18)
+#define RKISP2_CIF_ISP_VSM_END BIT(19)
+
+/* ISP_ERR */
+#define RKISP2_CIF_ISP_ERR_INFORM_SIZE BIT(0)
+#define RKISP2_CIF_ISP_ERR_IS_SIZE BIT(1)
+#define RKISP2_CIF_ISP_ERR_OUTFORM_SIZE BIT(2)
+
+/* MI_CTRL */
+#define RKISP2_CIF_MI_CTRL_MP_ENABLE (1 << 0)
+#define RKISP2_CIF_MI_CTRL_SP_ENABLE (2 << 0)
+#define RKISP2_CIF_MI_CTRL_JPEG_ENABLE (4 << 0)
+#define RKISP2_CIF_MI_CTRL_RAW_ENABLE (8 << 0)
+#define RKISP2_CIF_MI_CTRL_HFLIP BIT(4)
+#define RKISP2_CIF_MI_CTRL_VFLIP BIT(5)
+#define RKISP2_CIF_MI_CTRL_ROT BIT(6)
+#define RKISP2_CIF_MI_BYTE_SWAP BIT(7)
+#define RKISP2_CIF_MI_SP_Y_FULL_YUV2RGB BIT(8)
+#define RKISP2_CIF_MI_SP_CBCR_FULL_YUV2RGB BIT(9)
+#define RKISP2_CIF_MI_SP_422NONCOSITEED BIT(10)
+#define RKISP2_CIF_MI_MP_PINGPONG_ENABLE BIT(11)
+#define RKISP2_CIF_MI_SP_PINGPONG_ENABLE BIT(12)
+#define RKISP2_CIF_MI_MP_AUTOUPDATE_ENABLE BIT(13)
+#define RKISP2_CIF_MI_SP_AUTOUPDATE_ENABLE BIT(14)
+#define RKISP2_CIF_MI_LAST_PIXEL_SIG_ENABLE BIT(15)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_LUM_4 (0 << 16)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_LUM_8 (1 << 16)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_LUM_16 (2 << 16)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_LUM_64 (2 << 16)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_CHROM_4 (0 << 18)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_CHROM_8 (1 << 18)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_CHROM_16 (2 << 18)
+#define RKISP2_CIF_MI_CTRL_BURST_LEN_CHROM_64 (2 << 18)
+#define RKISP2_CIF_MI_CTRL_INIT_BASE_EN BIT(20)
+#define RKISP2_CIF_MI_CTRL_INIT_OFFSET_EN BIT(21)
+#define RKISP2_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8 (0 << 22)
+#define RKISP2_MI_CTRL_MP_WRITE_YUV_SPLA (1 << 22)
+#define RKISP2_MI_CTRL_MP_WRITE_YUVINT (2 << 22)
+#define RKISP2_MI_CTRL_MP_WRITE_RAW12 (2 << 22)
+#define RKISP2_MI_CTRL_SP_WRITE_PLA (0 << 24)
+#define RKISP2_MI_CTRL_SP_WRITE_SPLA (1 << 24)
+#define RKISP2_MI_CTRL_SP_WRITE_INT (2 << 24)
+#define RKISP2_MI_CTRL_SP_INPUT_YUV400 (0 << 26)
+#define RKISP2_MI_CTRL_SP_INPUT_YUV420 (1 << 26)
+#define RKISP2_MI_CTRL_SP_INPUT_YUV422 (2 << 26)
+#define RKISP2_MI_CTRL_SP_INPUT_YUV444 (3 << 26)
+#define RKISP2_MI_CTRL_SP_OUTPUT_YUV400 (0 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_YUV420 (1 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_YUV422 (2 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_YUV444 (3 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_RGB565 (4 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_RGB666 (5 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_ARGB888 (6 << 28)
+#define RKISP2_MI_CTRL_SP_OUTPUT_RGB888 (7 << 28)
+
+#define RKISP2_MI_CTRL_MP_FMT_MASK GENMASK(23, 22)
+#define RKISP2_MI_CTRL_SP_FMT_MASK GENMASK(30, 24)
+
+/* MI_INIT */
+#define RKISP2_CIF_MI_INIT_SKIP BIT(2)
+#define RKISP2_CIF_MI_INIT_SOFT_UPD BIT(4)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_YUV444 (2 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_RAW565 (4 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_RAW666 (5 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_RAW888 (6 << 28)
+#define RKISP2_CIF_MI_INIT_MP_OUTPUT_MASK (7 << 28)
+
+/* MI_CTRL_SHD */
+#define RKISP2_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
+#define RKISP2_CIF_MI_CTRL_SHD_SP_IN_ENABLED BIT(1)
+#define RKISP2_CIF_MI_CTRL_SHD_JPEG_IN_ENABLED BIT(2)
+#define RKISP2_CIF_MI_CTRL_SHD_RAW_IN_ENABLED BIT(3)
+#define RKISP2_CIF_MI_CTRL_SHD_MP_OUT_ENABLED BIT(16)
+#define RKISP2_CIF_MI_CTRL_SHD_SP_OUT_ENABLED BIT(17)
+#define RKISP2_CIF_MI_CTRL_SHD_JPEG_OUT_ENABLED BIT(18)
+#define RKISP2_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED BIT(19)
+
+/* MI_CTRL2 */
+#define RKISP2_CIF_MI_CTRL2_MIPI_RAW0_PINGPONG_EN BIT(2)
+#define RKISP2_CIF_MI_CTRL2_MIPI_RAW0_AUTO_UPDATE BIT(1)
+#define RKISP2_CIF_MI_CTRL2_MIPI_RAW0_ENABLE BIT(0)
+
+/* RSZ_CTRL */
+#define RKISP2_CIF_RSZ_CTRL 0x0000
+#define RKISP2_CIF_RSZ_SCALE_HY 0x0004
+#define RKISP2_CIF_RSZ_SCALE_HCB 0x0008
+#define RKISP2_CIF_RSZ_SCALE_HCR 0x000C
+#define RKISP2_CIF_RSZ_SCALE_VY 0x0010
+#define RKISP2_CIF_RSZ_SCALE_VC 0x0014
+#define RKISP2_CIF_RSZ_PHASE_HY 0x0018
+#define RKISP2_CIF_RSZ_PHASE_HC 0x001C
+#define RKISP2_CIF_RSZ_PHASE_VY 0x0020
+#define RKISP2_CIF_RSZ_PHASE_VC 0x0024
+#define RKISP2_CIF_RSZ_SCALE_LUT_ADDR 0x0028
+#define RKISP2_CIF_RSZ_SCALE_LUT 0x002C
+#define RKISP2_CIF_RSZ_CTRL_SCALE_HY_ENABLE BIT(0)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_HC_ENABLE BIT(1)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_VY_ENABLE BIT(2)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_VC_ENABLE BIT(3)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_HY_UP BIT(4)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_HC_UP BIT(5)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_VY_UP BIT(6)
+#define RKISP2_CIF_RSZ_CTRL_SCALE_VC_UP BIT(7)
+#define RKISP2_CIF_RSZ_CTRL_CFG_UPD BIT(8)
+#define RKISP2_CIF_RSZ_CTRL_CFG_UPD_AUTO BIT(9)
+#define RKISP2_CIF_RSZ_SCALER_FACTOR BIT(16)
+
+/* MI_IMSC - MI_MIS - MI_RIS - MI_ICR - MI_ISR */
+#define RKISP2_CIF_MI_FRAME(stream) BIT((stream)->id)
+#define RKISP2_CIF_MI_MP_FE BIT(0)
+#define RKISP2_CIF_MI_SP_FE BIT(1)
+#define RKISP2_CIF_MI_MBLK_LINE BIT(2)
+#define RKISP2_CIF_MI_FILL_MP_Y BIT(3)
+#define RKISP2_CIF_MI_WRAP_MP_Y BIT(4)
+#define RKISP2_CIF_MI_WRAP_MP_CB BIT(5)
+#define RKISP2_CIF_MI_WRAP_MP_CR BIT(6)
+#define RKISP2_CIF_MI_WRAP_SP_Y BIT(7)
+#define RKISP2_CIF_MI_WRAP_SP_CB BIT(8)
+#define RKISP2_CIF_MI_WRAP_SP_CR BIT(9)
+#define RKISP2_CIF_MI_DMA_READY BIT(11)
+
+/* MI_STATUS */
+#define RKISP2_CIF_MI_STATUS_MP_Y_FIFO_FULL BIT(0)
+#define RKISP2_CIF_MI_STATUS_SP_Y_FIFO_FULL BIT(4)
+
+/* MI_DMA_CTRL */
+#define RKISP2_CIF_MI_DMA_CTRL_BURST_LEN_LUM_4 (0 << 0)
+#define RKISP2_CIF_MI_DMA_CTRL_BURST_LEN_LUM_8 BIT(0)
+#define RKISP2_CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 BIT(1)
+#define RKISP2_CIF_MI_DMA_CTRL_BURST_LEN_CHROM_4 (0 << 2)
+#define RKISP2_CIF_MI_DMA_CTRL_BURST_LEN_CHROM_8 BIT(2)
+#define RKISP2_CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16 BIT(3)
+#define RKISP2_CIF_MI_DMA_CTRL_READ_FMT_PLANAR (0 << 4)
+#define RKISP2_CIF_MI_DMA_CTRL_READ_FMT_SPLANAR (1 << 4)
+#define RKISP2_CIF_MI_DMA_CTRL_READ_FMT_PACKED (2 << 4)
+#define RKISP2_CIF_MI_DMA_CTRL_FMT_YUV400 (0 << 6)
+#define RKISP2_CIF_MI_DMA_CTRL_FMT_YUV420 (1 << 6)
+#define RKISP2_CIF_MI_DMA_CTRL_FMT_YUV422 (2 << 6)
+#define RKISP2_CIF_MI_DMA_CTRL_FMT_YUV444 (3 << 6)
+#define RKISP2_CIF_MI_DMA_CTRL_BYTE_SWAP BIT(8)
+#define RKISP2_CIF_MI_DMA_CTRL_CONTINUOUS_ENA BIT(9)
+#define RKISP2_CIF_MI_DMA_CTRL_RGB_BAYER_NO (0 << 12)
+#define RKISP2_CIF_MI_DMA_CTRL_RGB_BAYER_8BIT (1 << 12)
+#define RKISP2_CIF_MI_DMA_CTRL_RGB_BAYER_16BIT (2 << 12)
+/* MI_DMA_START */
+#define RKISP2_CIF_MI_DMA_START_ENABLE BIT(0)
+/* MI_XTD_FORMAT_CTRL */
+#define RKISP2_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP BIT(0)
+#define RKISP2_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
+#define RKISP2_CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
+
+/* CCL */
+#define RKISP2_CIF_CCL_CIF_CLK_DIS BIT(2)
+/* VI_ISP_CLK_CTRL */
+#define RKISP2_CIF_CLK_CTRL_ISP_RAW BIT(0)
+#define RKISP2_CIF_CLK_CTRL_ISP_RGB BIT(1)
+#define RKISP2_CIF_CLK_CTRL_ISP_YUV BIT(2)
+#define RKISP2_CIF_CLK_CTRL_ISP_3A BIT(3)
+#define RKISP2_CIF_CLK_CTRL_MIPI_RAW BIT(4)
+#define RKISP2_CIF_CLK_CTRL_ISP_IE BIT(5)
+#define RKISP2_CIF_CLK_CTRL_RSZ_RAM BIT(6)
+#define RKISP2_CIF_CLK_CTRL_JPEG_RAM BIT(7)
+#define RKISP2_CIF_CLK_CTRL_ACLK_ISP BIT(8)
+#define RKISP2_CIF_CLK_CTRL_MI_IDC BIT(9)
+#define RKISP2_CIF_CLK_CTRL_MI_MP BIT(10)
+#define RKISP2_CIF_CLK_CTRL_MI_JPEG BIT(11)
+#define RKISP2_CIF_CLK_CTRL_MI_DP BIT(12)
+#define RKISP2_CIF_CLK_CTRL_MI_Y12 BIT(13)
+#define RKISP2_CIF_CLK_CTRL_MI_SP BIT(14)
+#define RKISP2_CIF_CLK_CTRL_MI_RAW0 BIT(15)
+#define RKISP2_CIF_CLK_CTRL_MI_RAW1 BIT(16)
+#define RKISP2_CIF_CLK_CTRL_MI_READ BIT(17)
+#define RKISP2_CIF_CLK_CTRL_MI_RAWRD BIT(18)
+#define RKISP2_CIF_CLK_CTRL_CP BIT(19)
+#define RKISP2_CIF_CLK_CTRL_IE BIT(20)
+#define RKISP2_CIF_CLK_CTRL_SI BIT(21)
+#define RKISP2_CIF_CLK_CTRL_RSZM BIT(22)
+#define RKISP2_CIF_CLK_CTRL_DPMUX BIT(23)
+#define RKISP2_CIF_CLK_CTRL_JPEG BIT(24)
+#define RKISP2_CIF_CLK_CTRL_RSZS BIT(25)
+#define RKISP2_CIF_CLK_CTRL_MIPI BIT(26)
+#define RKISP2_CIF_CLK_CTRL_MARVINMI BIT(27)
+/* ICCL */
+#define RKISP2_CIF_ICCL_ISP_CLK BIT(0)
+#define RKISP2_CIF_ICCL_CP_CLK BIT(1)
+#define RKISP2_CIF_ICCL_RES_2 BIT(2)
+#define RKISP2_CIF_ICCL_MRSZ_CLK BIT(3)
+#define RKISP2_CIF_ICCL_SRSZ_CLK BIT(4)
+#define RKISP2_CIF_ICCL_JPEG_CLK BIT(5)
+#define RKISP2_CIF_ICCL_MI_CLK BIT(6)
+#define RKISP2_CIF_ICCL_RES_7 BIT(7)
+#define RKISP2_CIF_ICCL_IE_CLK BIT(8)
+#define RKISP2_CIF_ICCL_SIMP_CLK BIT(9)
+#define RKISP2_CIF_ICCL_SMIA_CLK BIT(10)
+#define RKISP2_CIF_ICCL_MIPI_CLK BIT(11)
+#define RKISP2_CIF_ICCL_DCROP_CLK BIT(12)
+#define RKISP2_CIF_VI_ICCL (RKISP2_CIF_CTRL_BASE + 0x00000010)
+#define RKISP2_CIF_VI_ICCL_ISP_CLK BIT(0)
+#define RKISP2_CIF_VI_ICCL_CP_CLK BIT(1)
+#define RKISP2_CIF_VI_ICCL_MRSZ_CLK BIT(3)
+#define RKISP2_CIF_VI_ICCL_SRSZ_CLK BIT(4)
+#define RKISP2_CIF_VI_ICCL_JPEG_CLK BIT(5)
+#define RKISP2_CIF_VI_ICCL_MI_CLK BIT(6)
+#define RKISP2_CIF_VI_ICCL_IE_CLK BIT(8)
+#define RKISP2_CIF_VI_ICCL_MIPI_CLK BIT(11)
+#define RKISP2_CIF_VI_ICCL_DCROP_CLK BIT(12)
+/* IRCL */
+#define RKISP2_CIF_IRCL_ISP_SW_RST BIT(0)
+#define RKISP2_CIF_IRCL_CP_SW_RST BIT(1)
+#define RKISP2_CIF_IRCL_YCS_SW_RST BIT(2)
+#define RKISP2_CIF_IRCL_MRSZ_SW_RST BIT(3)
+#define RKISP2_CIF_IRCL_SRSZ_SW_RST BIT(4)
+#define RKISP2_CIF_IRCL_JPEG_SW_RST BIT(5)
+#define RKISP2_CIF_IRCL_MI_SW_RST BIT(6)
+#define RKISP2_CIF_IRCL_CIF_SW_RST BIT(7)
+#define RKISP2_CIF_IRCL_IE_SW_RST BIT(8)
+#define RKISP2_CIF_IRCL_SI_SW_RST BIT(9)
+#define RKISP2_CIF_IRCL_MIPI_SW_RST BIT(11)
+#define RKISP2_CIF_VI_IRCL (RKISP2_CIF_CTRL_BASE + 0x00000014)
+#define RKISP2_CIF_VI_IRCL_ISP_SW_RST BIT(0)
+#define RKISP2_CIF_VI_IRCL_MIPI_SW_RST BIT(11)
+/* SWS */
+#define RKISP2_CIF_SWS_MIPI_DROP_FRM_DIS BIT(2)
+#define RKISP2_CIF_SWS_ACK_FRM_PRO_DIS BIT(3)
+
+
+/* C_PROC_CTR */
+#define RKISP2_CIF_C_PROC_CTR_ENABLE BIT(0)
+#define RKISP2_CIF_C_PROC_YOUT_FULL BIT(1)
+#define RKISP2_CIF_C_PROC_YIN_FULL BIT(2)
+#define RKISP2_CIF_C_PROC_COUT_FULL BIT(3)
+#define RKISP2_CIF_C_PROC_CTRL_RESERVED 0xFFFFFFFE
+#define RKISP2_CIF_C_PROC_CONTRAST_RESERVED 0xFFFFFF00
+#define RKISP2_CIF_C_PROC_BRIGHTNESS_RESERVED 0xFFFFFF00
+#define RKISP2_CIF_C_PROC_HUE_RESERVED 0xFFFFFF00
+#define RKISP2_CIF_C_PROC_SATURATION_RESERVED 0xFFFFFF00
+#define RKISP2_CIF_C_PROC_MACC_RESERVED 0xE000E000
+#define RKISP2_CIF_C_PROC_TONE_RESERVED 0xF000
+/* DUAL_CROP_CTRL */
+#define RKISP2_CIF_DUAL_CROP_MP_MODE_BYPASS (0 << 0)
+#define RKISP2_CIF_DUAL_CROP_MP_MODE_YUV (1 << 0)
+#define RKISP2_CIF_DUAL_CROP_MP_MODE_RAW (2 << 0)
+#define RKISP2_CIF_DUAL_CROP_SP_MODE_BYPASS (0 << 2)
+#define RKISP2_CIF_DUAL_CROP_SP_MODE_YUV (1 << 2)
+#define RKISP2_CIF_DUAL_CROP_SP_MODE_RAW (2 << 2)
+#define RKISP2_CIF_DUAL_CROP_CFG_UPD_PERMANENT BIT(4)
+#define RKISP2_CIF_DUAL_CROP_CFG_UPD BIT(5)
+#define RKISP2_CIF_DUAL_CROP_GEN_CFG_UPD BIT(6)
+
+/* IMG_EFF_CTRL */
+#define RKISP2_CIF_IMG_EFF_CTRL_ENABLE BIT(0)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_BLACKWHITE (0 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_NEGATIVE (1 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_SEPIA (2 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_COLOR_SEL (3 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_EMBOSS (4 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_SKETCH (5 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_SHARPEN (6 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_RKSHARPEN (7 << 1)
+#define RKISP2_CIF_IMG_EFF_CTRL_CFG_UPD BIT(4)
+#define RKISP2_CIF_IMG_EFF_CTRL_YCBCR_FULL BIT(5)
+
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_BLACKWHITE_SHIFT 0
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_NEGATIVE_SHIFT 1
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT 2
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_COLOR_SEL_SHIFT 3
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT 4
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_SKETCH_SHIFT 5
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_SHARPEN_SHIFT 6
+#define RKISP2_CIF_IMG_EFF_CTRL_MODE_MASK 0xE
+
+/* IMG_EFF_COLOR_SEL */
+#define RKISP2_CIF_IMG_EFF_COLOR_RGB 0
+#define RKISP2_CIF_IMG_EFF_COLOR_B (1 << 0)
+#define RKISP2_CIF_IMG_EFF_COLOR_G (2 << 0)
+#define RKISP2_CIF_IMG_EFF_COLOR_GB (3 << 0)
+#define RKISP2_CIF_IMG_EFF_COLOR_R (4 << 0)
+#define RKISP2_CIF_IMG_EFF_COLOR_RB (5 << 0)
+#define RKISP2_CIF_IMG_EFF_COLOR_RG (6 << 0)
+#define RKISP2_CIF_IMG_EFF_COLOR_RGB2 (7 << 0)
+
+/* MIPI_CTRL */
+#define RKISP2_CIF_MIPI_CTRL_OUTPUT_ENA BIT(0)
+#define RKISP2_CIF_MIPI_CTRL_FLUSH_FIFO BIT(1)
+#define RKISP2_CIF_MIPI_CTRL_SHUTDOWNLANES(a) (((a) & 0xF) << 8)
+#define RKISP2_CIF_MIPI_CTRL_NUM_LANES(a) (((a) & 0x3) << 12)
+#define RKISP2_CIF_MIPI_CTRL_ERR_SOT_HS_SKIP BIT(16)
+#define RKISP2_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP BIT(17)
+#define RKISP2_CIF_MIPI_CTRL_CLOCKLANE_ENA BIT(18)
+
+/* MIPI_DATA_SEL */
+#define RKISP2_CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6)
+#define RKISP2_CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0)
+/* MIPI DATA_TYPE */
+#define RKISP2_CIF_CSI2_DT_EBD 0x12
+#define RKISP2_CIF_CSI2_DT_YUV420_8b 0x18
+#define RKISP2_CIF_CSI2_DT_YUV420_10b 0x19
+#define RKISP2_CIF_CSI2_DT_YUV422_8b 0x1E
+#define RKISP2_CIF_CSI2_DT_YUV422_10b 0x1F
+#define RKISP2_CIF_CSI2_DT_RGB565 0x22
+#define RKISP2_CIF_CSI2_DT_RGB666 0x23
+#define RKISP2_CIF_CSI2_DT_RGB888 0x24
+#define RKISP2_CIF_CSI2_DT_RAW8 0x2A
+#define RKISP2_CIF_CSI2_DT_RAW10 0x2B
+#define RKISP2_CIF_CSI2_DT_RAW12 0x2C
+#define RKISP2_CIF_CSI2_DT_RAW16 0x2e
+#define RKISP2_CIF_CSI2_DT_SPD 0x2F
+
+/* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */
+#define RKISP2_CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)
+#define RKISP2_CIF_MIPI_ERR_SOT(a) (((a) & 0xF) << 4)
+#define RKISP2_CIF_MIPI_ERR_SOT_SYNC(a) (((a) & 0xF) << 8)
+#define RKISP2_CIF_MIPI_ERR_EOT_SYNC(a) (((a) & 0xF) << 12)
+#define RKISP2_CIF_MIPI_ERR_CTRL(a) (((a) & 0xF) << 16)
+#define RKISP2_CIF_MIPI_ERR_PROTOCOL BIT(20)
+#define RKISP2_CIF_MIPI_ERR_ECC1 BIT(21)
+#define RKISP2_CIF_MIPI_ERR_ECC2 BIT(22)
+#define RKISP2_CIF_MIPI_ERR_CS BIT(23)
+#define RKISP2_CIF_MIPI_FRAME_END BIT(24)
+#define RKISP2_CIF_MIPI_ADD_DATA_OVFLW BIT(25)
+#define RKISP2_CIF_MIPI_ADD_DATA_WATER_MARK BIT(26)
+
+#define RKISP2_CIF_MIPI_ERR_CSI (RKISP2_CIF_MIPI_ERR_PROTOCOL | \
+ RKISP2_CIF_MIPI_ERR_ECC1 | \
+ RKISP2_CIF_MIPI_ERR_ECC2 | \
+ RKISP2_CIF_MIPI_ERR_CS)
+
+#define RKISP2_CIF_MIPI_ERR_DPHY (RKISP2_CIF_MIPI_ERR_SOT(0xF) | \
+ RKISP2_CIF_MIPI_ERR_SOT_SYNC(0xF) | \
+ RKISP2_CIF_MIPI_ERR_EOT_SYNC(0xF) | \
+ RKISP2_CIF_MIPI_ERR_CTRL(0xF))
+
+/* SUPER_IMPOSE */
+#define RKISP2_CIF_SUPER_IMP_CTRL_NORMAL_MODE BIT(0)
+#define RKISP2_CIF_SUPER_IMP_CTRL_REF_IMG_MEM BIT(1)
+#define RKISP2_CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2)
+
+/* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_DIS_V10 (0 << 0)
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_RGB_V10 (1 << 0)
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_RED_V10 (2 << 0)
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_GREEN_V10 (3 << 0)
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_BLUE_V10 (4 << 0)
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_LUM_V10 (5 << 0)
+#define RKISP2_CIF_ISP_HIST_PROP_MODE_MASK_V10 0x7
+#define RKISP2_CIF_ISP_HIST_PREDIV_SET_V10(x) (((x) & 0x7F) << 3)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3) \
+ (((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\
+ (((v2) & 0x1F) << 16) | \
+ (((v3) & 0x1F) << 24))
+#define RKISP2_CIF_ISP_HIST_GET_BIN_V10(x) ((x) & 0x000FFFFF)
+
+#define RKISP2_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10 0xFFFFF000
+#define RKISP2_CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10 0xFFFFF800
+#define RKISP2_CIF_ISP_HIST_WEIGHT_RESERVED_V10 0xE0E0E0E0
+#define RKISP2_CIF_ISP_MAX_HIST_PREDIVIDER_V10 0x0000007F
+#define RKISP2_CIF_ISP_HIST_ROW_NUM_V10 5
+#define RKISP2_CIF_ISP_HIST_COLUMN_NUM_V10 5
+
+/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
+#define RKISP2_CIF_ISP_HIST_CTRL_EN_SET_V12(x) (((x) & 0x01) << 0)
+#define RKISP2_CIF_ISP_HIST_CTRL_EN_MASK_V12 RKISP2_CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
+#define RKISP2_CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x) (((x) & 0x7F) << 1)
+#define RKISP2_CIF_ISP_HIST_CTRL_MODE_SET_V12(x) (((x) & 0x07) << 8)
+#define RKISP2_CIF_ISP_HIST_CTRL_MODE_MASK_V12 RKISP2_CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
+#define RKISP2_CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x) (((x) & 0x01) << 11)
+#define RKISP2_CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x) (((x) & 0xFFF) << 12)
+#define RKISP2_CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x) (((x) & 0x07) << 24)
+#define RKISP2_CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x) (((x) & 0x01) << 27)
+#define RKISP2_CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 28)
+#define RKISP2_CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x) (((x) & 0x01) << 30)
+#define RKISP2_CIF_ISP_HIST_ROW_NUM_V12 15
+#define RKISP2_CIF_ISP_HIST_COLUMN_NUM_V12 15
+#define RKISP2_CIF_ISP_HIST_WEIGHT_REG_SIZE_V12 \
+ (RKISP2_CIF_ISP_HIST_ROW_NUM_V12 * RKISP2_CIF_ISP_HIST_COLUMN_NUM_V12)
+
+#define RKISP2_CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3) \
+ (((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
+ (((v2) & 0x3F) << 16) |\
+ (((v3) & 0x3F) << 24))
+
+#define RKISP2_CIF_ISP_HIST_OFFS_SET_V12(v0, v1) \
+ (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
+#define RKISP2_CIF_ISP_HIST_SIZE_SET_V12(v0, v1) \
+ (((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
+
+#define RKISP2_CIF_ISP_HIST_GET_BIN0_V12(x) \
+ ((x) & 0xFFFF)
+#define RKISP2_CIF_ISP_HIST_GET_BIN1_V12(x) \
+ (((x) >> 16) & 0xFFFF)
+
+/* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
+#define RKISP2_ISP_AFM_CTRL_ENABLE BIT(0)
+
+/* SHUTTER CONTROL */
+#define RKISP2_CIF_ISP_SH_CTRL_SH_ENA BIT(0)
+#define RKISP2_CIF_ISP_SH_CTRL_REP_EN BIT(1)
+#define RKISP2_CIF_ISP_SH_CTRL_SRC_SH_TRIG BIT(2)
+#define RKISP2_CIF_ISP_SH_CTRL_EDGE_POS BIT(3)
+#define RKISP2_CIF_ISP_SH_CTRL_POL_LOW BIT(4)
+
+/* FLASH MODULE */
+/* ISP_FLASH_CMD */
+#define RKISP2_CIF_FLASH_CMD_PRELIGHT_ON BIT(0)
+#define RKISP2_CIF_FLASH_CMD_FLASH_ON BIT(1)
+#define RKISP2_CIF_FLASH_CMD_PRE_FLASH_ON BIT(2)
+/* ISP_FLASH_CONFIG */
+#define RKISP2_CIF_FLASH_CONFIG_PRELIGHT_END BIT(0)
+#define RKISP2_CIF_FLASH_CONFIG_VSYNC_POS BIT(1)
+#define RKISP2_CIF_FLASH_CONFIG_PRELIGHT_LOW BIT(2)
+#define RKISP2_CIF_FLASH_CONFIG_SRC_FL_TRIG BIT(3)
+#define RKISP2_CIF_FLASH_CONFIG_DELAY(a) (((a) & 0xF) << 4)
+
+/* Demosaic: ISP_DEMOSAIC */
+#define RKISP2_CIF_ISP_DEMOSAIC_BYPASS BIT(10)
+#define RKISP2_CIF_ISP_DEMOSAIC_TH(x) ((x) & 0xFF)
+
+/* AWB */
+/* ISP_AWB_PROP */
+#define RKISP2_CIF_ISP_AWB_YMAX_CMP_EN BIT(2)
+#define RKISP2_CIF_ISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
+#define RKISP2_CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0))
+#define RKISP2_CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
+#define RKISP2_CIF_ISP_AWB_MODE_RGB BIT(31)
+#define RKISP2_CIF_ISP_AWB_ENABLE (0x2 << 0)
+#define RKISP2_CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC
+#define RKISP2_CIF_ISP_AWB_MODE_READ(x) ((x) & 3)
+#define RKISP2_CIF_ISP_AWB_SET_FRAMES_V12(x) (((x) & 0x07) << 28)
+#define RKISP2_CIF_ISP_AWB_SET_FRAMES_MASK_V12 RKISP2_CIF_ISP_AWB_SET_FRAMES_V12(0x07)
+/* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */
+#define RKISP2_CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16)
+#define RKISP2_CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF)
+#define RKISP2_CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FF)
+#define RKISP2_CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FF)
+/* ISP_AWB_REF */
+#define RKISP2_CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8)
+#define RKISP2_CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF)
+#define RKISP2_CIF_ISP_AWB_REF_CB_READ(x) ((x) & 0xFF)
+/* ISP_AWB_THRESH */
+#define RKISP2_CIF_ISP_AWB_MAX_CS_SET(x) (((x) & 0xFF) << 8)
+#define RKISP2_CIF_ISP_AWB_MAX_CS_READ(x) (((x) >> 8) & 0xFF)
+#define RKISP2_CIF_ISP_AWB_MIN_C_READ(x) ((x) & 0xFF)
+#define RKISP2_CIF_ISP_AWB_MIN_Y_SET(x) (((x) & 0xFF) << 16)
+#define RKISP2_CIF_ISP_AWB_MIN_Y_READ(x) (((x) >> 16) & 0xFF)
+#define RKISP2_CIF_ISP_AWB_MAX_Y_SET(x) (((x) & 0xFF) << 24)
+#define RKISP2_CIF_ISP_AWB_MAX_Y_READ(x) (((x) >> 24) & 0xFF)
+/* ISP_AWB_MEAN */
+#define RKISP2_CIF_ISP_AWB_GET_MEAN_CR_R(x) ((x) & 0xFF)
+#define RKISP2_CIF_ISP_AWB_GET_MEAN_CB_B(x) (((x) >> 8) & 0xFF)
+#define RKISP2_CIF_ISP_AWB_GET_MEAN_Y_G(x) (((x) >> 16) & 0xFF)
+/* ISP_AWB_WHITE_CNT */
+#define RKISP2_CIF_ISP_AWB_GET_PIXEL_CNT(x) ((x) & 0x3FFFFFF)
+
+#define RKISP2_CIF_ISP_AWB_GAINS_MAX_VAL 0x000003FF
+#define RKISP2_CIF_ISP_AWB_WINDOW_OFFSET_MAX 0x00000FFF
+#define RKISP2_CIF_ISP_AWB_WINDOW_MAX_SIZE 0x00001FFF
+#define RKISP2_CIF_ISP_AWB_CBCR_MAX_REF 0x000000FF
+#define RKISP2_CIF_ISP_AWB_THRES_MAX_YC 0x000000FF
+
+/* AE */
+/* ISP_EXP_CTRL */
+#define RKISP2_CIF_ISP_EXP_ENA BIT(0)
+#define RKISP2_CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1)
+#define RKISP2_CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 2)
+/*
+ *'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)
+ *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
+ */
+#define RKISP2_CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31)
+
+/* ISP_EXP_H_SIZE */
+#define RKISP2_CIF_ISP_EXP_H_SIZE_SET_V10(x) ((x) & 0x7FF)
+#define RKISP2_CIF_ISP_EXP_HEIGHT_MASK_V10 0x000007FF
+/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
+#define RKISP2_CIF_ISP_EXP_V_SIZE_SET_V10(x) ((x) & 0x7FE)
+
+/* ISP_EXP_H_OFFSET */
+#define RKISP2_CIF_ISP_EXP_H_OFFSET_SET_V10(x) ((x) & 0x1FFF)
+#define RKISP2_CIF_ISP_EXP_MAX_HOFFS_V10 2424
+/* ISP_EXP_V_OFFSET */
+#define RKISP2_CIF_ISP_EXP_V_OFFSET_SET_V10(x) ((x) & 0x1FFF)
+#define RKISP2_CIF_ISP_EXP_MAX_VOFFS_V10 1806
+
+#define RKISP2_CIF_ISP_EXP_ROW_NUM_V10 5
+#define RKISP2_CIF_ISP_EXP_COLUMN_NUM_V10 5
+#define RKISP2_CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
+ (RKISP2_CIF_ISP_EXP_ROW_NUM_V10 * RKISP2_CIF_ISP_EXP_COLUMN_NUM_V10)
+#define RKISP2_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 516
+#define RKISP2_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 35
+#define RKISP2_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 390
+#define RKISP2_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 28
+#define RKISP2_CIF_ISP_EXP_MAX_HSIZE_V10 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * RKISP2_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
+#define RKISP2_CIF_ISP_EXP_MIN_HSIZE_V10 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * RKISP2_CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
+#define RKISP2_CIF_ISP_EXP_MAX_VSIZE_V10 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * RKISP2_CIF_ISP_EXP_ROW_NUM_V10 + 1)
+#define RKISP2_CIF_ISP_EXP_MIN_VSIZE_V10 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * RKISP2_CIF_ISP_EXP_ROW_NUM_V10 + 1)
+
+/* ISP_EXP_H_SIZE */
+#define RKISP2_CIF_ISP_EXP_H_SIZE_SET_V12(x) ((x) & 0x7FF)
+#define RKISP2_CIF_ISP_EXP_HEIGHT_MASK_V12 0x000007FF
+/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
+#define RKISP2_CIF_ISP_EXP_V_SIZE_SET_V12(x) (((x) & 0x7FE) << 16)
+
+/* ISP_EXP_H_OFFSET */
+#define RKISP2_CIF_ISP_EXP_H_OFFSET_SET_V12(x) ((x) & 0x1FFF)
+#define RKISP2_CIF_ISP_EXP_MAX_HOFFS_V12 0x1FFF
+/* ISP_EXP_V_OFFSET */
+#define RKISP2_CIF_ISP_EXP_V_OFFSET_SET_V12(x) (((x) & 0x1FFF) << 16)
+#define RKISP2_CIF_ISP_EXP_MAX_VOFFS_V12 0x1FFF
+
+#define RKISP2_CIF_ISP_EXP_ROW_NUM_V12 15
+#define RKISP2_CIF_ISP_EXP_COLUMN_NUM_V12 15
+#define RKISP2_CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
+ (RKISP2_CIF_ISP_EXP_ROW_NUM_V12 * RKISP2_CIF_ISP_EXP_COLUMN_NUM_V12)
+#define RKISP2_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 0x7FF
+#define RKISP2_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 0xE
+#define RKISP2_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 0x7FE
+#define RKISP2_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 0xE
+#define RKISP2_CIF_ISP_EXP_MAX_HSIZE_V12 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * RKISP2_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
+#define RKISP2_CIF_ISP_EXP_MIN_HSIZE_V12 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * RKISP2_CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
+#define RKISP2_CIF_ISP_EXP_MAX_VSIZE_V12 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * RKISP2_CIF_ISP_EXP_ROW_NUM_V12 + 1)
+#define RKISP2_CIF_ISP_EXP_MIN_VSIZE_V12 \
+ (RKISP2_CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * RKISP2_CIF_ISP_EXP_ROW_NUM_V12 + 1)
+
+#define RKISP2_CIF_ISP_EXP_GET_MEAN_xy0_V12(x) ((x) & 0xFF)
+#define RKISP2_CIF_ISP_EXP_GET_MEAN_xy1_V12(x) (((x) >> 8) & 0xFF)
+#define RKISP2_CIF_ISP_EXP_GET_MEAN_xy2_V12(x) (((x) >> 16) & 0xFF)
+#define RKISP2_CIF_ISP_EXP_GET_MEAN_xy3_V12(x) (((x) >> 24) & 0xFF)
+
+/* LSC: ISP_LSC_CTRL */
+#define RKISP2_CIF_ISP_LSC_CTRL_ENA BIT(0)
+#define RKISP2_CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00
+#define RKISP2_CIF_ISP_LSC_GRAD_RESERVED_V10 0xF000F000
+#define RKISP2_CIF_ISP_LSC_SAMPLE_RESERVED_V10 0xF000F000
+#define RKISP2_CIF_ISP_LSC_GRAD_RESERVED_V12 0xE000E000
+#define RKISP2_CIF_ISP_LSC_SAMPLE_RESERVED_V12 0xE000E000
+#define RKISP2_CIF_ISP_LSC_SECTORS_MAX 17
+#define RKISP2_CIF_ISP_LSC_TABLE_DATA_V10(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
+#define RKISP2_CIF_ISP_LSC_TABLE_DATA_V12(v0, v1) \
+ (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
+#define RKISP2_CIF_ISP_LSC_SECT_SIZE(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
+#define RKISP2_CIF_ISP_LSC_GRAD_SIZE(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
+
+/* LSC: ISP_LSC_TABLE_SEL */
+#define RKISP2_CIF_ISP_LSC_TABLE_0 0
+#define RKISP2_CIF_ISP_LSC_TABLE_1 1
+
+/* LSC: ISP_LSC_STATUS */
+#define RKISP2_CIF_ISP_LSC_ACTIVE_TABLE BIT(1)
+#define RKISP2_CIF_ISP_LSC_TABLE_ADDRESS_0 0
+#define RKISP2_CIF_ISP_LSC_TABLE_ADDRESS_153 153
+
+/* FLT */
+/* ISP_FILT_MODE */
+#define RKISP2_CIF_ISP_FLT_ENA BIT(0)
+
+/*
+ * 0: green filter static mode (active filter factor = FILT_FAC_MID)
+ * 1: dynamic noise reduction/sharpen Default
+ */
+#define RKISP2_CIF_ISP_FLT_MODE_DNR BIT(1)
+#define RKISP2_CIF_ISP_FLT_MODE_MAX 1
+#define RKISP2_CIF_ISP_FLT_CHROMA_V_MODE(x) (((x) & 0x3) << 4)
+#define RKISP2_CIF_ISP_FLT_CHROMA_H_MODE(x) (((x) & 0x3) << 6)
+#define RKISP2_CIF_ISP_FLT_CHROMA_MODE_MAX 3
+#define RKISP2_CIF_ISP_FLT_GREEN_STAGE1(x) (((x) & 0xF) << 8)
+#define RKISP2_CIF_ISP_FLT_GREEN_STAGE1_MAX 8
+#define RKISP2_CIF_ISP_FLT_THREAD_RESERVED 0xFFFFFC00
+#define RKISP2_CIF_ISP_FLT_FAC_RESERVED 0xFFFFFFC0
+#define RKISP2_CIF_ISP_FLT_LUM_WEIGHT_RESERVED 0xFFF80000
+
+#define RKISP2_CIF_ISP_CTK_COEFF_RESERVED 0xFFFFF800
+#define RKISP2_CIF_ISP_XTALK_OFFSET_RESERVED 0xFFFFF000
+
+#define RKISP2_CIF_ISP_FLT_LEVEL_OLD_LP BIT(16)
+
+/* GOC */
+#define RKISP2_CIF_ISP_GAMMA_OUT_MODE_EQU BIT(0)
+#define RKISP2_CIF_ISP_GOC_MODE_MAX 1
+#define RKISP2_CIF_ISP_GOC_RESERVED 0xFFFFF800
+/* ISP_CTRL BIT 11*/
+#define RKISP2_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA_READ(x) (((x) >> 11) & 1)
+
+/* DPCC */
+/* ISP_DPCC_MODE */
+#define RKISP2_CIF_ISP_DPCC_ENA BIT(0)
+#define RKISP2_CIF_ISP_DPCC_MODE_MAX 0x07
+#define RKISP2_CIF_ISP_DPCC_OUTPUTMODE_MAX 0x0F
+#define RKISP2_CIF_ISP_DPCC_SETUSE_MAX 0x0F
+#define RKISP2_CIF_ISP_DPCC_METHODS_SET_RESERVED 0xFFFFE000
+#define RKISP2_CIF_ISP_DPCC_LINE_THRESH_RESERVED 0xFFFF0000
+#define RKISP2_CIF_ISP_DPCC_LINE_MAD_FAC_RESERVED 0xFFFFC0C0
+#define RKISP2_CIF_ISP_DPCC_PG_FAC_RESERVED 0xFFFFC0C0
+#define RKISP2_CIF_ISP_DPCC_RND_THRESH_RESERVED 0xFFFF0000
+#define RKISP2_CIF_ISP_DPCC_RG_FAC_RESERVED 0xFFFFC0C0
+#define RKISP2_CIF_ISP_DPCC_RO_LIMIT_RESERVED 0xFFFFF000
+#define RKISP2_CIF_ISP_DPCC_RND_OFFS_RESERVED 0xFFFFF000
+#define RKISP2_CIF_ISP_DPCC_MODE_DPCC_ENABLE BIT(0)
+#define RKISP2_CIF_ISP_DPCC_OUTPUT_MODE_MASK GENMASK(3, 0)
+#define RKISP2_CIF_ISP_DPCC_SET_USE_MASK GENMASK(3, 0)
+#define RKISP2_CIF_ISP_DPCC_METHODS_SET_MASK 0x00001f1f
+#define RKISP2_CIF_ISP_DPCC_LINE_THRESH_MASK 0x0000ffff
+#define RKISP2_CIF_ISP_DPCC_LINE_MAD_FAC_MASK 0x00003f3f
+#define RKISP2_CIF_ISP_DPCC_PG_FAC_MASK 0x00003f3f
+#define RKISP2_CIF_ISP_DPCC_RND_THRESH_MASK 0x0000ffff
+#define RKISP2_CIF_ISP_DPCC_RG_FAC_MASK 0x00003f3f
+#define RKISP2_CIF_ISP_DPCC_RND_OFFS_MASK 0x00000fff
+#define RKISP2_CIF_ISP_DPCC_RO_LIMIT_MASK 0x00000fff
+
+/* BLS */
+/* ISP_BLS_CTRL */
+#define RKISP2_CIF_ISP_BLS_ENA BIT(0)
+#define RKISP2_CIF_ISP_BLS_MODE_MEASURED BIT(1)
+#define RKISP2_CIF_ISP_BLS_MODE_FIXED 0
+#define RKISP2_CIF_ISP_BLS_WINDOW_1 (1 << 2)
+#define RKISP2_CIF_ISP_BLS_WINDOW_2 (2 << 2)
+
+/* GAMMA-IN */
+#define RKISP2_CIFISP_DEGAMMA_X_RESERVED \
+ ((1 << 31) | (1 << 27) | (1 << 23) | (1 << 19) |\
+ (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
+#define RKISP2_CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000
+
+/* GAMMA-OUT */
+#define RKISP2_CIF_ISP_GAMMA_REG_VALUE_V12(x, y) \
+ (((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
+#define RKISP2_CIF_ISP_GAMMA_VALUE_V12(x, y) \
+ (((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
+
+/* AFM */
+#define RKISP2_CIF_ISP_AFM_ENA BIT(0)
+#define RKISP2_CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000
+#define RKISP2_CIF_ISP_AFM_VAR_SHIFT_RESERVED 0xFFF8FFF8
+#define RKISP2_CIF_ISP_AFM_WINDOW_X_RESERVED 0xE000
+#define RKISP2_CIF_ISP_AFM_WINDOW_Y_RESERVED 0xF000
+#define RKISP2_CIF_ISP_AFM_WINDOW_X_MIN 0x5
+#define RKISP2_CIF_ISP_AFM_WINDOW_Y_MIN 0x2
+#define RKISP2_CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16)
+#define RKISP2_CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF)
+#define RKISP2_CIF_ISP_AFM_SET_SHIFT_a_V12(x, y) (((x) & 0x7) << 16 | ((y) & 0x7) << 0)
+#define RKISP2_CIF_ISP_AFM_SET_SHIFT_b_V12(x, y) (((x) & 0x7) << 20 | ((y) & 0x7) << 4)
+#define RKISP2_CIF_ISP_AFM_SET_SHIFT_c_V12(x, y) (((x) & 0x7) << 24 | ((y) & 0x7) << 8)
+#define RKISP2_CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x) (((x) & 0x70000) >> 16)
+#define RKISP2_CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x) ((x) & 0x7)
+
+/* DPF */
+#define RKISP2_CIF_ISP_DPF_MODE_EN BIT(0)
+#define RKISP2_CIF_ISP_DPF_MODE_B_FLT_DIS BIT(1)
+#define RKISP2_CIF_ISP_DPF_MODE_GB_FLT_DIS BIT(2)
+#define RKISP2_CIF_ISP_DPF_MODE_GR_FLT_DIS BIT(3)
+#define RKISP2_CIF_ISP_DPF_MODE_R_FLT_DIS BIT(4)
+#define RKISP2_CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9 BIT(5)
+#define RKISP2_CIF_ISP_DPF_MODE_NLL_SEGMENTATION BIT(6)
+#define RKISP2_CIF_ISP_DPF_MODE_AWB_GAIN_COMP BIT(7)
+#define RKISP2_CIF_ISP_DPF_MODE_LSC_GAIN_COMP BIT(8)
+#define RKISP2_CIF_ISP_DPF_MODE_USE_NF_GAIN BIT(9)
+#define RKISP2_CIF_ISP_DPF_NF_GAIN_RESERVED 0xFFFFF000
+#define RKISP2_CIF_ISP_DPF_SPATIAL_COEFF_MAX 0x1F
+#define RKISP2_CIF_ISP_DPF_NLL_COEFF_N_MAX 0x3FF
+
+/* CSI0 */
+#define RKISP2_CIF_ISP_CSI0_IMASK_LINECNT BIT(12)
+#define RKISP2_CIF_ISP_CSI0_IMASK_RAW1_OUT_V_END BIT(11)
+#define RKISP2_CIF_ISP_CSI0_IMASK_RAW0_OUT_V_END BIT(10)
+#define RKISP2_CIF_ISP_CSI0_IMASK_FRAME_END(a) (((a) & 0x3F) << 0)
+
+#define RKISP2_CIF_ISP_CSI0_IMASK2_PHY_ERRSOTHS(a) (((a) & 0x0F) << 4)
+#define RKISP2_CIF_ISP_CSI0_IMASK2_PHY_ERRCONTROL(a) (((a) & 0x0F) << 16)
+#define RKISP2_CIF_ISP_CSI0_IMASK1_PHY_ERRSOTSYNC(a) (((a) & 0x0F) << 8)
+#define RKISP2_CIF_ISP_CSI0_IMASK1_PHY_ERREOTSYNC(a) (((a) & 0x0F) << 4)
+
+#define RKISP2_CIF_ISP_CSI0_DMATX0_VC(a) (((a) & 0xFF) << 8)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_SIMG_SWP BIT(2)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_SIMG_MODE BIT(1)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_EN BIT(0)
+
+/* MIPI RX */
+#define RKISP2_CIF_ISP_CSI_RAW_RD_LE_ALIGN BIT(4)
+#define RKISP2_CIF_ISP_CSI_RAW_RD_UNCOMPRESS BIT(3)
+
+
+/* =================================================================== */
+/* CIF Registers */
+/* =================================================================== */
+#define RKISP2_CIF_CTRL_BASE 0x00000000
+#define RKISP2_CIF_CCL (RKISP2_CIF_CTRL_BASE + 0x00000000)
+#define RKISP2_CIF_VI_ID (RKISP2_CIF_CTRL_BASE + 0x00000008)
+#define RKISP2_CIF_VI_ISP_CLK_CTRL_V12 (RKISP2_CIF_CTRL_BASE + 0x0000000C)
+#define RKISP2_CIF_ICCL (RKISP2_CIF_CTRL_BASE + 0x00000010)
+#define RKISP2_CIF_IRCL (RKISP2_CIF_CTRL_BASE + 0x00000014)
+#define RKISP2_CIF_VI_DPCL (RKISP2_CIF_CTRL_BASE + 0x00000018)
+
+#define RKISP2_CIF_IMG_EFF_BASE 0x00000200
+#define RKISP2_CIF_IMG_EFF_CTRL (RKISP2_CIF_IMG_EFF_BASE + 0x00000000)
+#define RKISP2_CIF_IMG_EFF_COLOR_SEL (RKISP2_CIF_IMG_EFF_BASE + 0x00000004)
+#define RKISP2_CIF_IMG_EFF_MAT_1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000008)
+#define RKISP2_CIF_IMG_EFF_MAT_2 (RKISP2_CIF_IMG_EFF_BASE + 0x0000000C)
+#define RKISP2_CIF_IMG_EFF_MAT_3 (RKISP2_CIF_IMG_EFF_BASE + 0x00000010)
+#define RKISP2_CIF_IMG_EFF_MAT_4 (RKISP2_CIF_IMG_EFF_BASE + 0x00000014)
+#define RKISP2_CIF_IMG_EFF_MAT_5 (RKISP2_CIF_IMG_EFF_BASE + 0x00000018)
+#define RKISP2_CIF_IMG_EFF_TINT (RKISP2_CIF_IMG_EFF_BASE + 0x0000001C)
+#define RKISP2_CIF_IMG_EFF_CTRL_SHD (RKISP2_CIF_IMG_EFF_BASE + 0x00000020)
+#define RKISP2_CIF_IMG_EFF_SHARPEN (RKISP2_CIF_IMG_EFF_BASE + 0x00000024)
+
+#define RKISP2_CIF_RKSHARP_CTRL (RKISP2_CIF_IMG_EFF_BASE + 0x00000030)
+#define RKISP2_CIF_RKSHARP_YAVG_THR (RKISP2_CIF_IMG_EFF_BASE + 0x00000034)
+#define RKISP2_CIF_RKSHARP_DELTA_P0_P1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000038)
+#define RKISP2_CIF_RKSHARP_DELTA_P2_P3 (RKISP2_CIF_IMG_EFF_BASE + 0x0000003c)
+#define RKISP2_CIF_RKSHARP_DELTA_P4 (RKISP2_CIF_IMG_EFF_BASE + 0x00000040)
+#define RKISP2_CIF_RKSHARP_NPIXEL_P0_P1_P2_P3 (RKISP2_CIF_IMG_EFF_BASE + 0x00000044)
+#define RKISP2_CIF_RKSHARP_NPIXEL_P4 (RKISP2_CIF_IMG_EFF_BASE + 0x00000048)
+#define RKISP2_CIF_RKSHARP_GAUSS_FLAT_COE1 (RKISP2_CIF_IMG_EFF_BASE + 0x0000004c)
+#define RKISP2_CIF_RKSHARP_GAUSS_FLAT_COE2 (RKISP2_CIF_IMG_EFF_BASE + 0x00000050)
+#define RKISP2_CIF_RKSHARP_GAUSS_FLAT_COE3 (RKISP2_CIF_IMG_EFF_BASE + 0x00000054)
+#define RKISP2_CIF_RKSHARP_GAUSS_NOISE_COE1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000058)
+#define RKISP2_CIF_RKSHARP_GAUSS_NOISE_COE2 (RKISP2_CIF_IMG_EFF_BASE + 0x0000005c)
+#define RKISP2_CIF_RKSHARP_GAUSS_NOISE_COE3 (RKISP2_CIF_IMG_EFF_BASE + 0x00000060)
+#define RKISP2_CIF_RKSHARP_GAUSS_OTHER_COE1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000064)
+#define RKISP2_CIF_RKSHARP_GAUSS_OTHER_COE2 (RKISP2_CIF_IMG_EFF_BASE + 0x00000068)
+#define RKISP2_CIF_RKSHARP_GAUSS_OTHER_COE3 (RKISP2_CIF_IMG_EFF_BASE + 0x0000006c)
+#define RKISP2_CIF_RKSHARP_LINE1_FILTER_COE1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000070)
+#define RKISP2_CIF_RKSHARP_LINE1_FILTER_COE2 (RKISP2_CIF_IMG_EFF_BASE + 0x00000074)
+#define RKISP2_CIF_RKSHARP_LINE2_FILTER_COE1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000078)
+#define RKISP2_CIF_RKSHARP_LINE2_FILTER_COE2 (RKISP2_CIF_IMG_EFF_BASE + 0x0000007c)
+#define RKISP2_CIF_RKSHARP_LINE2_FILTER_COE3 (RKISP2_CIF_IMG_EFF_BASE + 0x00000080)
+#define RKISP2_CIF_RKSHARP_LINE3_FILTER_COE1 (RKISP2_CIF_IMG_EFF_BASE + 0x00000084)
+#define RKISP2_CIF_RKSHARP_LINE3_FILTER_COE2 (RKISP2_CIF_IMG_EFF_BASE + 0x00000088)
+#define RKISP2_CIF_RKSHARP_GRAD_SEQ_P0_P1 (RKISP2_CIF_IMG_EFF_BASE + 0x0000008c)
+#define RKISP2_CIF_RKSHARP_GRAD_SEQ_P2_P3 (RKISP2_CIF_IMG_EFF_BASE + 0x00000090)
+#define RKISP2_CIF_RKSHARP_SHARP_FACTOR_P0_P1_P2 (RKISP2_CIF_IMG_EFF_BASE + 0x00000094)
+#define RKISP2_CIF_RKSHARP_SHARP_FACTOR_P3_P4 (RKISP2_CIF_IMG_EFF_BASE + 0x00000098)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_FLAT_COE11_COE14 (RKISP2_CIF_IMG_EFF_BASE + 0x0000009c)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_FLAT_COE15_COE23 (RKISP2_CIF_IMG_EFF_BASE + 0x000000a0)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_FLAT_COE24_COE32 (RKISP2_CIF_IMG_EFF_BASE + 0x000000a4)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_FLAT_COE33_COE35 (RKISP2_CIF_IMG_EFF_BASE + 0x000000a8)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_NOISE_COE11_COE14 (RKISP2_CIF_IMG_EFF_BASE + 0x000000ac)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_NOISE_COE15_COE23 (RKISP2_CIF_IMG_EFF_BASE + 0x000000b0)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_NOISE_COE24_COE32 (RKISP2_CIF_IMG_EFF_BASE + 0x000000b4)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_NOISE_COE33_COE35 (RKISP2_CIF_IMG_EFF_BASE + 0x000000b8)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_OTHER_COE11_COE14 (RKISP2_CIF_IMG_EFF_BASE + 0x000000bc)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_OTHER_COE15_COE23 (RKISP2_CIF_IMG_EFF_BASE + 0x000000c0)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_OTHER_COE24_COE32 (RKISP2_CIF_IMG_EFF_BASE + 0x000000c4)
+#define RKISP2_CIF_RKSHARP_UV_GAUSS_OTHER_COE33_COE35 (RKISP2_CIF_IMG_EFF_BASE + 0x000000c8)
+
+#define RKISP2_CIF_SUPER_IMP_BASE 0x00000300
+#define RKISP2_CIF_SUPER_IMP_CTRL (RKISP2_CIF_SUPER_IMP_BASE + 0x00000000)
+#define RKISP2_CIF_SUPER_IMP_OFFSET_X (RKISP2_CIF_SUPER_IMP_BASE + 0x00000004)
+#define RKISP2_CIF_SUPER_IMP_OFFSET_Y (RKISP2_CIF_SUPER_IMP_BASE + 0x00000008)
+#define RKISP2_CIF_SUPER_IMP_COLOR_Y (RKISP2_CIF_SUPER_IMP_BASE + 0x0000000C)
+#define RKISP2_CIF_SUPER_IMP_COLOR_CB (RKISP2_CIF_SUPER_IMP_BASE + 0x00000010)
+#define RKISP2_CIF_SUPER_IMP_COLOR_CR (RKISP2_CIF_SUPER_IMP_BASE + 0x00000014)
+
+#define RKISP2_CIF_ISP_BASE 0x00000400
+#define RKISP2_CIF_ISP_CTRL (RKISP2_CIF_ISP_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_ACQ_PROP (RKISP2_CIF_ISP_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_ACQ_H_OFFS (RKISP2_CIF_ISP_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_ACQ_V_OFFS (RKISP2_CIF_ISP_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_ACQ_H_SIZE (RKISP2_CIF_ISP_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_ACQ_V_SIZE (RKISP2_CIF_ISP_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_ACQ_NR_FRAMES (RKISP2_CIF_ISP_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_GAMMA_DX_LO (RKISP2_CIF_ISP_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_GAMMA_DX_HI (RKISP2_CIF_ISP_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_GAMMA_R_Y0 (RKISP2_CIF_ISP_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_GAMMA_R_Y1 (RKISP2_CIF_ISP_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_GAMMA_R_Y2 (RKISP2_CIF_ISP_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_GAMMA_R_Y3 (RKISP2_CIF_ISP_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_GAMMA_R_Y4 (RKISP2_CIF_ISP_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_GAMMA_R_Y5 (RKISP2_CIF_ISP_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_GAMMA_R_Y6 (RKISP2_CIF_ISP_BASE + 0x0000003C)
+#define RKISP2_CIF_ISP_GAMMA_R_Y7 (RKISP2_CIF_ISP_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_GAMMA_R_Y8 (RKISP2_CIF_ISP_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_GAMMA_R_Y9 (RKISP2_CIF_ISP_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_GAMMA_R_Y10 (RKISP2_CIF_ISP_BASE + 0x0000004C)
+#define RKISP2_CIF_ISP_GAMMA_R_Y11 (RKISP2_CIF_ISP_BASE + 0x00000050)
+#define RKISP2_CIF_ISP_GAMMA_R_Y12 (RKISP2_CIF_ISP_BASE + 0x00000054)
+#define RKISP2_CIF_ISP_GAMMA_R_Y13 (RKISP2_CIF_ISP_BASE + 0x00000058)
+#define RKISP2_CIF_ISP_GAMMA_R_Y14 (RKISP2_CIF_ISP_BASE + 0x0000005C)
+#define RKISP2_CIF_ISP_GAMMA_R_Y15 (RKISP2_CIF_ISP_BASE + 0x00000060)
+#define RKISP2_CIF_ISP_GAMMA_R_Y16 (RKISP2_CIF_ISP_BASE + 0x00000064)
+#define RKISP2_CIF_ISP_GAMMA_G_Y0 (RKISP2_CIF_ISP_BASE + 0x00000068)
+#define RKISP2_CIF_ISP_GAMMA_G_Y1 (RKISP2_CIF_ISP_BASE + 0x0000006C)
+#define RKISP2_CIF_ISP_GAMMA_G_Y2 (RKISP2_CIF_ISP_BASE + 0x00000070)
+#define RKISP2_CIF_ISP_GAMMA_G_Y3 (RKISP2_CIF_ISP_BASE + 0x00000074)
+#define RKISP2_CIF_ISP_GAMMA_G_Y4 (RKISP2_CIF_ISP_BASE + 0x00000078)
+#define RKISP2_CIF_ISP_GAMMA_G_Y5 (RKISP2_CIF_ISP_BASE + 0x0000007C)
+#define RKISP2_CIF_ISP_GAMMA_G_Y6 (RKISP2_CIF_ISP_BASE + 0x00000080)
+#define RKISP2_CIF_ISP_GAMMA_G_Y7 (RKISP2_CIF_ISP_BASE + 0x00000084)
+#define RKISP2_CIF_ISP_GAMMA_G_Y8 (RKISP2_CIF_ISP_BASE + 0x00000088)
+#define RKISP2_CIF_ISP_GAMMA_G_Y9 (RKISP2_CIF_ISP_BASE + 0x0000008C)
+#define RKISP2_CIF_ISP_GAMMA_G_Y10 (RKISP2_CIF_ISP_BASE + 0x00000090)
+#define RKISP2_CIF_ISP_GAMMA_G_Y11 (RKISP2_CIF_ISP_BASE + 0x00000094)
+#define RKISP2_CIF_ISP_GAMMA_G_Y12 (RKISP2_CIF_ISP_BASE + 0x00000098)
+#define RKISP2_CIF_ISP_GAMMA_G_Y13 (RKISP2_CIF_ISP_BASE + 0x0000009C)
+#define RKISP2_CIF_ISP_GAMMA_G_Y14 (RKISP2_CIF_ISP_BASE + 0x000000A0)
+#define RKISP2_CIF_ISP_GAMMA_G_Y15 (RKISP2_CIF_ISP_BASE + 0x000000A4)
+#define RKISP2_CIF_ISP_GAMMA_G_Y16 (RKISP2_CIF_ISP_BASE + 0x000000A8)
+#define RKISP2_CIF_ISP_GAMMA_B_Y0 (RKISP2_CIF_ISP_BASE + 0x000000AC)
+#define RKISP2_CIF_ISP_GAMMA_B_Y1 (RKISP2_CIF_ISP_BASE + 0x000000B0)
+#define RKISP2_CIF_ISP_GAMMA_B_Y2 (RKISP2_CIF_ISP_BASE + 0x000000B4)
+#define RKISP2_CIF_ISP_GAMMA_B_Y3 (RKISP2_CIF_ISP_BASE + 0x000000B8)
+#define RKISP2_CIF_ISP_GAMMA_B_Y4 (RKISP2_CIF_ISP_BASE + 0x000000BC)
+#define RKISP2_CIF_ISP_GAMMA_B_Y5 (RKISP2_CIF_ISP_BASE + 0x000000C0)
+#define RKISP2_CIF_ISP_GAMMA_B_Y6 (RKISP2_CIF_ISP_BASE + 0x000000C4)
+#define RKISP2_CIF_ISP_GAMMA_B_Y7 (RKISP2_CIF_ISP_BASE + 0x000000C8)
+#define RKISP2_CIF_ISP_GAMMA_B_Y8 (RKISP2_CIF_ISP_BASE + 0x000000CC)
+#define RKISP2_CIF_ISP_GAMMA_B_Y9 (RKISP2_CIF_ISP_BASE + 0x000000D0)
+#define RKISP2_CIF_ISP_GAMMA_B_Y10 (RKISP2_CIF_ISP_BASE + 0x000000D4)
+#define RKISP2_CIF_ISP_GAMMA_B_Y11 (RKISP2_CIF_ISP_BASE + 0x000000D8)
+#define RKISP2_CIF_ISP_GAMMA_B_Y12 (RKISP2_CIF_ISP_BASE + 0x000000DC)
+#define RKISP2_CIF_ISP_GAMMA_B_Y13 (RKISP2_CIF_ISP_BASE + 0x000000E0)
+#define RKISP2_CIF_ISP_GAMMA_B_Y14 (RKISP2_CIF_ISP_BASE + 0x000000E4)
+#define RKISP2_CIF_ISP_GAMMA_B_Y15 (RKISP2_CIF_ISP_BASE + 0x000000E8)
+#define RKISP2_CIF_ISP_GAMMA_B_Y16 (RKISP2_CIF_ISP_BASE + 0x000000EC)
+
+#define RKISP2_CIF_ISP_AWB_PROP_V10 (RKISP2_CIF_ISP_BASE + 0x00000110)
+#define RKISP2_CIF_ISP_AWB_WND_H_OFFS_V10 (RKISP2_CIF_ISP_BASE + 0x00000114)
+#define RKISP2_CIF_ISP_AWB_WND_V_OFFS_V10 (RKISP2_CIF_ISP_BASE + 0x00000118)
+#define RKISP2_CIF_ISP_AWB_WND_H_SIZE_V10 (RKISP2_CIF_ISP_BASE + 0x0000011C)
+#define RKISP2_CIF_ISP_AWB_WND_V_SIZE_V10 (RKISP2_CIF_ISP_BASE + 0x00000120)
+#define RKISP2_CIF_ISP_AWB_FRAMES_V10 (RKISP2_CIF_ISP_BASE + 0x00000124)
+#define RKISP2_CIF_ISP_AWB_REF_V10 (RKISP2_CIF_ISP_BASE + 0x00000128)
+#define RKISP2_CIF_ISP_AWB_THRESH_V10 (RKISP2_CIF_ISP_BASE + 0x0000012C)
+#define RKISP2_CIF_ISP_AWB_GAIN_G_V10 (RKISP2_CIF_ISP_BASE + 0x00000138)
+#define RKISP2_CIF_ISP_AWB_GAIN_RB_V10 (RKISP2_CIF_ISP_BASE + 0x0000013C)
+#define RKISP2_CIF_ISP_AWB_WHITE_CNT_V10 (RKISP2_CIF_ISP_BASE + 0x00000140)
+#define RKISP2_CIF_ISP_AWB_MEAN_V10 (RKISP2_CIF_ISP_BASE + 0x00000144)
+
+#define RKISP2_CIF_ISP_AWB_PROP_V12 (RKISP2_CIF_ISP_BASE + 0x00000110)
+#define RKISP2_CIF_ISP_AWB_SIZE_V12 (RKISP2_CIF_ISP_BASE + 0x00000114)
+#define RKISP2_CIF_ISP_AWB_OFFS_V12 (RKISP2_CIF_ISP_BASE + 0x00000118)
+#define RKISP2_CIF_ISP_AWB_REF_V12 (RKISP2_CIF_ISP_BASE + 0x0000011C)
+#define RKISP2_CIF_ISP_AWB_THRESH_V12 (RKISP2_CIF_ISP_BASE + 0x00000120)
+#define RKISP2_CIF_ISP_X_COOR12_V12 (RKISP2_CIF_ISP_BASE + 0x00000124)
+#define RKISP2_CIF_ISP_X_COOR34_V12 (RKISP2_CIF_ISP_BASE + 0x00000128)
+#define RKISP2_CIF_ISP_AWB_WHITE_CNT_V12 (RKISP2_CIF_ISP_BASE + 0x0000012C)
+#define RKISP2_CIF_ISP_AWB_MEAN_V12 (RKISP2_CIF_ISP_BASE + 0x00000130)
+#define RKISP2_CIF_ISP_DEGAIN_V12 (RKISP2_CIF_ISP_BASE + 0x00000134)
+#define RKISP2_CIF_ISP_AWB_GAIN_G_V12 (RKISP2_CIF_ISP_BASE + 0x00000138)
+#define RKISP2_CIF_ISP_AWB_GAIN_RB_V12 (RKISP2_CIF_ISP_BASE + 0x0000013C)
+#define RKISP2_CIF_ISP_REGION_LINE_V12 (RKISP2_CIF_ISP_BASE + 0x00000140)
+#define RKISP2_CIF_ISP_WP_CNT_REGION0_V12 (RKISP2_CIF_ISP_BASE + 0x00000160)
+#define RKISP2_CIF_ISP_WP_CNT_REGION1_V12 (RKISP2_CIF_ISP_BASE + 0x00000164)
+#define RKISP2_CIF_ISP_WP_CNT_REGION2_V12 (RKISP2_CIF_ISP_BASE + 0x00000168)
+#define RKISP2_CIF_ISP_WP_CNT_REGION3_V12 (RKISP2_CIF_ISP_BASE + 0x0000016C)
+
+#define RKISP2_CIF_ISP_CC_COEFF_0 (RKISP2_CIF_ISP_BASE + 0x00000170)
+#define RKISP2_CIF_ISP_CC_COEFF_1 (RKISP2_CIF_ISP_BASE + 0x00000174)
+#define RKISP2_CIF_ISP_CC_COEFF_2 (RKISP2_CIF_ISP_BASE + 0x00000178)
+#define RKISP2_CIF_ISP_CC_COEFF_3 (RKISP2_CIF_ISP_BASE + 0x0000017C)
+#define RKISP2_CIF_ISP_CC_COEFF_4 (RKISP2_CIF_ISP_BASE + 0x00000180)
+#define RKISP2_CIF_ISP_CC_COEFF_5 (RKISP2_CIF_ISP_BASE + 0x00000184)
+#define RKISP2_CIF_ISP_CC_COEFF_6 (RKISP2_CIF_ISP_BASE + 0x00000188)
+#define RKISP2_CIF_ISP_CC_COEFF_7 (RKISP2_CIF_ISP_BASE + 0x0000018C)
+#define RKISP2_CIF_ISP_CC_COEFF_8 (RKISP2_CIF_ISP_BASE + 0x00000190)
+#define RKISP2_CIF_ISP_OUT_H_OFFS (RKISP2_CIF_ISP_BASE + 0x00000194)
+#define RKISP2_CIF_ISP_OUT_V_OFFS (RKISP2_CIF_ISP_BASE + 0x00000198)
+#define RKISP2_CIF_ISP_OUT_H_SIZE (RKISP2_CIF_ISP_BASE + 0x0000019C)
+#define RKISP2_CIF_ISP_OUT_V_SIZE (RKISP2_CIF_ISP_BASE + 0x000001A0)
+#define RKISP2_CIF_ISP_DEMOSAIC (RKISP2_CIF_ISP_BASE + 0x000001A4)
+#define RKISP2_CIF_ISP_FLAGS_SHD (RKISP2_CIF_ISP_BASE + 0x000001A8)
+#define RKISP2_CIF_ISP_FLAGS_SHD_S_DATA_MASK GENMASK(27, 16)
+#define RKISP2_CIF_ISP_FLAGS_SHD_S_DATA_SHIFT 16
+#define RKISP2_CIF_ISP_FLAGS_SHD_S_VSYNC BIT(30)
+#define RKISP2_CIF_ISP_FLAGS_SHD_S_HSYNC BIT(31)
+#define RKISP2_CIF_ISP_OUT_H_OFFS_SHD (RKISP2_CIF_ISP_BASE + 0x000001AC)
+#define RKISP2_CIF_ISP_OUT_V_OFFS_SHD (RKISP2_CIF_ISP_BASE + 0x000001B0)
+#define RKISP2_CIF_ISP_OUT_H_SIZE_SHD (RKISP2_CIF_ISP_BASE + 0x000001B4)
+#define RKISP2_CIF_ISP_OUT_V_SIZE_SHD (RKISP2_CIF_ISP_BASE + 0x000001B8)
+#define RKISP2_CIF_ISP_IMSC (RKISP2_CIF_ISP_BASE + 0x000001BC)
+#define RKISP2_CIF_ISP_RIS (RKISP2_CIF_ISP_BASE + 0x000001C0)
+#define RKISP2_CIF_ISP_MIS (RKISP2_CIF_ISP_BASE + 0x000001C4)
+#define RKISP2_CIF_ISP_ICR (RKISP2_CIF_ISP_BASE + 0x000001C8)
+#define RKISP2_CIF_ISP_ISR (RKISP2_CIF_ISP_BASE + 0x000001CC)
+#define RKISP2_CIF_ISP_CT_COEFF_0 (RKISP2_CIF_ISP_BASE + 0x000001D0)
+#define RKISP2_CIF_ISP_CT_COEFF_1 (RKISP2_CIF_ISP_BASE + 0x000001D4)
+#define RKISP2_CIF_ISP_CT_COEFF_2 (RKISP2_CIF_ISP_BASE + 0x000001D8)
+#define RKISP2_CIF_ISP_CT_COEFF_3 (RKISP2_CIF_ISP_BASE + 0x000001DC)
+#define RKISP2_CIF_ISP_CT_COEFF_4 (RKISP2_CIF_ISP_BASE + 0x000001E0)
+#define RKISP2_CIF_ISP_CT_COEFF_5 (RKISP2_CIF_ISP_BASE + 0x000001E4)
+#define RKISP2_CIF_ISP_CT_COEFF_6 (RKISP2_CIF_ISP_BASE + 0x000001E8)
+#define RKISP2_CIF_ISP_CT_COEFF_7 (RKISP2_CIF_ISP_BASE + 0x000001EC)
+#define RKISP2_CIF_ISP_CT_COEFF_8 (RKISP2_CIF_ISP_BASE + 0x000001F0)
+#define RKISP2_CIF_ISP_GAMMA_OUT_MODE_V10 (RKISP2_CIF_ISP_BASE + 0x000001F4)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_0_V10 (RKISP2_CIF_ISP_BASE + 0x000001F8)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_1_V10 (RKISP2_CIF_ISP_BASE + 0x000001FC)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_2_V10 (RKISP2_CIF_ISP_BASE + 0x00000200)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_3_V10 (RKISP2_CIF_ISP_BASE + 0x00000204)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_4_V10 (RKISP2_CIF_ISP_BASE + 0x00000208)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_5_V10 (RKISP2_CIF_ISP_BASE + 0x0000020C)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_6_V10 (RKISP2_CIF_ISP_BASE + 0x00000210)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_7_V10 (RKISP2_CIF_ISP_BASE + 0x00000214)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_8_V10 (RKISP2_CIF_ISP_BASE + 0x00000218)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_9_V10 (RKISP2_CIF_ISP_BASE + 0x0000021C)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_10_V10 (RKISP2_CIF_ISP_BASE + 0x00000220)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_11_V10 (RKISP2_CIF_ISP_BASE + 0x00000224)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_12_V10 (RKISP2_CIF_ISP_BASE + 0x00000228)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_13_V10 (RKISP2_CIF_ISP_BASE + 0x0000022C)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_14_V10 (RKISP2_CIF_ISP_BASE + 0x00000230)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_15_V10 (RKISP2_CIF_ISP_BASE + 0x00000234)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_16_V10 (RKISP2_CIF_ISP_BASE + 0x00000238)
+#define RKISP2_CIF_ISP_ERR (RKISP2_CIF_ISP_BASE + 0x0000023C)
+#define RKISP2_CIF_ISP_ERR_CLR (RKISP2_CIF_ISP_BASE + 0x00000240)
+#define RKISP2_CIF_ISP_FRAME_COUNT (RKISP2_CIF_ISP_BASE + 0x00000244)
+#define RKISP2_CIF_ISP_CT_OFFSET_R (RKISP2_CIF_ISP_BASE + 0x00000248)
+#define RKISP2_CIF_ISP_CT_OFFSET_G (RKISP2_CIF_ISP_BASE + 0x0000024C)
+#define RKISP2_CIF_ISP_CT_OFFSET_B (RKISP2_CIF_ISP_BASE + 0x00000250)
+#define RKISP2_CIF_ISP_GAMMA_OUT_MODE_V12 (RKISP2_CIF_ISP_BASE + 0x00000300)
+#define RKISP2_CIF_ISP_GAMMA_OUT_Y_0_V12 (RKISP2_CIF_ISP_BASE + 0x00000304)
+
+#define RKISP2_CIF_ISP_FLASH_BASE 0x00000660
+#define RKISP2_CIF_ISP_FLASH_CMD (RKISP2_CIF_ISP_FLASH_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_FLASH_CONFIG (RKISP2_CIF_ISP_FLASH_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_FLASH_PREDIV (RKISP2_CIF_ISP_FLASH_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_FLASH_DELAY (RKISP2_CIF_ISP_FLASH_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_FLASH_TIME (RKISP2_CIF_ISP_FLASH_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_FLASH_MAXP (RKISP2_CIF_ISP_FLASH_BASE + 0x00000014)
+
+#define RKISP2_CIF_ISP_SH_BASE 0x00000680
+#define RKISP2_CIF_ISP_SH_CTRL (RKISP2_CIF_ISP_SH_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_SH_PREDIV (RKISP2_CIF_ISP_SH_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_SH_DELAY (RKISP2_CIF_ISP_SH_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_SH_TIME (RKISP2_CIF_ISP_SH_BASE + 0x0000000C)
+
+#define RKISP2_CIF_C_PROC_BASE 0x00000800
+#define RKISP2_CIF_C_PROC_CTRL (RKISP2_CIF_C_PROC_BASE + 0x00000000)
+#define RKISP2_CIF_C_PROC_CONTRAST (RKISP2_CIF_C_PROC_BASE + 0x00000004)
+#define RKISP2_CIF_C_PROC_BRIGHTNESS (RKISP2_CIF_C_PROC_BASE + 0x00000008)
+#define RKISP2_CIF_C_PROC_SATURATION (RKISP2_CIF_C_PROC_BASE + 0x0000000C)
+#define RKISP2_CIF_C_PROC_HUE (RKISP2_CIF_C_PROC_BASE + 0x00000010)
+
+#define RKISP2_CIF_DUAL_CROP_BASE 0x00000880
+#define RKISP2_CIF_DUAL_CROP_CTRL (RKISP2_CIF_DUAL_CROP_BASE + 0x00000000)
+#define RKISP2_CIF_DUAL_CROP_M_H_OFFS (RKISP2_CIF_DUAL_CROP_BASE + 0x00000004)
+#define RKISP2_CIF_DUAL_CROP_M_V_OFFS (RKISP2_CIF_DUAL_CROP_BASE + 0x00000008)
+#define RKISP2_CIF_DUAL_CROP_M_H_SIZE (RKISP2_CIF_DUAL_CROP_BASE + 0x0000000C)
+#define RKISP2_CIF_DUAL_CROP_M_V_SIZE (RKISP2_CIF_DUAL_CROP_BASE + 0x00000010)
+#define RKISP2_CIF_DUAL_CROP_S_H_OFFS (RKISP2_CIF_DUAL_CROP_BASE + 0x00000014)
+#define RKISP2_CIF_DUAL_CROP_S_V_OFFS (RKISP2_CIF_DUAL_CROP_BASE + 0x00000018)
+#define RKISP2_CIF_DUAL_CROP_S_H_SIZE (RKISP2_CIF_DUAL_CROP_BASE + 0x0000001C)
+#define RKISP2_CIF_DUAL_CROP_S_V_SIZE (RKISP2_CIF_DUAL_CROP_BASE + 0x00000020)
+#define RKISP2_CIF_DUAL_CROP_M_H_OFFS_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x00000024)
+#define RKISP2_CIF_DUAL_CROP_M_V_OFFS_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x00000028)
+#define RKISP2_CIF_DUAL_CROP_M_H_SIZE_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x0000002C)
+#define RKISP2_CIF_DUAL_CROP_M_V_SIZE_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x00000030)
+#define RKISP2_CIF_DUAL_CROP_S_H_OFFS_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x00000034)
+#define RKISP2_CIF_DUAL_CROP_S_V_OFFS_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x00000038)
+#define RKISP2_CIF_DUAL_CROP_S_H_SIZE_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x0000003C)
+#define RKISP2_CIF_DUAL_CROP_S_V_SIZE_SHD (RKISP2_CIF_DUAL_CROP_BASE + 0x00000040)
+
+#define RKISP2_CIF_MRSZ_BASE 0x00000C00
+#define RKISP2_CIF_MRSZ_CTRL (RKISP2_CIF_MRSZ_BASE + 0x00000000)
+#define RKISP2_CIF_MRSZ_SCALE_HY (RKISP2_CIF_MRSZ_BASE + 0x00000004)
+#define RKISP2_CIF_MRSZ_SCALE_HCB (RKISP2_CIF_MRSZ_BASE + 0x00000008)
+#define RKISP2_CIF_MRSZ_SCALE_HCR (RKISP2_CIF_MRSZ_BASE + 0x0000000C)
+#define RKISP2_CIF_MRSZ_SCALE_VY (RKISP2_CIF_MRSZ_BASE + 0x00000010)
+#define RKISP2_CIF_MRSZ_SCALE_VC (RKISP2_CIF_MRSZ_BASE + 0x00000014)
+#define RKISP2_CIF_MRSZ_PHASE_HY (RKISP2_CIF_MRSZ_BASE + 0x00000018)
+#define RKISP2_CIF_MRSZ_PHASE_HC (RKISP2_CIF_MRSZ_BASE + 0x0000001C)
+#define RKISP2_CIF_MRSZ_PHASE_VY (RKISP2_CIF_MRSZ_BASE + 0x00000020)
+#define RKISP2_CIF_MRSZ_PHASE_VC (RKISP2_CIF_MRSZ_BASE + 0x00000024)
+#define RKISP2_CIF_MRSZ_SCALE_LUT_ADDR (RKISP2_CIF_MRSZ_BASE + 0x00000028)
+#define RKISP2_CIF_MRSZ_SCALE_LUT (RKISP2_CIF_MRSZ_BASE + 0x0000002C)
+#define RKISP2_CIF_MRSZ_CTRL_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000030)
+#define RKISP2_CIF_MRSZ_SCALE_HY_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000034)
+#define RKISP2_CIF_MRSZ_SCALE_HCB_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000038)
+#define RKISP2_CIF_MRSZ_SCALE_HCR_SHD (RKISP2_CIF_MRSZ_BASE + 0x0000003C)
+#define RKISP2_CIF_MRSZ_SCALE_VY_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000040)
+#define RKISP2_CIF_MRSZ_SCALE_VC_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000044)
+#define RKISP2_CIF_MRSZ_PHASE_HY_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000048)
+#define RKISP2_CIF_MRSZ_PHASE_HC_SHD (RKISP2_CIF_MRSZ_BASE + 0x0000004C)
+#define RKISP2_CIF_MRSZ_PHASE_VY_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000050)
+#define RKISP2_CIF_MRSZ_PHASE_VC_SHD (RKISP2_CIF_MRSZ_BASE + 0x00000054)
+
+#define RKISP2_CIF_SRSZ_BASE 0x00001000
+#define RKISP2_CIF_SRSZ_CTRL (RKISP2_CIF_SRSZ_BASE + 0x00000000)
+#define RKISP2_CIF_SRSZ_SCALE_HY (RKISP2_CIF_SRSZ_BASE + 0x00000004)
+#define RKISP2_CIF_SRSZ_SCALE_HCB (RKISP2_CIF_SRSZ_BASE + 0x00000008)
+#define RKISP2_CIF_SRSZ_SCALE_HCR (RKISP2_CIF_SRSZ_BASE + 0x0000000C)
+#define RKISP2_CIF_SRSZ_SCALE_VY (RKISP2_CIF_SRSZ_BASE + 0x00000010)
+#define RKISP2_CIF_SRSZ_SCALE_VC (RKISP2_CIF_SRSZ_BASE + 0x00000014)
+#define RKISP2_CIF_SRSZ_PHASE_HY (RKISP2_CIF_SRSZ_BASE + 0x00000018)
+#define RKISP2_CIF_SRSZ_PHASE_HC (RKISP2_CIF_SRSZ_BASE + 0x0000001C)
+#define RKISP2_CIF_SRSZ_PHASE_VY (RKISP2_CIF_SRSZ_BASE + 0x00000020)
+#define RKISP2_CIF_SRSZ_PHASE_VC (RKISP2_CIF_SRSZ_BASE + 0x00000024)
+#define RKISP2_CIF_SRSZ_SCALE_LUT_ADDR (RKISP2_CIF_SRSZ_BASE + 0x00000028)
+#define RKISP2_CIF_SRSZ_SCALE_LUT (RKISP2_CIF_SRSZ_BASE + 0x0000002C)
+#define RKISP2_CIF_SRSZ_CTRL_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000030)
+#define RKISP2_CIF_SRSZ_SCALE_HY_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000034)
+#define RKISP2_CIF_SRSZ_SCALE_HCB_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000038)
+#define RKISP2_CIF_SRSZ_SCALE_HCR_SHD (RKISP2_CIF_SRSZ_BASE + 0x0000003C)
+#define RKISP2_CIF_SRSZ_SCALE_VY_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000040)
+#define RKISP2_CIF_SRSZ_SCALE_VC_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000044)
+#define RKISP2_CIF_SRSZ_PHASE_HY_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000048)
+#define RKISP2_CIF_SRSZ_PHASE_HC_SHD (RKISP2_CIF_SRSZ_BASE + 0x0000004C)
+#define RKISP2_CIF_SRSZ_PHASE_VY_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000050)
+#define RKISP2_CIF_SRSZ_PHASE_VC_SHD (RKISP2_CIF_SRSZ_BASE + 0x00000054)
+
+#define RKISP2_CIF_MI_BASE 0x00001400
+#define RKISP2_CIF_MI_CTRL (RKISP2_CIF_MI_BASE + 0x00000000)
+#define RKISP2_CIF_MI_INIT (RKISP2_CIF_MI_BASE + 0x00000004)
+#define RKISP2_CIF_MI_MP_Y_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x00000008)
+#define RKISP2_CIF_MI_MP_Y_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x0000000C)
+#define RKISP2_CIF_MI_MP_Y_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000010)
+#define RKISP2_CIF_MI_MP_Y_OFFS_CNT_START (RKISP2_CIF_MI_BASE + 0x00000014)
+#define RKISP2_CIF_MI_MP_Y_IRQ_OFFS_INIT (RKISP2_CIF_MI_BASE + 0x00000018)
+#define RKISP2_CIF_MI_MP_CB_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x0000001C)
+#define RKISP2_CIF_MI_MP_CB_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x00000020)
+#define RKISP2_CIF_MI_MP_CB_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000024)
+#define RKISP2_CIF_MI_MP_CB_OFFS_CNT_START (RKISP2_CIF_MI_BASE + 0x00000028)
+#define RKISP2_CIF_MI_MP_CR_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x0000002C)
+#define RKISP2_CIF_MI_MP_CR_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x00000030)
+#define RKISP2_CIF_MI_MP_CR_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000034)
+#define RKISP2_CIF_MI_MP_CR_OFFS_CNT_START (RKISP2_CIF_MI_BASE + 0x00000038)
+#define RKISP2_CIF_MI_SP_Y_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x0000003C)
+#define RKISP2_CIF_MI_SP_Y_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x00000040)
+#define RKISP2_CIF_MI_SP_Y_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000044)
+#define RKISP2_CIF_MI_SP_Y_OFFS_CNT_START (RKISP2_CIF_MI_BASE + 0x00000048)
+#define RKISP2_CIF_MI_SP_Y_LLENGTH (RKISP2_CIF_MI_BASE + 0x0000004C)
+#define RKISP2_CIF_MI_SP_CB_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x00000050)
+#define RKISP2_CIF_MI_SP_CB_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x00000054)
+#define RKISP2_CIF_MI_SP_CB_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000058)
+#define RKISP2_CIF_MI_SP_CB_OFFS_CNT_START (RKISP2_CIF_MI_BASE + 0x0000005C)
+#define RKISP2_CIF_MI_SP_CR_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x00000060)
+#define RKISP2_CIF_MI_SP_CR_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x00000064)
+#define RKISP2_CIF_MI_SP_CR_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000068)
+#define RKISP2_CIF_MI_SP_CR_OFFS_CNT_START (RKISP2_CIF_MI_BASE + 0x0000006C)
+#define RKISP2_CIF_MI_BYTE_CNT (RKISP2_CIF_MI_BASE + 0x00000070)
+#define RKISP2_CIF_MI_CTRL_SHD (RKISP2_CIF_MI_BASE + 0x00000074)
+#define RKISP2_CIF_MI_MP_Y_BASE_AD_SHD (RKISP2_CIF_MI_BASE + 0x00000078)
+#define RKISP2_CIF_MI_MP_Y_SIZE_SHD (RKISP2_CIF_MI_BASE + 0x0000007C)
+#define RKISP2_CIF_MI_MP_Y_OFFS_CNT_SHD (RKISP2_CIF_MI_BASE + 0x00000080)
+#define RKISP2_CIF_MI_MP_Y_IRQ_OFFS_SHD (RKISP2_CIF_MI_BASE + 0x00000084)
+#define RKISP2_CIF_MI_MP_CB_BASE_AD_SHD (RKISP2_CIF_MI_BASE + 0x00000088)
+#define RKISP2_CIF_MI_MP_CB_SIZE_SHD (RKISP2_CIF_MI_BASE + 0x0000008C)
+#define RKISP2_CIF_MI_MP_CB_OFFS_CNT_SHD (RKISP2_CIF_MI_BASE + 0x00000090)
+#define RKISP2_CIF_MI_MP_CR_BASE_AD_SHD (RKISP2_CIF_MI_BASE + 0x00000094)
+#define RKISP2_CIF_MI_MP_CR_SIZE_SHD (RKISP2_CIF_MI_BASE + 0x00000098)
+#define RKISP2_CIF_MI_MP_CR_OFFS_CNT_SHD (RKISP2_CIF_MI_BASE + 0x0000009C)
+#define RKISP2_CIF_MI_SP_Y_BASE_AD_SHD (RKISP2_CIF_MI_BASE + 0x000000A0)
+#define RKISP2_CIF_MI_SP_Y_SIZE_SHD (RKISP2_CIF_MI_BASE + 0x000000A4)
+#define RKISP2_CIF_MI_SP_Y_OFFS_CNT_SHD (RKISP2_CIF_MI_BASE + 0x000000A8)
+#define RKISP2_CIF_MI_SP_CB_BASE_AD_SHD (RKISP2_CIF_MI_BASE + 0x000000B0)
+#define RKISP2_CIF_MI_SP_CB_SIZE_SHD (RKISP2_CIF_MI_BASE + 0x000000B4)
+#define RKISP2_CIF_MI_SP_CB_OFFS_CNT_SHD (RKISP2_CIF_MI_BASE + 0x000000B8)
+#define RKISP2_CIF_MI_SP_CR_BASE_AD_SHD (RKISP2_CIF_MI_BASE + 0x000000BC)
+#define RKISP2_CIF_MI_SP_CR_SIZE_SHD (RKISP2_CIF_MI_BASE + 0x000000C0)
+#define RKISP2_CIF_MI_SP_CR_OFFS_CNT_SHD (RKISP2_CIF_MI_BASE + 0x000000C4)
+#define RKISP2_CIF_MI_DMA_Y_PIC_START_AD (RKISP2_CIF_MI_BASE + 0x000000C8)
+#define RKISP2_CIF_MI_DMA_Y_PIC_WIDTH (RKISP2_CIF_MI_BASE + 0x000000CC)
+#define RKISP2_CIF_MI_DMA_Y_LLENGTH (RKISP2_CIF_MI_BASE + 0x000000D0)
+#define RKISP2_CIF_MI_DMA_Y_PIC_SIZE (RKISP2_CIF_MI_BASE + 0x000000D4)
+#define RKISP2_CIF_MI_DMA_CB_PIC_START_AD (RKISP2_CIF_MI_BASE + 0x000000D8)
+#define RKISP2_CIF_MI_DMA_CR_PIC_START_AD (RKISP2_CIF_MI_BASE + 0x000000E8)
+#define RKISP2_CIF_MI_IMSC (RKISP2_CIF_MI_BASE + 0x000000F8)
+#define RKISP2_CIF_MI_RIS (RKISP2_CIF_MI_BASE + 0x000000FC)
+#define RKISP2_CIF_MI_MIS (RKISP2_CIF_MI_BASE + 0x00000100)
+#define RKISP2_CIF_MI_ICR (RKISP2_CIF_MI_BASE + 0x00000104)
+#define RKISP2_CIF_MI_ISR (RKISP2_CIF_MI_BASE + 0x00000108)
+#define RKISP2_CIF_MI_STATUS (RKISP2_CIF_MI_BASE + 0x0000010C)
+#define RKISP2_CIF_MI_STATUS_CLR (RKISP2_CIF_MI_BASE + 0x00000110)
+#define RKISP2_CIF_MI_SP_Y_PIC_WIDTH (RKISP2_CIF_MI_BASE + 0x00000114)
+#define RKISP2_CIF_MI_SP_Y_PIC_HEIGHT (RKISP2_CIF_MI_BASE + 0x00000118)
+#define RKISP2_CIF_MI_SP_Y_PIC_SIZE (RKISP2_CIF_MI_BASE + 0x0000011C)
+#define RKISP2_CIF_MI_DMA_CTRL (RKISP2_CIF_MI_BASE + 0x00000120)
+#define RKISP2_CIF_MI_DMA_START (RKISP2_CIF_MI_BASE + 0x00000124)
+#define RKISP2_CIF_MI_DMA_STATUS (RKISP2_CIF_MI_BASE + 0x00000128)
+#define RKISP2_CIF_MI_PIXEL_COUNT (RKISP2_CIF_MI_BASE + 0x0000012C)
+#define RKISP2_CIF_MI_MP_Y_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x00000130)
+#define RKISP2_CIF_MI_MP_CB_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x00000134)
+#define RKISP2_CIF_MI_MP_CR_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x00000138)
+#define RKISP2_CIF_MI_SP_Y_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x0000013C)
+#define RKISP2_CIF_MI_SP_CB_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x00000140)
+#define RKISP2_CIF_MI_SP_CR_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x00000144)
+#define RKISP2_CIF_MI_XTD_FORMAT_CTRL (RKISP2_CIF_MI_BASE + 0x00000148)
+#define RKISP2_CIF_MI_MP_HANDSHAKE_0 (RKISP2_CIF_MI_BASE + 0x0000014C)
+#define RKISP2_CIF_MI_MP_Y_LLENGTH (RKISP2_CIF_MI_BASE + 0x00000150)
+#define RKISP2_CIF_MI_OUTPUT_ALIGN_FORMAT (RKISP2_CIF_MI_BASE + 0x0000015C)
+#define RKISP2_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT BIT(0)
+#define RKISP2_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES BIT(1)
+#define RKISP2_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES BIT(4)
+#define RKISP2_CIF_MI_MP_OUTPUT_FIFO_SIZE (RKISP2_CIF_MI_BASE + 0x00000160)
+#define RKISP2_CIF_MI_MP_Y_PIC_WIDTH (RKISP2_CIF_MI_BASE + 0x00000164)
+#define RKISP2_CIF_MI_MP_Y_PIC_HEIGHT (RKISP2_CIF_MI_BASE + 0x00000168)
+#define RKISP2_CIF_MI_MP_Y_PIC_SIZE (RKISP2_CIF_MI_BASE + 0x0000016C)
+#define RKISP2_CIF_MI_CTRL2 (RKISP2_CIF_MI_BASE + 0x00000150)
+#define RKISP2_CIF_MI_RAW0_BASE_AD_INIT (RKISP2_CIF_MI_BASE + 0x00000160)
+#define RKISP2_CIF_MI_RAW0_BASE_AD_INIT2 (RKISP2_CIF_MI_BASE + 0x00000164)
+#define RKISP2_CIF_MI_RAW0_IRQ_OFFS_INIT (RKISP2_CIF_MI_BASE + 0x00000168)
+#define RKISP2_CIF_MI_RAW0_SIZE_INIT (RKISP2_CIF_MI_BASE + 0x0000016c)
+#define RKISP2_CIF_MI_RAW0_OFFS_CNT_INIT (RKISP2_CIF_MI_BASE + 0x00000170)
+#define RKISP2_CIF_MI_RAW0_LENGTH (RKISP2_CIF_MI_BASE + 0x00000174)
+#define RKISP2_CIF_MI_RAW0_OFFS_CNT_START_SHD (RKISP2_CIF_MI_BASE + 0x00000178)
+#define RKISP2_CIF_MI_RAW0_BASE_AS_SHD (RKISP2_CIF_MI_BASE + 0x00000180)
+#define RKISP2_CIF_MI_RAW0_IRQ_OFFS_INI_SHD (RKISP2_CIF_MI_BASE + 0x00000184)
+#define RKISP2_CIF_MI_RAW0_SIZE_INIT_SHD (RKISP2_CIF_MI_BASE + 0x00000188)
+#define RKISP2_CIF_MI_RAW0_OFFS_CNT_INIT_SHD (RKISP2_CIF_MI_BASE + 0x0000018c)
+
+#define RKISP2_CIF_SMIA_BASE 0x00001A00
+#define RKISP2_CIF_SMIA_CTRL (RKISP2_CIF_SMIA_BASE + 0x00000000)
+#define RKISP2_CIF_SMIA_STATUS (RKISP2_CIF_SMIA_BASE + 0x00000004)
+#define RKISP2_CIF_SMIA_IMSC (RKISP2_CIF_SMIA_BASE + 0x00000008)
+#define RKISP2_CIF_SMIA_RIS (RKISP2_CIF_SMIA_BASE + 0x0000000C)
+#define RKISP2_CIF_SMIA_MIS (RKISP2_CIF_SMIA_BASE + 0x00000010)
+#define RKISP2_CIF_SMIA_ICR (RKISP2_CIF_SMIA_BASE + 0x00000014)
+#define RKISP2_CIF_SMIA_ISR (RKISP2_CIF_SMIA_BASE + 0x00000018)
+#define RKISP2_CIF_SMIA_DATA_FORMAT_SEL (RKISP2_CIF_SMIA_BASE + 0x0000001C)
+#define RKISP2_CIF_SMIA_SOF_EMB_DATA_LINES (RKISP2_CIF_SMIA_BASE + 0x00000020)
+#define RKISP2_CIF_SMIA_EMB_HSTART (RKISP2_CIF_SMIA_BASE + 0x00000024)
+#define RKISP2_CIF_SMIA_EMB_HSIZE (RKISP2_CIF_SMIA_BASE + 0x00000028)
+#define RKISP2_CIF_SMIA_EMB_VSTART (RKISP2_CIF_SMIA_BASE + 0x0000002c)
+#define RKISP2_CIF_SMIA_NUM_LINES (RKISP2_CIF_SMIA_BASE + 0x00000030)
+#define RKISP2_CIF_SMIA_EMB_DATA_FIFO (RKISP2_CIF_SMIA_BASE + 0x00000034)
+#define RKISP2_CIF_SMIA_EMB_DATA_WATERMARK (RKISP2_CIF_SMIA_BASE + 0x00000038)
+
+#define RKISP2_CIF_MIPI_BASE 0x00001C00
+#define RKISP2_CIF_MIPI_CTRL (RKISP2_CIF_MIPI_BASE + 0x00000000)
+#define RKISP2_CIF_MIPI_STATUS (RKISP2_CIF_MIPI_BASE + 0x00000004)
+#define RKISP2_CIF_MIPI_IMSC (RKISP2_CIF_MIPI_BASE + 0x00000008)
+#define RKISP2_CIF_MIPI_RIS (RKISP2_CIF_MIPI_BASE + 0x0000000C)
+#define RKISP2_CIF_MIPI_MIS (RKISP2_CIF_MIPI_BASE + 0x00000010)
+#define RKISP2_CIF_MIPI_ICR (RKISP2_CIF_MIPI_BASE + 0x00000014)
+#define RKISP2_CIF_MIPI_ISR (RKISP2_CIF_MIPI_BASE + 0x00000018)
+#define RKISP2_CIF_MIPI_CUR_DATA_ID (RKISP2_CIF_MIPI_BASE + 0x0000001C)
+#define RKISP2_CIF_MIPI_IMG_DATA_SEL (RKISP2_CIF_MIPI_BASE + 0x00000020)
+#define RKISP2_CIF_MIPI_ADD_DATA_SEL_1 (RKISP2_CIF_MIPI_BASE + 0x00000024)
+#define RKISP2_CIF_MIPI_ADD_DATA_SEL_2 (RKISP2_CIF_MIPI_BASE + 0x00000028)
+#define RKISP2_CIF_MIPI_ADD_DATA_SEL_3 (RKISP2_CIF_MIPI_BASE + 0x0000002C)
+#define RKISP2_CIF_MIPI_ADD_DATA_SEL_4 (RKISP2_CIF_MIPI_BASE + 0x00000030)
+#define RKISP2_CIF_MIPI_ADD_DATA_FIFO (RKISP2_CIF_MIPI_BASE + 0x00000034)
+#define RKISP2_CIF_MIPI_FIFO_FILL_LEVEL (RKISP2_CIF_MIPI_BASE + 0x00000038)
+#define RKISP2_CIF_MIPI_COMPRESSED_MODE (RKISP2_CIF_MIPI_BASE + 0x0000003C)
+#define RKISP2_CIF_MIPI_FRAME (RKISP2_CIF_MIPI_BASE + 0x00000040)
+#define RKISP2_CIF_MIPI_GEN_SHORT_DT (RKISP2_CIF_MIPI_BASE + 0x00000044)
+#define RKISP2_CIF_MIPI_GEN_SHORT_8_9 (RKISP2_CIF_MIPI_BASE + 0x00000048)
+#define RKISP2_CIF_MIPI_GEN_SHORT_A_B (RKISP2_CIF_MIPI_BASE + 0x0000004C)
+#define RKISP2_CIF_MIPI_GEN_SHORT_C_D (RKISP2_CIF_MIPI_BASE + 0x00000050)
+#define RKISP2_CIF_MIPI_GEN_SHORT_E_F (RKISP2_CIF_MIPI_BASE + 0x00000054)
+
+#define RKISP2_CIF_ISP_AFM_BASE 0x00002000
+#define RKISP2_CIF_ISP_AFM_CTRL (RKISP2_CIF_ISP_AFM_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_AFM_LT_A (RKISP2_CIF_ISP_AFM_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_AFM_RB_A (RKISP2_CIF_ISP_AFM_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_AFM_LT_B (RKISP2_CIF_ISP_AFM_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_AFM_RB_B (RKISP2_CIF_ISP_AFM_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_AFM_LT_C (RKISP2_CIF_ISP_AFM_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_AFM_RB_C (RKISP2_CIF_ISP_AFM_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_AFM_THRES (RKISP2_CIF_ISP_AFM_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_AFM_VAR_SHIFT (RKISP2_CIF_ISP_AFM_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_AFM_SUM_A (RKISP2_CIF_ISP_AFM_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_AFM_SUM_B (RKISP2_CIF_ISP_AFM_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_AFM_SUM_C (RKISP2_CIF_ISP_AFM_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_AFM_LUM_A (RKISP2_CIF_ISP_AFM_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_AFM_LUM_B (RKISP2_CIF_ISP_AFM_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_AFM_LUM_C (RKISP2_CIF_ISP_AFM_BASE + 0x00000038)
+
+#define RKISP2_CIF_ISP_LSC_BASE 0x00002200
+#define RKISP2_CIF_ISP_LSC_CTRL (RKISP2_CIF_ISP_LSC_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_LSC_R_TABLE_ADDR (RKISP2_CIF_ISP_LSC_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_LSC_GR_TABLE_ADDR (RKISP2_CIF_ISP_LSC_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_LSC_B_TABLE_ADDR (RKISP2_CIF_ISP_LSC_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_LSC_GB_TABLE_ADDR (RKISP2_CIF_ISP_LSC_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_LSC_R_TABLE_DATA (RKISP2_CIF_ISP_LSC_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_LSC_GR_TABLE_DATA (RKISP2_CIF_ISP_LSC_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_LSC_B_TABLE_DATA (RKISP2_CIF_ISP_LSC_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_LSC_GB_TABLE_DATA (RKISP2_CIF_ISP_LSC_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_LSC_SECT_GRAD(v0, v1) (((v0) & 0x0FFF) | (((v1) & 0x0FFF) << 16))
+#define RKISP2_CIF_ISP_LSC_XGRAD(n) (RKISP2_CIF_ISP_LSC_BASE + 0x00000024 + (n) * 4)
+#define RKISP2_CIF_ISP_LSC_YGRAD(n) (RKISP2_CIF_ISP_LSC_BASE + 0x00000034 + (n) * 4)
+#define RKISP2_CIF_ISP_LSC_XSIZE(n) (RKISP2_CIF_ISP_LSC_BASE + 0x00000044 + (n) * 4)
+#define RKISP2_CIF_ISP_LSC_YSIZE(n) (RKISP2_CIF_ISP_LSC_BASE + 0x00000054 + (n) * 4)
+#define RKISP2_CIF_ISP_LSC_XGRAD_01 (RKISP2_CIF_ISP_LSC_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_LSC_XGRAD_23 (RKISP2_CIF_ISP_LSC_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_LSC_XGRAD_45 (RKISP2_CIF_ISP_LSC_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_LSC_XGRAD_67 (RKISP2_CIF_ISP_LSC_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_LSC_YGRAD_01 (RKISP2_CIF_ISP_LSC_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_LSC_YGRAD_23 (RKISP2_CIF_ISP_LSC_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_LSC_YGRAD_45 (RKISP2_CIF_ISP_LSC_BASE + 0x0000003C)
+#define RKISP2_CIF_ISP_LSC_YGRAD_67 (RKISP2_CIF_ISP_LSC_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_LSC_XSIZE_01 (RKISP2_CIF_ISP_LSC_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_LSC_XSIZE_23 (RKISP2_CIF_ISP_LSC_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_LSC_XSIZE_45 (RKISP2_CIF_ISP_LSC_BASE + 0x0000004C)
+#define RKISP2_CIF_ISP_LSC_XSIZE_67 (RKISP2_CIF_ISP_LSC_BASE + 0x00000050)
+#define RKISP2_CIF_ISP_LSC_YSIZE_01 (RKISP2_CIF_ISP_LSC_BASE + 0x00000054)
+#define RKISP2_CIF_ISP_LSC_YSIZE_23 (RKISP2_CIF_ISP_LSC_BASE + 0x00000058)
+#define RKISP2_CIF_ISP_LSC_YSIZE_45 (RKISP2_CIF_ISP_LSC_BASE + 0x0000005C)
+#define RKISP2_CIF_ISP_LSC_YSIZE_67 (RKISP2_CIF_ISP_LSC_BASE + 0x00000060)
+#define RKISP2_CIF_ISP_LSC_TABLE_SEL (RKISP2_CIF_ISP_LSC_BASE + 0x00000064)
+#define RKISP2_CIF_ISP_LSC_STATUS (RKISP2_CIF_ISP_LSC_BASE + 0x00000068)
+
+#define RKISP2_CIF_ISP_IS_BASE 0x00002300
+#define RKISP2_CIF_ISP_IS_CTRL (RKISP2_CIF_ISP_IS_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_IS_RECENTER (RKISP2_CIF_ISP_IS_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_IS_H_OFFS (RKISP2_CIF_ISP_IS_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_IS_V_OFFS (RKISP2_CIF_ISP_IS_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_IS_H_SIZE (RKISP2_CIF_ISP_IS_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_IS_V_SIZE (RKISP2_CIF_ISP_IS_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_IS_MAX_DX (RKISP2_CIF_ISP_IS_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_IS_MAX_DY (RKISP2_CIF_ISP_IS_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_IS_DISPLACE (RKISP2_CIF_ISP_IS_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_IS_H_OFFS_SHD (RKISP2_CIF_ISP_IS_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_IS_V_OFFS_SHD (RKISP2_CIF_ISP_IS_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_IS_H_SIZE_SHD (RKISP2_CIF_ISP_IS_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_IS_V_SIZE_SHD (RKISP2_CIF_ISP_IS_BASE + 0x00000030)
+
+#define RKISP2_CIF_ISP_HIST_BASE_V10 0x00002400
+#define RKISP2_CIF_ISP_HIST_PROP_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000000)
+#define RKISP2_CIF_ISP_HIST_H_OFFS_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000004)
+#define RKISP2_CIF_ISP_HIST_V_OFFS_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000008)
+#define RKISP2_CIF_ISP_HIST_H_SIZE_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000000C)
+#define RKISP2_CIF_ISP_HIST_V_SIZE_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000010)
+#define RKISP2_CIF_ISP_HIST_BIN_0_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000014)
+#define RKISP2_CIF_ISP_HIST_BIN_1_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000018)
+#define RKISP2_CIF_ISP_HIST_BIN_2_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000001C)
+#define RKISP2_CIF_ISP_HIST_BIN_3_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000020)
+#define RKISP2_CIF_ISP_HIST_BIN_4_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000024)
+#define RKISP2_CIF_ISP_HIST_BIN_5_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000028)
+#define RKISP2_CIF_ISP_HIST_BIN_6_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000002C)
+#define RKISP2_CIF_ISP_HIST_BIN_7_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000030)
+#define RKISP2_CIF_ISP_HIST_BIN_8_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000034)
+#define RKISP2_CIF_ISP_HIST_BIN_9_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000038)
+#define RKISP2_CIF_ISP_HIST_BIN_10_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000003C)
+#define RKISP2_CIF_ISP_HIST_BIN_11_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000040)
+#define RKISP2_CIF_ISP_HIST_BIN_12_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000044)
+#define RKISP2_CIF_ISP_HIST_BIN_13_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000048)
+#define RKISP2_CIF_ISP_HIST_BIN_14_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000004C)
+#define RKISP2_CIF_ISP_HIST_BIN_15_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000050)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_00TO30_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000054)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_40TO21_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000058)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_31TO12_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000005C)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_22TO03_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000060)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_13TO43_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000064)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_04TO34_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x00000068)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_44_V10 (RKISP2_CIF_ISP_HIST_BASE_V10 + 0x0000006C)
+
+#define RKISP2_CIF_ISP_FILT_BASE 0x00002500
+#define RKISP2_CIF_ISP_FILT_MODE (RKISP2_CIF_ISP_FILT_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_FILT_THRESH_BL0 (RKISP2_CIF_ISP_FILT_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_FILT_THRESH_BL1 (RKISP2_CIF_ISP_FILT_BASE + 0x0000002c)
+#define RKISP2_CIF_ISP_FILT_THRESH_SH0 (RKISP2_CIF_ISP_FILT_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_FILT_THRESH_SH1 (RKISP2_CIF_ISP_FILT_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_FILT_LUM_WEIGHT (RKISP2_CIF_ISP_FILT_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_FILT_FAC_SH1 (RKISP2_CIF_ISP_FILT_BASE + 0x0000003c)
+#define RKISP2_CIF_ISP_FILT_FAC_SH0 (RKISP2_CIF_ISP_FILT_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_FILT_FAC_MID (RKISP2_CIF_ISP_FILT_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_FILT_FAC_BL0 (RKISP2_CIF_ISP_FILT_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_FILT_FAC_BL1 (RKISP2_CIF_ISP_FILT_BASE + 0x0000004C)
+#define RKISP2_CIF_ISP_FILT_ISP_CAC_CTRL (RKISP2_CIF_ISP_FILT_BASE + 0x00000080)
+#define RKISP2_CIF_ISP_FILT_CAC_COUNT_START (RKISP2_CIF_ISP_FILT_BASE + 0x00000084)
+#define RKISP2_CIF_ISP_FILT_CAC_A (RKISP2_CIF_ISP_FILT_BASE + 0x00000088)
+#define RKISP2_CIF_ISP_FILT_CAC_B (RKISP2_CIF_ISP_FILT_BASE + 0x0000008c)
+#define RKISP2_CIF_ISP_FILT_CAC_C (RKISP2_CIF_ISP_FILT_BASE + 0x00000090)
+#define RKISP2_CIF_ISP_FILT_CAC_X_NORM (RKISP2_CIF_ISP_FILT_BASE + 0x00000094)
+#define RKISP2_CIF_ISP_FILT_CAC_Y_NORM (RKISP2_CIF_ISP_FILT_BASE + 0x00000098)
+#define RKISP2_CIF_ISP_FILT_LU_DIVID (RKISP2_CIF_ISP_FILT_BASE + 0x000000a0)
+#define RKISP2_CIF_ISP_FILT_THGRAD_DIVID0123 (RKISP2_CIF_ISP_FILT_BASE + 0x000000a4)
+#define RKISP2_CIF_ISP_FILT_THGRAD_DIVID4 (RKISP2_CIF_ISP_FILT_BASE + 0x000000a8)
+#define RKISP2_CIF_ISP_FILT_THDIFF_DIVID0123 (RKISP2_CIF_ISP_FILT_BASE + 0x000000ac)
+#define RKISP2_CIF_ISP_FILT_THDIFF_DIVID4 (RKISP2_CIF_ISP_FILT_BASE + 0x000000b0)
+#define RKISP2_CIF_ISP_FILT_THCSC_DIVID0123 (RKISP2_CIF_ISP_FILT_BASE + 0x000000b4)
+#define RKISP2_CIF_ISP_FILT_THCSC_DIVID4 (RKISP2_CIF_ISP_FILT_BASE + 0x000000b8)
+#define RKISP2_CIF_ISP_FILT_THVAR_DIVID01 (RKISP2_CIF_ISP_FILT_BASE + 0x000000bc)
+#define RKISP2_CIF_ISP_FILT_THVAR_DIVID23 (RKISP2_CIF_ISP_FILT_BASE + 0x000000c0)
+#define RKISP2_CIF_ISP_FILT_THVAR_DIVID4 (RKISP2_CIF_ISP_FILT_BASE + 0x000000c4)
+#define RKISP2_CIF_ISP_FILT_TH_GRAD (RKISP2_CIF_ISP_FILT_BASE + 0x000000c8)
+#define RKISP2_CIF_ISP_FILT_TH_DIFF (RKISP2_CIF_ISP_FILT_BASE + 0x000000cc)
+#define RKISP2_CIF_ISP_FILT_TH_CSC (RKISP2_CIF_ISP_FILT_BASE + 0x000000d0)
+#define RKISP2_CIF_ISP_FILT_TH_VAR (RKISP2_CIF_ISP_FILT_BASE + 0x000000d4)
+#define RKISP2_CIF_ISP_FILT_LELEL_SEL (RKISP2_CIF_ISP_FILT_BASE + 0x000000d8)
+#define RKISP2_CIF_ISP_FILT_R_FCT (RKISP2_CIF_ISP_FILT_BASE + 0x000000dc)
+#define RKISP2_CIF_ISP_FILT_B_FCT (RKISP2_CIF_ISP_FILT_BASE + 0x000000e0)
+
+#define RKISP2_CIF_ISP_CAC_BASE 0x00002580
+#define RKISP2_CIF_ISP_CAC_CTRL (RKISP2_CIF_ISP_CAC_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_CAC_COUNT_START (RKISP2_CIF_ISP_CAC_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_CAC_A (RKISP2_CIF_ISP_CAC_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_CAC_B (RKISP2_CIF_ISP_CAC_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_CAC_C (RKISP2_CIF_ISP_CAC_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_X_NORM (RKISP2_CIF_ISP_CAC_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_Y_NORM (RKISP2_CIF_ISP_CAC_BASE + 0x00000018)
+
+#define RKISP2_CIF_ISP_EXP_BASE 0x00002600
+#define RKISP2_CIF_ISP_EXP_CTRL (RKISP2_CIF_ISP_EXP_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_EXP_H_OFFSET_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_EXP_V_OFFSET_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_EXP_H_SIZE_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_EXP_V_SIZE_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_EXP_SIZE_V12 (RKISP2_CIF_ISP_EXP_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_EXP_OFFS_V12 (RKISP2_CIF_ISP_EXP_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_EXP_MEAN_V12 (RKISP2_CIF_ISP_EXP_BASE + 0x0000000c)
+#define RKISP2_CIF_ISP_EXP_MEAN_00_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_EXP_MEAN_10_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_EXP_MEAN_20_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000001c)
+#define RKISP2_CIF_ISP_EXP_MEAN_30_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_EXP_MEAN_40_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_EXP_MEAN_01_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_EXP_MEAN_11_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000002c)
+#define RKISP2_CIF_ISP_EXP_MEAN_21_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_EXP_MEAN_31_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_EXP_MEAN_41_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_EXP_MEAN_02_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000003c)
+#define RKISP2_CIF_ISP_EXP_MEAN_12_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_EXP_MEAN_22_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_EXP_MEAN_32_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_EXP_MEAN_42_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000004c)
+#define RKISP2_CIF_ISP_EXP_MEAN_03_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000050)
+#define RKISP2_CIF_ISP_EXP_MEAN_13_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000054)
+#define RKISP2_CIF_ISP_EXP_MEAN_23_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000058)
+#define RKISP2_CIF_ISP_EXP_MEAN_33_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000005c)
+#define RKISP2_CIF_ISP_EXP_MEAN_43_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000060)
+#define RKISP2_CIF_ISP_EXP_MEAN_04_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000064)
+#define RKISP2_CIF_ISP_EXP_MEAN_14_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000068)
+#define RKISP2_CIF_ISP_EXP_MEAN_24_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x0000006c)
+#define RKISP2_CIF_ISP_EXP_MEAN_34_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000070)
+#define RKISP2_CIF_ISP_EXP_MEAN_44_V10 (RKISP2_CIF_ISP_EXP_BASE + 0x00000074)
+
+#define RKISP2_CIF_ISP_BLS_BASE 0x00002700
+#define RKISP2_CIF_ISP_BLS_CTRL (RKISP2_CIF_ISP_BLS_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_BLS_SAMPLES (RKISP2_CIF_ISP_BLS_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_BLS_H1_START (RKISP2_CIF_ISP_BLS_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_BLS_H1_STOP (RKISP2_CIF_ISP_BLS_BASE + 0x0000000c)
+#define RKISP2_CIF_ISP_BLS_V1_START (RKISP2_CIF_ISP_BLS_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_BLS_V1_STOP (RKISP2_CIF_ISP_BLS_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_BLS_H2_START (RKISP2_CIF_ISP_BLS_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_BLS_H2_STOP (RKISP2_CIF_ISP_BLS_BASE + 0x0000001c)
+#define RKISP2_CIF_ISP_BLS_V2_START (RKISP2_CIF_ISP_BLS_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_BLS_V2_STOP (RKISP2_CIF_ISP_BLS_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_BLS_A_FIXED (RKISP2_CIF_ISP_BLS_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_BLS_B_FIXED (RKISP2_CIF_ISP_BLS_BASE + 0x0000002c)
+#define RKISP2_CIF_ISP_BLS_C_FIXED (RKISP2_CIF_ISP_BLS_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_BLS_D_FIXED (RKISP2_CIF_ISP_BLS_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_BLS_A_MEASURED (RKISP2_CIF_ISP_BLS_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_BLS_B_MEASURED (RKISP2_CIF_ISP_BLS_BASE + 0x0000003c)
+#define RKISP2_CIF_ISP_BLS_C_MEASURED (RKISP2_CIF_ISP_BLS_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_BLS_D_MEASURED (RKISP2_CIF_ISP_BLS_BASE + 0x00000044)
+
+#define RKISP2_CIF_ISP_DPF_BASE 0x00002800
+#define RKISP2_CIF_ISP_DPF_MODE (RKISP2_CIF_ISP_DPF_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_DPF_STRENGTH_R (RKISP2_CIF_ISP_DPF_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_DPF_STRENGTH_G (RKISP2_CIF_ISP_DPF_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_DPF_STRENGTH_B (RKISP2_CIF_ISP_DPF_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_DPF_S_WEIGHT_G_1_4 (RKISP2_CIF_ISP_DPF_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_DPF_S_WEIGHT_G_5_6 (RKISP2_CIF_ISP_DPF_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_DPF_S_WEIGHT_RB_1_4 (RKISP2_CIF_ISP_DPF_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_DPF_S_WEIGHT_RB_5_6 (RKISP2_CIF_ISP_DPF_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_0 (RKISP2_CIF_ISP_DPF_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_1 (RKISP2_CIF_ISP_DPF_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_2 (RKISP2_CIF_ISP_DPF_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_3 (RKISP2_CIF_ISP_DPF_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_4 (RKISP2_CIF_ISP_DPF_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_5 (RKISP2_CIF_ISP_DPF_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_6 (RKISP2_CIF_ISP_DPF_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_7 (RKISP2_CIF_ISP_DPF_BASE + 0x0000003C)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_8 (RKISP2_CIF_ISP_DPF_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_9 (RKISP2_CIF_ISP_DPF_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_10 (RKISP2_CIF_ISP_DPF_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_11 (RKISP2_CIF_ISP_DPF_BASE + 0x0000004C)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_12 (RKISP2_CIF_ISP_DPF_BASE + 0x00000050)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_13 (RKISP2_CIF_ISP_DPF_BASE + 0x00000054)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_14 (RKISP2_CIF_ISP_DPF_BASE + 0x00000058)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_15 (RKISP2_CIF_ISP_DPF_BASE + 0x0000005C)
+#define RKISP2_CIF_ISP_DPF_NULL_COEFF_16 (RKISP2_CIF_ISP_DPF_BASE + 0x00000060)
+#define RKISP2_CIF_ISP_DPF_NF_GAIN_R (RKISP2_CIF_ISP_DPF_BASE + 0x00000064)
+#define RKISP2_CIF_ISP_DPF_NF_GAIN_GR (RKISP2_CIF_ISP_DPF_BASE + 0x00000068)
+#define RKISP2_CIF_ISP_DPF_NF_GAIN_GB (RKISP2_CIF_ISP_DPF_BASE + 0x0000006C)
+#define RKISP2_CIF_ISP_DPF_NF_GAIN_B (RKISP2_CIF_ISP_DPF_BASE + 0x00000070)
+
+#define RKISP2_CIF_ISP_DPCC_BASE 0x00002900
+#define RKISP2_CIF_ISP_DPCC_MODE (RKISP2_CIF_ISP_DPCC_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_DPCC_OUTPUT_MODE (RKISP2_CIF_ISP_DPCC_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_DPCC_SET_USE (RKISP2_CIF_ISP_DPCC_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_DPCC_METHODS_SET_1 (RKISP2_CIF_ISP_DPCC_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_DPCC_METHODS_SET_2 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_DPCC_METHODS_SET_3 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_DPCC_LINE_THRESH_1 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_DPCC_LINE_MAD_FAC_1 (RKISP2_CIF_ISP_DPCC_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_DPCC_PG_FAC_1 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_DPCC_RND_THRESH_1 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_DPCC_RG_FAC_1 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_DPCC_LINE_THRESH_2 (RKISP2_CIF_ISP_DPCC_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_DPCC_LINE_MAD_FAC_2 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_DPCC_PG_FAC_2 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_DPCC_RND_THRESH_2 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_DPCC_RG_FAC_2 (RKISP2_CIF_ISP_DPCC_BASE + 0x0000003C)
+#define RKISP2_CIF_ISP_DPCC_LINE_THRESH_3 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_DPCC_LINE_MAD_FAC_3 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_DPCC_PG_FAC_3 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_DPCC_RND_THRESH_3 (RKISP2_CIF_ISP_DPCC_BASE + 0x0000004C)
+#define RKISP2_CIF_ISP_DPCC_RG_FAC_3 (RKISP2_CIF_ISP_DPCC_BASE + 0x00000050)
+#define RKISP2_CIF_ISP_DPCC_RO_LIMITS (RKISP2_CIF_ISP_DPCC_BASE + 0x00000054)
+#define RKISP2_CIF_ISP_DPCC_RND_OFFS (RKISP2_CIF_ISP_DPCC_BASE + 0x00000058)
+#define RKISP2_CIF_ISP_DPCC_BPT_CTRL (RKISP2_CIF_ISP_DPCC_BASE + 0x0000005C)
+#define RKISP2_CIF_ISP_DPCC_BPT_NUMBER (RKISP2_CIF_ISP_DPCC_BASE + 0x00000060)
+#define RKISP2_CIF_ISP_DPCC_BPT_ADDR (RKISP2_CIF_ISP_DPCC_BASE + 0x00000064)
+#define RKISP2_CIF_ISP_DPCC_BPT_DATA (RKISP2_CIF_ISP_DPCC_BASE + 0x00000068)
+
+#define RKISP2_CIF_ISP_WDR_BASE 0x00002A00
+#define RKISP2_CIF_ISP_WDR_CTRL (RKISP2_CIF_ISP_WDR_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_WDR_CTRL_ENABLE BIT(0)
+#define RKISP2_CIF_ISP_WDR_COLOR_SPACE_SELECT BIT(1)
+#define RKISP2_CIF_ISP_WDR_CR_MAPPING_DISABLE BIT(2)
+#define RKISP2_CIF_ISP_WDR_USE_IREF BIT(3)
+#define RKISP2_CIF_ISP_WDR_USE_Y9_8 BIT(4)
+#define RKISP2_CIF_ISP_WDR_USE_RGB7_8 BIT(5)
+#define RKISP2_CIF_ISP_WDR_DISABLE_TRANSIENT BIT(6)
+#define RKISP2_CIF_ISP_WDR_RGB_FACTOR_MASK GENMASK(11, 8)
+#define RKISP2_CIF_ISP_WDR_RGB_FACTOR_MAX 8U
+#define RKISP2_CIF_ISP_WDR_TONECURVE_1 (RKISP2_CIF_ISP_WDR_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_2 (RKISP2_CIF_ISP_WDR_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_3 (RKISP2_CIF_ISP_WDR_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_4 (RKISP2_CIF_ISP_WDR_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_WDR_TONECURVE(n) (RKISP2_CIF_ISP_WDR_BASE + 0x00000004 + (n) * 4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_0 (RKISP2_CIF_ISP_WDR_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_1 (RKISP2_CIF_ISP_WDR_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_2 (RKISP2_CIF_ISP_WDR_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_3 (RKISP2_CIF_ISP_WDR_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM(n) (RKISP2_CIF_ISP_WDR_BASE + 0x00000014 + (n) * 4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_4 (RKISP2_CIF_ISP_WDR_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_5 (RKISP2_CIF_ISP_WDR_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_6 (RKISP2_CIF_ISP_WDR_BASE + 0x0000002C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_7 (RKISP2_CIF_ISP_WDR_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_8 (RKISP2_CIF_ISP_WDR_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_9 (RKISP2_CIF_ISP_WDR_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_10 (RKISP2_CIF_ISP_WDR_BASE + 0x0000003C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_11 (RKISP2_CIF_ISP_WDR_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_12 (RKISP2_CIF_ISP_WDR_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_13 (RKISP2_CIF_ISP_WDR_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_14 (RKISP2_CIF_ISP_WDR_BASE + 0x0000004C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_15 (RKISP2_CIF_ISP_WDR_BASE + 0x00000050)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_16 (RKISP2_CIF_ISP_WDR_BASE + 0x00000054)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_17 (RKISP2_CIF_ISP_WDR_BASE + 0x00000058)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_18 (RKISP2_CIF_ISP_WDR_BASE + 0x0000005C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_19 (RKISP2_CIF_ISP_WDR_BASE + 0x00000060)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_20 (RKISP2_CIF_ISP_WDR_BASE + 0x00000064)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_21 (RKISP2_CIF_ISP_WDR_BASE + 0x00000068)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_22 (RKISP2_CIF_ISP_WDR_BASE + 0x0000006C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_23 (RKISP2_CIF_ISP_WDR_BASE + 0x00000070)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_24 (RKISP2_CIF_ISP_WDR_BASE + 0x00000074)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_25 (RKISP2_CIF_ISP_WDR_BASE + 0x00000078)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_26 (RKISP2_CIF_ISP_WDR_BASE + 0x0000007C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_27 (RKISP2_CIF_ISP_WDR_BASE + 0x00000080)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_28 (RKISP2_CIF_ISP_WDR_BASE + 0x00000084)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_29 (RKISP2_CIF_ISP_WDR_BASE + 0x00000088)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_30 (RKISP2_CIF_ISP_WDR_BASE + 0x0000008C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_31 (RKISP2_CIF_ISP_WDR_BASE + 0x00000090)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_32 (RKISP2_CIF_ISP_WDR_BASE + 0x00000094)
+#define RKISP2_CIF_ISP_WDR_OFFSET (RKISP2_CIF_ISP_WDR_BASE + 0x00000098)
+#define RKISP2_CIF_ISP_WDR_RGB_OFFSET_MASK GENMASK(11, 0)
+#define RKISP2_CIF_ISP_WDR_LUM_OFFSET_MASK GENMASK(27, 16)
+#define RKISP2_CIF_ISP_WDR_DELTAMIN (RKISP2_CIF_ISP_WDR_BASE + 0x0000009C)
+#define RKISP2_CIF_ISP_WDR_DMIN_THRESH_MASK GENMASK(11, 0)
+#define RKISP2_CIF_ISP_WDR_DMIN_STRENGTH_MASK GENMASK(20, 16)
+#define RKISP2_CIF_ISP_WDR_DMIN_STRENGTH_MAX 16U
+#define RKISP2_CIF_ISP_WDR_TONE_CURVE_YM_MASK GENMASK(12, 0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_1_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000A0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_2_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000A4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_3_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000A8)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_4_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000AC)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_0_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000B0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_1_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000B4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_2_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000B8)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_3_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000BC)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_4_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000C0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_5_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000C4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_6_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000C8)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_7_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000CC)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_8_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000D0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_9_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000D4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_10_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000D8)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_11_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000DC)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_12_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000E0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_13_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000E4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_14_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000E8)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_15_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000EC)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_16_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000F0)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_17_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000F4)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_18_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000F8)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_19_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x000000FC)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_20_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000100)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_21_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000104)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_22_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000108)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_23_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x0000010C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_24_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000110)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_25_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000114)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_26_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000118)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_27_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x0000011C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_28_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000120)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_29_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000124)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_30_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000128)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_31_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x0000012C)
+#define RKISP2_CIF_ISP_WDR_TONECURVE_YM_32_SHD (RKISP2_CIF_ISP_WDR_BASE + 0x00000130)
+
+#define RKISP2_CIF_ISP_RKWDR_CTRL0 (RKISP2_CIF_ISP_WDR_BASE + 0x00000150)
+#define RKISP2_CIF_ISP_RKWDR_CTRL1 (RKISP2_CIF_ISP_WDR_BASE + 0x00000154)
+#define RKISP2_CIF_ISP_RKWDR_BLKOFF0 (RKISP2_CIF_ISP_WDR_BASE + 0x00000158)
+#define RKISP2_CIF_ISP_RKWDR_AVGCLIP (RKISP2_CIF_ISP_WDR_BASE + 0x0000015c)
+#define RKISP2_CIF_ISP_RKWDR_COE_0 (RKISP2_CIF_ISP_WDR_BASE + 0x00000160)
+#define RKISP2_CIF_ISP_RKWDR_COE_1 (RKISP2_CIF_ISP_WDR_BASE + 0x00000164)
+#define RKISP2_CIF_ISP_RKWDR_COE_2 (RKISP2_CIF_ISP_WDR_BASE + 0x00000168)
+#define RKISP2_CIF_ISP_RKWDR_COE_OFF (RKISP2_CIF_ISP_WDR_BASE + 0x0000016c)
+#define RKISP2_CIF_ISP_RKWDR_OVERL (RKISP2_CIF_ISP_WDR_BASE + 0x00000170)
+#define RKISP2_CIF_ISP_RKWDR_BLKOFF1 (RKISP2_CIF_ISP_WDR_BASE + 0x00000174)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW0_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x00000180)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW0_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x00000184)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW1_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x00000188)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW1_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x0000018c)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW2_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x00000190)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW2_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x00000194)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW3_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x00000198)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW3_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x0000019c)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW4_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x000001a0)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW4_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x000001a4)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW5_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x000001a8)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW5_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x000001ac)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW6_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x000001b0)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW6_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x000001b4)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW7_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x000001b8)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW7_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x000001bc)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW8_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x000001c0)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW8_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x000001c4)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW9_0TO3 (RKISP2_CIF_ISP_WDR_BASE + 0x000001c8)
+#define RKISP2_CIF_ISP_RKWDR_BLKMEAN8_ROW9_4TO7 (RKISP2_CIF_ISP_WDR_BASE + 0x000001cc)
+
+#define RKISP2_CIF_ISP_COMPAND_BASE 0x00003200
+#define RKISP2_CIF_ISP_COMPAND_CTRL (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_COMPAND_CTRL_EXPAND_ENABLE BIT(0)
+#define RKISP2_CIF_ISP_COMPAND_CTRL_COMPRESS_ENABLE BIT(1)
+#define RKISP2_CIF_ISP_COMPAND_CTRL_BLS_ENABLE BIT(3)
+#define RKISP2_CIF_ISP_COMPAND_EXPAND_PX_N(n) (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000014 + (n) * 4)
+#define RKISP2_CIF_ISP_COMPAND_COMPRESS_PX_N(n) (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000040 + (n) * 4)
+#define RKISP2_CIF_ISP_COMPAND_EXPAND_Y_ADDR (RKISP2_CIF_ISP_COMPAND_BASE + 0x0000006C)
+#define RKISP2_CIF_ISP_COMPAND_EXPAND_Y_WRITE_DATA (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000070)
+#define RKISP2_CIF_ISP_COMPAND_COMPRESS_Y_ADDR (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000074)
+#define RKISP2_CIF_ISP_COMPAND_COMPRESS_Y_WRITE_DATA (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000078)
+#define RKISP2_CIF_ISP_COMPAND_EXPAND_X_ADDR (RKISP2_CIF_ISP_COMPAND_BASE + 0x0000007C)
+#define RKISP2_CIF_ISP_COMPAND_EXPAND_X_WRITE_DATA (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000080)
+#define RKISP2_CIF_ISP_COMPAND_COMPRESS_X_ADDR (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000084)
+#define RKISP2_CIF_ISP_COMPAND_COMPRESS_X_WRITE_DATA (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000088)
+#define RKISP2_CIF_ISP_COMPAND_BLS_A_FIXED (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_COMPAND_BLS_B_FIXED (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_COMPAND_BLS_C_FIXED (RKISP2_CIF_ISP_COMPAND_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_COMPAND_BLS_D_FIXED (RKISP2_CIF_ISP_COMPAND_BASE + 0x00000010)
+
+#define RKISP2_CIF_ISP_HIST_BASE_V12 0x00002C00
+#define RKISP2_CIF_ISP_HIST_CTRL_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x00000000)
+#define RKISP2_CIF_ISP_HIST_SIZE_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x00000004)
+#define RKISP2_CIF_ISP_HIST_OFFS_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x00000008)
+#define RKISP2_CIF_ISP_HIST_DBG1_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x0000000C)
+#define RKISP2_CIF_ISP_HIST_DBG2_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x0000001C)
+#define RKISP2_CIF_ISP_HIST_DBG3_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x0000002C)
+#define RKISP2_CIF_ISP_HIST_WEIGHT_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x0000003C)
+#define RKISP2_CIF_ISP_HIST_BIN_V12 (RKISP2_CIF_ISP_HIST_BASE_V12 + 0x00000120)
+
+#define RKISP2_CIF_ISP_VSM_BASE 0x00002F00
+#define RKISP2_CIF_ISP_VSM_MODE (RKISP2_CIF_ISP_VSM_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_VSM_H_OFFS (RKISP2_CIF_ISP_VSM_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_VSM_V_OFFS (RKISP2_CIF_ISP_VSM_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_VSM_H_SIZE (RKISP2_CIF_ISP_VSM_BASE + 0x0000000C)
+#define RKISP2_CIF_ISP_VSM_V_SIZE (RKISP2_CIF_ISP_VSM_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_VSM_H_SEGMENTS (RKISP2_CIF_ISP_VSM_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_VSM_V_SEGMENTS (RKISP2_CIF_ISP_VSM_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_VSM_DELTA_H (RKISP2_CIF_ISP_VSM_BASE + 0x0000001C)
+#define RKISP2_CIF_ISP_VSM_DELTA_V (RKISP2_CIF_ISP_VSM_BASE + 0x00000020)
+
+#define RKISP2_CIF_ISP_CSI0_BASE 0x00007000
+#define RKISP2_CIF_ISP_CSI0_CTRL0 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000000)
+#define RKISP2_CIF_ISP_CSI0_CTRL1 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000004)
+#define RKISP2_CIF_ISP_CSI0_CTRL2 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000008)
+#define RKISP2_CIF_ISP_CSI0_CSI2_RESETN (RKISP2_CIF_ISP_CSI0_BASE + 0x00000010)
+#define RKISP2_CIF_ISP_CSI0_PHY_STATE_RO (RKISP2_CIF_ISP_CSI0_BASE + 0x00000014)
+#define RKISP2_CIF_ISP_CSI0_DATA_IDS_1 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000018)
+#define RKISP2_CIF_ISP_CSI0_DATA_IDS_2 (RKISP2_CIF_ISP_CSI0_BASE + 0x0000001c)
+#define RKISP2_CIF_ISP_CSI0_ERR1 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000020)
+#define RKISP2_CIF_ISP_CSI0_ERR2 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000024)
+#define RKISP2_CIF_ISP_CSI0_ERR3 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000028)
+#define RKISP2_CIF_ISP_CSI0_MASK1 (RKISP2_CIF_ISP_CSI0_BASE + 0x0000002c)
+#define RKISP2_CIF_ISP_CSI0_MASK2 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000030)
+#define RKISP2_CIF_ISP_CSI0_MASK3 (RKISP2_CIF_ISP_CSI0_BASE + 0x00000034)
+#define RKISP2_CIF_ISP_CSI0_SET_HEARDER (RKISP2_CIF_ISP_CSI0_BASE + 0x00000038)
+#define RKISP2_CIF_ISP_CSI0_CUR_HEADER_RO (RKISP2_CIF_ISP_CSI0_BASE + 0x0000003c)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_CTRL (RKISP2_CIF_ISP_CSI0_BASE + 0x00000040)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_LINECNT_RO (RKISP2_CIF_ISP_CSI0_BASE + 0x00000044)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_PIC_SIZE (RKISP2_CIF_ISP_CSI0_BASE + 0x00000048)
+#define RKISP2_CIF_ISP_CSI0_DMATX0_PIC_OFF (RKISP2_CIF_ISP_CSI0_BASE + 0x0000004c)
+#define RKISP2_CIF_ISP_CSI0_FRAME_NUM_RO (RKISP2_CIF_ISP_CSI0_BASE + 0x00000070)
+#define RKISP2_CIF_ISP_CSI0_ISP_LINECNT_RO (RKISP2_CIF_ISP_CSI0_BASE + 0x00000074)
+#define RKISP2_CIF_ISP_CSI0_TX_IBUF_STATUS_RO (RKISP2_CIF_ISP_CSI0_BASE + 0x00000078)
+#define RKISP2_CIF_ISP_CSI0_VERSION (RKISP2_CIF_ISP_CSI0_BASE + 0x0000007c)
+
+#endif /* _RKISP2_REGS_H */
diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h
index b2d2a71f7baf..2575bbef032b 100644
--- a/include/uapi/linux/rkisp1-config.h
+++ b/include/uapi/linux/rkisp1-config.h
@@ -207,6 +207,7 @@ enum rkisp1_cif_isp_version {
RKISP1_V12,
RKISP1_V13,
RKISP1_V_IMX8MP,
+ RKISP1_V30,
};
enum rkisp1_cif_isp_histogram_mode {
diff --git a/include/uapi/linux/rkisp2-config.h b/include/uapi/linux/rkisp2-config.h
new file mode 100644
index 000000000000..ce8093db5998
--- /dev/null
+++ b/include/uapi/linux/rkisp2-config.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: ((GPL-2.0-or-later WITH Linux-syscall-note) OR MIT) */
+/*
+ * Rockchip ISP2 userspace API
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ */
+
+#ifndef _UAPI_RKISP2_CONFIG_H
+#define _UAPI_RKISP2_CONFIG_H
+
+/**
+ * enum rkisp2_isp_version - ISP variants
+ *
+ * @RKISP3_V0: Used at least in RK3588
+ */
+enum rkisp2_isp_version {
+ RKISP3_V0 = 30,
+};
+
+#endif /* _UAPI_RKISP2_CONFIG_H */
--
2.47.2
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [RFC PATCH 4/5] media: rkisp2: Add parameters output video node
2026-04-24 17:58 [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588 Paul Elder
` (2 preceding siblings ...)
2026-04-24 17:58 ` [RFC PATCH 3/5] media: rockchip: rkisp2: Add rkisp2 driver Paul Elder
@ 2026-04-24 17:58 ` Paul Elder
2026-04-24 17:58 ` [RFC PATCH 5/5] media: rkisp2: Add statistics capture " Paul Elder
4 siblings, 0 replies; 8+ messages in thread
From: Paul Elder @ 2026-04-24 17:58 UTC (permalink / raw)
To: laurent.pinchart
Cc: Paul Elder, michael.riesch, xuhf, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel
Implement support for setting parameters on the ISP by queueing
parameter buffers to rkisp2.
Support for the following parameters is added:
- BLS (black level subtraction)
- AWB gains (color gains)
- CSM (color space conversion)
- CCM (color correction matrix)
- GOC (gamma out correction)
- LSC (lens shading correction)
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
---
.../media/platform/rockchip/rkisp2/Makefile | 3 +-
.../platform/rockchip/rkisp2/rkisp2-common.h | 50 ++
.../platform/rockchip/rkisp2/rkisp2-dev.c | 15 +
.../platform/rockchip/rkisp2/rkisp2-isp.c | 11 +-
.../platform/rockchip/rkisp2/rkisp2-params.c | 775 ++++++++++++++++++
.../rockchip/rkisp2/rkisp2-regs-v3x.h | 31 +
drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
include/uapi/linux/rkisp2-config.h | 314 +++++++
include/uapi/linux/videodev2.h | 3 +
9 files changed, 1201 insertions(+), 2 deletions(-)
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
diff --git a/drivers/media/platform/rockchip/rkisp2/Makefile b/drivers/media/platform/rockchip/rkisp2/Makefile
index 9a9d7b5233c4..0fa014afcae4 100644
--- a/drivers/media/platform/rockchip/rkisp2/Makefile
+++ b/drivers/media/platform/rockchip/rkisp2/Makefile
@@ -4,7 +4,8 @@ rockchip-isp2-y := rkisp2-capture.o \
rkisp2-common.o \
rkisp2-dev.o \
rkisp2-dmarx.o \
- rkisp2-isp.o
+ rkisp2-isp.o \
+ rkisp2-params.o
rockchip-isp2-$(CONFIG_DEBUG_FS) += rkisp2-debug.o
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
index e08adfec2c50..7473dae6c525 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
@@ -22,6 +22,7 @@
#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
+#include <media/v4l2-isp.h>
#include <media/videobuf2-v4l2.h>
#include "rkisp2-regs.h"
@@ -88,6 +89,7 @@ enum rkisp2_fmt_raw_pat_type {
/* enum for the isp pads */
enum rkisp2_isp_pad {
RKISP2_ISP_PAD_SINK_VIDEO,
+ RKISP2_ISP_PAD_SINK_PARAMS,
RKISP2_ISP_PAD_SOURCE_VIDEO,
RKISP2_ISP_PAD_MAX
};
@@ -182,6 +184,26 @@ struct rkisp2_buffer {
dma_addr_t buff_addr[VIDEO_MAX_PLANES];
};
+/*
+ * struct rkisp2_params_buffer - A container for the vb2 buffers used by the
+ * params video device
+ *
+ * @vb: vb2 buffer
+ * @queue: entry of the buffer in the queue
+ * @cfg: scratch buffer used for caching the ISP configuration parameters
+ */
+struct rkisp2_params_buffer {
+ struct vb2_v4l2_buffer vb;
+ struct list_head queue;
+ struct v4l2_isp_params_buffer *cfg;
+};
+
+static inline struct rkisp2_params_buffer *
+to_rkisp2_params_buffer(struct vb2_v4l2_buffer *vbuf)
+{
+ return container_of(vbuf, struct rkisp2_params_buffer, vb);
+}
+
/*
* struct rkisp2_dummy_buffer - A buffer to write the next frame to in case
* there are no vb2 buffers available.
@@ -292,6 +314,25 @@ struct rkisp2_capture {
struct v4l2_rect crop;
};
+/*
+ * struct rkisp2_params - ISP input parameters device
+ *
+ * @vnode: video node
+ * @rkisp2: pointer to the rkisp2 device
+ * @buf_lock: locks the buffer list 'params'
+ * @params: queue of rkisp2_buffer
+ * @raw_type: the bayer pattern on the isp video sink pad
+ */
+struct rkisp2_params {
+ struct rkisp2_vdev_node vnode;
+ struct rkisp2_device *rkisp2;
+
+ spinlock_t buf_lock; /* locks the buffers list 'params' */
+ struct list_head params;
+
+ enum rkisp2_fmt_raw_pat_type raw_type;
+};
+
struct rkisp2_debug {
struct dentry *debugfs_dir;
unsigned long data_loss;
@@ -324,6 +365,7 @@ struct rkisp2_debug {
* @resizer_devs: resizer sub-devices
* @capture_devs: capture devices
* @dmarx: ISP memory read device
+ * @params: ISP parameters metadata output device
* @pipe: media pipeline
* @stream_lock: serializes {start/stop}_streaming callbacks between the capture devices.
* @debug: debug params to be exposed on debugfs
@@ -345,6 +387,7 @@ struct rkisp2_device {
struct rkisp2_isp isp;
struct rkisp2_capture capture_devs[2];
struct rkisp2_dmarx dmarx;
+ struct rkisp2_params params;
struct media_pipeline pipe;
struct mutex stream_lock; /* serialize {start/stop}_streaming cb between capture devices */
struct rkisp2_debug debug;
@@ -434,6 +477,7 @@ irqreturn_t rkisp2_isp_isr(int irq, void *ctx);
irqreturn_t rkisp2_capture_isr(int irq, void *ctx);
irqreturn_t rkisp2_mipi_isr(int irq, void *ctx);
void rkisp2_dmarx_isr(struct rkisp2_device *rkisp2, u32 status);
+void rkisp2_params_isr(struct rkisp2_params *params);
/* register/unregisters functions of the entities */
int rkisp2_capture_devs_register(struct rkisp2_device *rkisp2);
@@ -444,6 +488,12 @@ void rkisp2_isp_unregister(struct rkisp2_device *rkisp2);
int rkisp2_dmarx_register(struct rkisp2_device *rkisp2);
void rkisp2_dmarx_unregister(struct rkisp2_device *rkisp2);
+int rkisp2_params_register(struct rkisp2_device *rkisp2);
+void rkisp2_params_unregister(struct rkisp2_device *rkisp2);
+void rkisp2_params_pre_configure(struct rkisp2_params *params,
+ enum rkisp2_fmt_raw_pat_type bayer_pat);
+void rkisp2_params_post_configure(struct rkisp2_params *params);
+
#if IS_ENABLED(CONFIG_DEBUG_FS)
void rkisp2_debug_init(struct rkisp2_device *rkisp2);
void rkisp2_debug_cleanup(struct rkisp2_device *rkisp2);
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
index 4d5c41850395..0356ef2a1cf1 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
@@ -129,11 +129,22 @@ static int rkisp2_create_links(struct rkisp2_device *rkisp2)
return ret;
}
+ /* params links */
+ ret = media_create_pad_link(&rkisp2->params.vnode.vdev.entity, 0,
+ &rkisp2->isp.sd.entity,
+ RKISP2_ISP_PAD_SINK_PARAMS,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (ret)
+ return ret;
+
+
return 0;
}
static void rkisp2_entities_unregister(struct rkisp2_device *rkisp2)
{
+ rkisp2_params_unregister(rkisp2);
rkisp2_dmarx_unregister(rkisp2);
rkisp2_capture_devs_unregister(rkisp2);
rkisp2_isp_unregister(rkisp2);
@@ -155,6 +166,10 @@ static int rkisp2_entities_register(struct rkisp2_device *rkisp2)
if (ret)
goto error;
+ ret = rkisp2_params_register(rkisp2);
+ if (ret)
+ goto error;
+
ret = rkisp2_create_links(rkisp2);
if (ret)
goto error;
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
index 4140139da3c1..0967d5772bc9 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
@@ -120,6 +120,10 @@ static int rkisp2_config_isp(struct rkisp2_isp *isp,
RKISP2_CIF_ISP_PIC_SIZE_ERROR;
rkisp2_write(rkisp2, RKISP2_CIF_ISP_IMSC, irq_mask);
+ src_frm = v4l2_subdev_state_get_format(sd_state,
+ RKISP2_ISP_PAD_SOURCE_VIDEO);
+ rkisp2_params_pre_configure(&rkisp2->params, sink_fmt->bayer_pat);
+
isp->sink_fmt = sink_fmt;
return 0;
@@ -248,6 +252,8 @@ static int rkisp2_isp_start(struct rkisp2_isp *isp,
RKISP2_CIF_ISP_CTRL_ISP_INFORM_ENABLE | RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
rkisp2_write(rkisp2, RKISP2_CIF_ISP_CTRL, val);
+ rkisp2_params_post_configure(&rkisp2->params);
+
return 0;
}
@@ -804,6 +810,7 @@ int rkisp2_isp_register(struct rkisp2_device *rkisp2)
pads[RKISP2_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK |
MEDIA_PAD_FL_MUST_CONNECT;
+ pads[RKISP2_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
pads[RKISP2_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&sd->entity, RKISP2_ISP_PAD_MAX, pads);
@@ -893,8 +900,10 @@ irqreturn_t rkisp2_isp_isr(int irq, void *ctx)
rkisp2->debug.data_loss++;
}
- if (status & RKISP2_CIF_ISP_FRAME)
+ if (status & RKISP2_CIF_ISP_FRAME) {
rkisp2->debug.complete_frames++;
+ rkisp2_params_isr(&rkisp2->params);
+ }
rkisp2_write(rkisp2, RKISP2_CIF_ISP_ICR, status);
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
new file mode 100644
index 000000000000..b7b27d0e90c6
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
@@ -0,0 +1,775 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - Params subdevice
+ *
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/build_bug.h>
+#include <linux/math.h>
+#include <linux/string.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-isp.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-vmalloc.h>
+
+#include "rkisp2-common.h"
+
+#define RKISP2_PARAMS_DEV_NAME RKISP2_DRIVER_NAME "_params"
+
+#define RKISP2_PARAMS_BLOCK_INFO(block, data) \
+ [RKISP2_PARAMS_BLOCK_ ## block] = { \
+ .size = sizeof(struct rkisp2_params_ ## data ), \
+ }
+
+#define RKISP2_PARAMS_BLOCK_HANDLER_INFO(block, handler_postfix, prio_postfix) \
+ [RKISP2_PARAMS_BLOCK_ ## block] = { \
+ .handler = rkisp2_params_ ## handler_postfix,\
+ .priority = RKISP2_PARAMS_CONFIG_PRIO_ ## prio_postfix, \
+ }
+
+union rkisp2_params_block {
+ const struct v4l2_isp_params_block_header *header;
+ const struct rkisp2_params_bls *bls;
+ const struct rkisp2_params_awb_gains *awb_gains;
+ const struct rkisp2_params_csm *csm;
+ const struct rkisp2_params_ccm *ccm;
+ const struct rkisp2_params_goc *goc;
+ const struct rkisp2_params_lsc *lsc;
+ const __u8 *data;
+};
+
+static void rkisp2_params_bls(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_awb_gains(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_csm(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_ccm(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_goc(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_lsc(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+
+typedef void (*rkisp2_params_handler)(struct rkisp2_params *params,
+ const union rkisp2_params_block block);
+
+enum rkisp2_params_configure_priority {
+ RKISP2_PARAMS_CONFIG_PRIO_NONE = 0,
+ RKISP2_PARAMS_CONFIG_PRIO_PRE,
+ RKISP2_PARAMS_CONFIG_PRIO_POST,
+};
+
+struct rkisp2_params_block_handler_info {
+ rkisp2_params_handler handler;
+ enum rkisp2_params_configure_priority priority;
+};
+
+static const struct rkisp2_params_block_handler_info
+rkisp2_params_handlers[] = {
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(BLS, bls, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(AWB_GAINS, awb_gains, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(CSM, csm, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(CCM, ccm, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(GOC, goc, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(LSC, lsc, POST),
+};
+
+static const struct v4l2_isp_params_block_type_info
+rkisp2_params_block_types_info[] = {
+ RKISP2_PARAMS_BLOCK_INFO(BLS, bls),
+ RKISP2_PARAMS_BLOCK_INFO(AWB_GAINS, awb_gains),
+ RKISP2_PARAMS_BLOCK_INFO(CSM, csm),
+ RKISP2_PARAMS_BLOCK_INFO(CCM, ccm),
+ RKISP2_PARAMS_BLOCK_INFO(GOC, goc),
+ RKISP2_PARAMS_BLOCK_INFO(LSC, lsc),
+};
+
+static_assert(ARRAY_SIZE(rkisp2_params_handlers) ==
+ ARRAY_SIZE(rkisp2_params_block_types_info));
+
+static inline void
+rkisp2_param_set_bits(struct rkisp2_params *params, u32 reg, u32 bit_mask)
+{
+ u32 val;
+
+ val = rkisp2_read(params->rkisp2, reg);
+ rkisp2_write(params->rkisp2, reg, val | bit_mask);
+}
+
+static inline void
+rkisp2_param_clear_bits(struct rkisp2_params *params, u32 reg, u32 bit_mask)
+{
+ u32 val;
+
+ val = rkisp2_read(params->rkisp2, reg);
+ rkisp2_write(params->rkisp2, reg, val & ~bit_mask);
+}
+
+static void rkisp2_params_bls(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_bls *arg = block.bls;
+ u32 control;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP_BLS_CTRL, ISP_BLS_ENA | ISP_BLS_BLS1_EN);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ control = ISP_BLS_ENA;
+
+ if (!arg->enable_auto) {
+ /* TODO plumb BLS1 */
+
+ rkisp2_write(params->rkisp2, ISP_BLS_A_FIXED, arg->bls_fixed_val.a);
+ rkisp2_write(params->rkisp2, ISP_BLS_B_FIXED, arg->bls_fixed_val.b);
+ rkisp2_write(params->rkisp2, ISP_BLS_C_FIXED, arg->bls_fixed_val.c);
+ rkisp2_write(params->rkisp2, ISP_BLS_D_FIXED, arg->bls_fixed_val.d);
+
+ /* Set fixed mode */
+ rkisp2_param_clear_bits(params, ISP_BLS_CTRL,
+ ISP_BLS_MODE_MEASURED);
+ return;
+ }
+
+ if (arg->enabled_windows & BIT(1)) {
+ rkisp2_write(params->rkisp2, ISP_BLS_H2_START,
+ arg->bls_window2.h_offs);
+ rkisp2_write(params->rkisp2, ISP_BLS_H2_STOP,
+ arg->bls_window2.h_size);
+ rkisp2_write(params->rkisp2, ISP_BLS_V2_START,
+ arg->bls_window2.v_offs);
+ rkisp2_write(params->rkisp2, ISP_BLS_V2_STOP,
+ arg->bls_window2.v_size);
+ control |= ISP_BLS_WINDOW_2;
+ }
+
+ if (arg->enabled_windows & BIT(0)) {
+ rkisp2_write(params->rkisp2, ISP_BLS_H1_START,
+ arg->bls_window1.h_offs);
+ rkisp2_write(params->rkisp2, ISP_BLS_H1_STOP,
+ arg->bls_window1.h_size);
+ rkisp2_write(params->rkisp2, ISP_BLS_V1_START,
+ arg->bls_window1.v_offs);
+ rkisp2_write(params->rkisp2, ISP_BLS_V1_STOP,
+ arg->bls_window1.v_size);
+ control |= ISP_BLS_WINDOW_1;
+ }
+
+ rkisp2_write(params->rkisp2, ISP_BLS_SAMPLES,
+ arg->bls_samples);
+
+ control |= ISP_BLS_MODE_MEASURED;
+ rkisp2_write(params->rkisp2, ISP_BLS_CTRL, control);
+}
+
+static void rkisp2_params_awb_gains(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_awb_gains *arg = block.awb_gains;
+ unsigned int i;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, RKISP2_CIF_ISP_CTRL,
+ RKISP2_CIF_ISP_CTRL_ISP_AWB_ENA);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(arg->gains); i++) {
+ rkisp2_write(params->rkisp2, ISP21_AWB_GAIN0_G + i * 8,
+ arg->gains[i].gr << 16 | arg->gains[i].gb);
+ rkisp2_write(params->rkisp2, ISP21_AWB_GAIN0_RB + i * 8,
+ arg->gains[i].r << 16 | arg->gains[i].b);
+ }
+
+ rkisp2_param_set_bits(params, RKISP2_CIF_ISP_CTRL,
+ RKISP2_CIF_ISP_CTRL_ISP_AWB_ENA);
+}
+
+static void rkisp2_params_csm_reset(struct rkisp2_params *params)
+{
+ /* Write back the default values. */
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_0, 0x80);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_1, 0);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_2, 0);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_3, 0);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_4, 0x80);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_5, 0);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_6, 0);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_7, 0);
+ rkisp2_write(params->rkisp2, RKISP2_CIF_ISP_CC_COEFF_8, 0x80);
+}
+
+static void rkisp2_params_csm(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_csm *arg = block.csm;
+ unsigned int i, j, k = 0;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_params_csm_reset(params);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ for (i = 0; i < 3; i++)
+ for (j = 0; j < 3; j++)
+ rkisp2_write(params->rkisp2,
+ RKISP2_CIF_ISP_CC_COEFF_0 + 4 * k++,
+ arg->coeff[i][j]);
+}
+
+static void rkisp2_params_ccm(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_ccm *arg = block.ccm;
+ unsigned int i;
+ u32 control = 0;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP_CCM_CTRL, ISP_CCM_EN);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ for (i = 0; i < 3; i++) {
+ rkisp2_write(params->rkisp2, ISP_CCM_COEFF0_R + 8 * i,
+ ISP3X_CCM_COEFF(arg->coeff[i][0], arg->coeff[i][1]));
+ rkisp2_write(params->rkisp2, ISP_CCM_COEFF1_R + 8 * i,
+ ISP3X_CCM_COEFF(arg->coeff[i][2], arg->offset[i]));
+ }
+
+ rkisp2_write(params->rkisp2, ISP_CCM_COEFF0_Y,
+ ISP3X_CCM_COEFF(arg->y_coeff[0], arg->y_coeff[1]));
+ rkisp2_write(params->rkisp2, ISP_CCM_COEFF1_Y, arg->y_coeff[2]);
+
+ for (i = 0; i < 8; i++)
+ rkisp2_write(params->rkisp2, ISP_CCM_ALP_Y0 + 4 * i,
+ ISP3X_CCM_COEFF(arg->alp[2 * i], arg->alp[2 * i + 1]));
+ rkisp2_write(params->rkisp2, ISP_CCM_ALP_Y8, arg->alp[16]);
+
+ rkisp2_write(params->rkisp2, ISP_CCM_BOUND_BIT, arg->inflection_point);
+
+ if (!arg->high_y_alpha_adj_en)
+ control = ISP3X_CCM_HIGHY_ADJ_DIS;
+ control |= ISP_CCM_EN;
+ rkisp2_write(params->rkisp2, ISP_CCM_CTRL, control);
+}
+
+static void rkisp2_params_goc(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_goc *arg = block.goc;
+ unsigned int i;
+ u32 control = 0;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP3X_GAMMA_OUT_CTRL,
+ ISP3X_GAMMA_OUT_CTRL_EN);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ for (i = 0; i < RKISP2_ISP_GAMMA_OUT_MAX_SEGMENTS >> 1; i++)
+ rkisp2_write(params->rkisp2,
+ ISP3X_GAMMA_OUT_Y0 + 4 * i,
+ ISP3X_GAMMA_OUT_SAMPLE(arg->gamma_y[2 * i],
+ arg->gamma_y[2 * i + 1]));
+
+ rkisp2_write(params->rkisp2, ISP3X_GAMMA_OUT_Y24,
+ arg->gamma_y[RKISP2_ISP_GAMMA_OUT_MAX_SEGMENTS - 1]);
+
+ rkisp2_write(params->rkisp2, ISP3X_GAMMA_OUT_OFFSET, arg->offset);
+
+ if (arg->mode == RKISP2_ISP_GOC_MODE_EQUIDISTANT)
+ control = ISP3X_GAMMA_OUT_CTRL_MODE_EQUIDISTANT;
+ if (arg->mode == RKISP2_ISP_GOC_SEGMENTS_48)
+ control |= ISP3X_GAMMA_OUT_CTRL_SEGMENTS_48;
+ control |= ISP3X_GAMMA_OUT_CTRL_EN;
+ rkisp2_write(params->rkisp2, ISP3X_GAMMA_OUT_CTRL, control);
+}
+
+static void rkisp2_params_lsc(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_lsc *arg = block.lsc;
+ struct rkisp2_device *rkisp2 = params->rkisp2;
+ u32 sram_addr;
+ u32 data;
+ unsigned int i, j, table_i;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP3X_LSC_CTRL, ISP3X_LSC_CTRL_EN);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ if (arg->set_active_table_when == RKISP2_ISP_LSC_SET_ACTIVE_TABLE_BEFORE)
+ rkisp2_write(rkisp2, ISP3X_LSC_TABLE_SEL, arg->active_table ? 1 : 0);
+
+ /*
+ * - No need to disable the lsc before writing the table
+ * - Table 0 starts at 0, table 1 starts at 153.
+ * - TABLE_SEL selects which table is active, but programming the tables
+ * is done by just writing to the right address.
+ * - The address automatically increments, so no need to increment it.
+ */
+
+ for (table_i = 0; table_i < 2; table_i++) {
+ if (!arg->write_table[table_i])
+ continue;
+
+ sram_addr = table_i * 153;
+
+ rkisp2_write(rkisp2, ISP3X_LSC_R_TABLE_ADDR, sram_addr);
+ rkisp2_write(rkisp2, ISP3X_LSC_GR_TABLE_ADDR, sram_addr);
+ rkisp2_write(rkisp2, ISP3X_LSC_B_TABLE_ADDR, sram_addr);
+ rkisp2_write(rkisp2, ISP3X_LSC_GB_TABLE_ADDR, sram_addr);
+
+ /* Program data tables (table size is 9 * 17 = 153) */
+ for (i = 0; i < RKISP2_ISP_LSC_SAMPLES_MAX; i++) {
+ const __u16 *r_row = arg->r_data_tbl[table_i][i];
+ const __u16 *gr_row = arg->gr_data_tbl[table_i][i];
+ const __u16 *gb_row = arg->gb_data_tbl[table_i][i];
+ const __u16 *b_row = arg->b_data_tbl[table_i][i];
+
+ /*
+ * 17 sectors with 2 values in one DWORD = 9
+ * DWORDs (2nd value of last DWORD unused)
+ */
+ for (j = 0; j < RKISP2_ISP_LSC_SAMPLES_MAX / 2; j++) {
+ rkisp2_write(rkisp2, ISP3X_LSC_R_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(r_row[2 * j], r_row[2 * j + 1]));
+ rkisp2_write(rkisp2, ISP3X_LSC_GR_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(gr_row[2 * j], gr_row[2 * j + 1]));
+ rkisp2_write(rkisp2, ISP3X_LSC_GB_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(gb_row[2 * j], gb_row[2 * j + 1]));
+ rkisp2_write(rkisp2, ISP3X_LSC_B_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(b_row[2 * j], b_row[2 * j + 1]));
+ }
+
+ rkisp2_write(rkisp2, ISP3X_LSC_R_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(r_row[2 * j], 0));
+ rkisp2_write(rkisp2, ISP3X_LSC_GR_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(gr_row[2 * j], 0));
+ rkisp2_write(rkisp2, ISP3X_LSC_GB_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(gb_row[2 * j], 0));
+ rkisp2_write(rkisp2, ISP3X_LSC_B_TABLE_DATA,
+ ISP3X_LSC_TABLE_DATA(b_row[2 * j], 0));
+
+ }
+ }
+
+ /* Program grid sizes and interpolation gradients */
+ for (i = 0; i < RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX / 2; i++) {
+ /* program x size tables */
+ data = ISP3X_LSC_SECT_SIZE(arg->x_sizes[i * 2],
+ arg->x_sizes[i * 2 + 1]);
+ rkisp2_write(rkisp2, ISP3X_LSC_XSIZE(i), data);
+
+ /* program x grad tables */
+ data = ISP3X_LSC_GRAD_SIZE(arg->x_grads[i * 2],
+ arg->x_grads[i * 2 + 1]);
+ rkisp2_write(rkisp2, ISP3X_LSC_XGRAD(i), data);
+
+ /* program y size tables */
+ data = ISP3X_LSC_SECT_SIZE(arg->y_sizes[i * 2],
+ arg->y_sizes[i * 2 + 1]);
+ rkisp2_write(rkisp2, ISP3X_LSC_YSIZE(i), data);
+
+ /* program y grad tables */
+ data = ISP3X_LSC_GRAD_SIZE(arg->y_grads[i * 2],
+ arg->y_grads[i * 2 + 1]);
+ rkisp2_write(rkisp2, ISP3X_LSC_YGRAD(i), data);
+ }
+
+ rkisp2_write(rkisp2, ISP3X_LSC_TABLE_SEL, arg->active_table ? 1 : 0);
+
+ data = 0;
+ if (arg->window_mode)
+ data |= ISP3X_LSC_SECTOR_16X16;
+ /* TODO plumb the rest of the ctrl fields */
+ data |= ISP3X_LSC_CTRL_EN;
+
+ rkisp2_param_set_bits(params, ISP3X_LSC_CTRL, data);
+}
+
+static void rkisp2_params_configure(struct rkisp2_params *params,
+ struct rkisp2_params_buffer *buf,
+ enum rkisp2_params_configure_priority prio)
+{
+ struct v4l2_isp_params_buffer *cfg;
+ const struct rkisp2_params_block_handler_info *info;
+ size_t block_offset = 0;
+ size_t max_offset;
+
+ buf->vb.sequence = params->rkisp2->isp.frame_sequence + 1;
+ cfg = buf->cfg;
+
+ max_offset = cfg->data_size;
+
+ /* Walk the list of parameter blocks and process them. */
+ while (max_offset && block_offset < max_offset) {
+ union rkisp2_params_block block;
+
+ /* \todo Check if we want to avoid this copy */
+ block.data = &cfg->data[block_offset];
+
+ block_offset += block.header->size;
+
+ info = &rkisp2_params_handlers[block.header->type];
+
+ if (prio != RKISP2_PARAMS_CONFIG_PRIO_NONE &&
+ prio != info->priority)
+ continue;
+
+ info->handler(params, block);
+ }
+
+ /* update shadow register immediately */
+ rkisp2_param_set_bits(params, RKISP2_CIF_ISP_CTRL,
+ RKISP2_CIF_ISP_CTRL_ISP_CFG_UPD);
+
+ if (prio == RKISP2_PARAMS_CONFIG_PRIO_NONE)
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+}
+
+void rkisp2_params_isr(struct rkisp2_params *params)
+{
+ struct rkisp2_params_buffer *buf;
+
+ spin_lock(¶ms->buf_lock);
+ buf = list_first_entry_or_null(¶ms->params,
+ struct rkisp2_params_buffer, queue);
+ if (buf)
+ list_del(&buf->queue);
+ spin_unlock(¶ms->buf_lock);
+
+ if (!buf)
+ return;
+
+ rkisp2_params_configure(params, buf, RKISP2_PARAMS_CONFIG_PRIO_NONE);
+}
+
+void rkisp2_params_pre_configure(struct rkisp2_params *params,
+ enum rkisp2_fmt_raw_pat_type bayer_pat)
+{
+ struct rkisp2_params_buffer *buf;
+
+ params->raw_type = bayer_pat;
+
+ spin_lock_irq(¶ms->buf_lock);
+ buf = list_first_entry_or_null(¶ms->params,
+ struct rkisp2_params_buffer, queue);
+ spin_unlock_irq(¶ms->buf_lock);
+
+ if (!buf)
+ return;
+
+ rkisp2_params_configure(params, buf, RKISP2_PARAMS_CONFIG_PRIO_PRE);
+}
+
+void rkisp2_params_post_configure(struct rkisp2_params *params)
+{
+ struct rkisp2_params_buffer *buf;
+
+ spin_lock_irq(¶ms->buf_lock);
+ buf = list_first_entry_or_null(¶ms->params,
+ struct rkisp2_params_buffer, queue);
+ if (buf)
+ list_del(&buf->queue);
+ spin_unlock_irq(¶ms->buf_lock);
+
+ if (!buf)
+ return;
+
+ rkisp2_params_configure(params, buf, RKISP2_PARAMS_CONFIG_PRIO_POST);
+}
+
+/*** V4L2 ***/
+
+static int rkisp2_params_enum_fmt_meta_out(struct file *file, void *fh,
+ struct v4l2_fmtdesc *f)
+{
+ if (f->index)
+ return -EINVAL;
+
+ if (f->mbus_code && f->mbus_code != MEDIA_BUS_FMT_METADATA_FIXED)
+ return -EINVAL;
+
+ f->pixelformat = V4L2_META_FMT_RKISP2_PARAMS;
+
+ return 0;
+}
+
+static int rkisp2_params_g_fmt_meta_out(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+
+ static const struct v4l2_meta_format mfmt = {
+ .dataformat = V4L2_META_FMT_RKISP2_PARAMS,
+ .buffersize = v4l2_isp_params_buffer_size(RKISP2_PARAMS_MAX_SIZE),
+ };
+
+ f->fmt.meta = mfmt;
+
+ return 0;
+}
+
+static int rkisp2_params_querycap(struct file *file,
+ void *priv, struct v4l2_capability *cap)
+{
+ struct video_device *vdev = video_devdata(file);
+
+ strscpy(cap->driver, RKISP2_DRIVER_NAME, sizeof(cap->driver));
+ strscpy(cap->card, vdev->name, sizeof(cap->card));
+ strscpy(cap->bus_info, RKISP2_BUS_INFO, sizeof(cap->bus_info));
+
+ return 0;
+}
+
+/* ISP params video device IOCTLs */
+static const struct v4l2_ioctl_ops rkisp2_params_ioctl = {
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_enum_fmt_meta_out = rkisp2_params_enum_fmt_meta_out,
+ .vidioc_g_fmt_meta_out = rkisp2_params_g_fmt_meta_out,
+ .vidioc_s_fmt_meta_out = rkisp2_params_g_fmt_meta_out,
+ .vidioc_try_fmt_meta_out = rkisp2_params_g_fmt_meta_out,
+ .vidioc_querycap = rkisp2_params_querycap,
+};
+
+static int rkisp2_params_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ /* \todo num_buffers? */
+
+ *num_planes = 1;
+
+ sizes[0] = v4l2_isp_params_buffer_size(RKISP2_PARAMS_MAX_SIZE);
+
+ return 0;
+}
+
+static int rkisp2_params_vb2_buf_init(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_params_buffer *params_buf = to_rkisp2_params_buffer(vbuf);
+
+ params_buf->cfg = kvmalloc(v4l2_isp_params_buffer_size(RKISP2_PARAMS_MAX_SIZE),
+ GFP_KERNEL);
+ if (!params_buf->cfg)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void rkisp2_params_vb2_buf_cleanup(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_params_buffer *params_buf = to_rkisp2_params_buffer(vbuf);
+
+ kvfree(params_buf->cfg);
+ params_buf->cfg = NULL;
+}
+
+static void rkisp2_params_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_params_buffer *params_buf = to_rkisp2_params_buffer(vbuf);
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct rkisp2_params *params = vq->drv_priv;
+
+ spin_lock_irq(¶ms->buf_lock);
+ list_add_tail(¶ms_buf->queue, ¶ms->params);
+ spin_unlock_irq(¶ms->buf_lock);
+}
+
+static int rkisp2_params_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ struct rkisp2_params *params = vb->vb2_queue->drv_priv;
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_params_buffer *params_buf = to_rkisp2_params_buffer(vbuf);
+ struct v4l2_isp_params_buffer *cfg = vb2_plane_vaddr(&vbuf->vb2_buf, 0);
+ size_t payload_size = vb2_get_plane_payload(vb, 0);
+ int ret;
+
+ ret = v4l2_isp_params_validate_buffer_size(params->rkisp2->dev, vb,
+ v4l2_isp_params_buffer_size(RKISP2_PARAMS_MAX_SIZE));
+ if (ret)
+ return ret;
+
+ /*
+ * Copy the parameters buffer to the internal scratch buffer to avoid
+ * userspace modifying the buffer content while the driver processes it.
+ */
+ memcpy(params_buf->cfg, cfg, payload_size);
+
+ return v4l2_isp_params_validate_buffer(params->rkisp2->dev, vb, cfg,
+ rkisp2_params_block_types_info,
+ ARRAY_SIZE(rkisp2_params_block_types_info));
+}
+
+static void rkisp2_params_vb2_stop_streaming(struct vb2_queue *vq)
+{
+ struct rkisp2_params *params = vq->drv_priv;
+ struct rkisp2_params_buffer *buf;
+ LIST_HEAD(tmp_list);
+
+ /*
+ * we first move the buffers into a local list 'tmp_list'
+ * and then we can iterate it and call vb2_buffer_done
+ * without holding the lock
+ */
+ spin_lock_irq(¶ms->buf_lock);
+ list_splice_init(¶ms->params, &tmp_list);
+ spin_unlock_irq(¶ms->buf_lock);
+
+ list_for_each_entry(buf, &tmp_list, queue)
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+}
+
+static const struct vb2_ops rkisp2_params_vb2_ops = {
+ .queue_setup = rkisp2_params_vb2_queue_setup,
+ .buf_init = rkisp2_params_vb2_buf_init,
+ .buf_cleanup = rkisp2_params_vb2_buf_cleanup,
+ .buf_queue = rkisp2_params_vb2_buf_queue,
+ .buf_prepare = rkisp2_params_vb2_buf_prepare,
+ .stop_streaming = rkisp2_params_vb2_stop_streaming,
+};
+
+static const struct v4l2_file_operations rkisp2_params_fops = {
+ .mmap = vb2_fop_mmap,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vb2_fop_poll,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release
+};
+
+static int rkisp2_params_link_validate(struct media_link *link)
+{
+ /* \todo implement this */
+ return 0;
+}
+
+static const struct media_entity_operations rkisp2_params_media_ops = {
+ .link_validate = rkisp2_params_link_validate,
+};
+
+static int rkisp2_params_init_vb2_queue(struct vb2_queue *q,
+ struct rkisp2_params *params)
+{
+ struct rkisp2_vdev_node *node;
+
+ node = container_of(q, struct rkisp2_vdev_node, buf_queue);
+
+ q->type = V4L2_BUF_TYPE_META_OUTPUT;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->drv_priv = params;
+ q->ops = &rkisp2_params_vb2_ops;
+ q->mem_ops = &vb2_vmalloc_memops;
+ q->buf_struct_size = sizeof(struct rkisp2_params_buffer);
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->vlock;
+
+ return vb2_queue_init(q);
+}
+
+int rkisp2_params_register(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_params *params = &rkisp2->params;
+ struct rkisp2_vdev_node *node = ¶ms->vnode;
+ struct video_device *vdev = &node->vdev;
+ int ret;
+
+ params->rkisp2 = rkisp2;
+ mutex_init(&node->vlock);
+ INIT_LIST_HEAD(¶ms->params);
+ spin_lock_init(¶ms->buf_lock);
+
+ strscpy(vdev->name, RKISP2_PARAMS_DEV_NAME, sizeof(vdev->name));
+
+ video_set_drvdata(vdev, params);
+ vdev->ioctl_ops = &rkisp2_params_ioctl;
+ vdev->fops = &rkisp2_params_fops;
+ vdev->release = video_device_release_empty;
+ /*
+ * Provide a mutex to v4l2 core. It will be used
+ * to protect all fops and v4l2 ioctls.
+ */
+ vdev->lock = &node->vlock;
+ vdev->v4l2_dev = &rkisp2->v4l2_dev;
+ vdev->queue = &node->buf_queue;
+ vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_META_OUTPUT;
+ vdev->entity.ops = &rkisp2_params_media_ops;
+ vdev->vfl_dir = VFL_DIR_TX;
+ ret = rkisp2_params_init_vb2_queue(vdev->queue, params);
+ if (ret)
+ goto err_media;
+
+ video_set_drvdata(vdev, params);
+
+ node->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret)
+ goto err_media;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(rkisp2->dev,
+ "failed to register %s, ret=%d\n", vdev->name, ret);
+ return ret;
+ }
+
+ return 0;
+
+err_media:
+ media_entity_cleanup(&vdev->entity);
+ mutex_destroy(&node->vlock);
+ return ret;
+}
+
+void rkisp2_params_unregister(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_params *params = &rkisp2->params;
+ struct rkisp2_vdev_node *node = ¶ms->vnode;
+ struct video_device *vdev = &node->vdev;
+
+ if (!video_is_registered(vdev))
+ return;
+
+ vb2_video_unregister_device(vdev);
+ media_entity_cleanup(&vdev->entity);
+ mutex_destroy(&node->vlock);
+}
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
index bb79d08d206f..d27d9a48887e 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
@@ -881,6 +881,15 @@
#define ISP3X_LSC_YSIZE_CD (ISP3X_LSC_BASE + 0x000A8)
#define ISP3X_LSC_YSIZE_EF (ISP3X_LSC_BASE + 0x000AC)
+#define ISP3X_LSC_XGRAD(n) (n < 4 ? (ISP3X_LSC_XGRAD_01 + (n) * 4) : \
+ (ISP3X_LSC_XGRAD_89 + ((n) - 4) * 4))
+#define ISP3X_LSC_YGRAD(n) (n < 4 ? (ISP3X_LSC_YGRAD_01 + (n) * 4) : \
+ (ISP3X_LSC_YGRAD_89 + ((n) - 4) * 4))
+#define ISP3X_LSC_XSIZE(n) (n < 4 ? (ISP3X_LSC_XSIZE_01 + (n) * 4) : \
+ (ISP3X_LSC_XSIZE_89 + ((n) - 4) * 4))
+#define ISP3X_LSC_YSIZE(n) (n < 4 ? (ISP3X_LSC_YSIZE_01 + (n) * 4) : \
+ (ISP3X_LSC_YSIZE_89 + ((n) - 4) * 4))
+
#define ISP3X_DEBAYER_BASE 0x00002500
#define ISP3X_DEBAYER_CONTROL (ISP3X_DEBAYER_BASE + 0x00000)
#define ISP3X_DEBAYER_G_INTERP (ISP3X_DEBAYER_BASE + 0x00004)
@@ -3235,6 +3244,12 @@
#define ISP33_IIR_WR_ID(x) (((x) & 0x3f) << 16)
#define ISP33_IIR_WR_CLEAR BIT(24)
+/* GAMMA_OUT */
+#define ISP3X_GAMMA_OUT_CTRL_EN BIT(0)
+#define ISP3X_GAMMA_OUT_CTRL_MODE_EQUIDISTANT BIT(1)
+#define ISP3X_GAMMA_OUT_CTRL_SEGMENTS_48 BIT(2)
+#define ISP3X_GAMMA_OUT_SAMPLE(a, b) (((a) & 0xfff) | (((b) & 0xfff) << 16))
+
/* HDRTMO */
/* HDRDRC */
@@ -3264,6 +3279,7 @@
#define ISP3X_DPCC_WORKING BIT(30)
/* CCM */
+#define ISP3X_CCM_COEFF(a, b) ((a & 0x7ff) | (b << 16))
#define ISP3X_CCM_HIGHY_ADJ_DIS BIT(1)
#define ISP32_CCM_ENH_ADJ_EN BIT(2)
#define ISP32_CCM_ASYM_ADJ_EN BIT(3)
@@ -3288,6 +3304,21 @@
#define ISP3X_LSC_TABLE_ADDRESS_0 0
#define ISP3X_LSC_TABLE_ADDRESS_153 153
+#define ISP3X_LSC_CTRL_EN BIT(0)
+
+#define ISP3X_LSC_ACTIVE_TABLE BIT(1)
+
+#define ISP3X_LSC_LUT_EN BIT(1)
+#define ISP3X_LSC_SECTOR_16X16 BIT(2)
+#define ISP3X_LSC_PRE_RD_ST_MODE BIT(4)
+
+#define ISP3X_LSC_TABLE_DATA(v0, v1) \
+ (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
+#define ISP3X_LSC_SECT_SIZE(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
+#define ISP3X_LSC_GRAD_SIZE(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
+
#define ISP3X_LSC_LUT_EN BIT(1)
#define ISP3X_LSC_SECTOR_16X16 BIT(2)
#define ISP3X_LSC_PRE_RD_ST_MODE BIT(4)
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index a2b650f4ec3c..470e5b84ed15 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1467,6 +1467,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_META_FMT_RK_ISP1_PARAMS: descr = "Rockchip ISP1 3A Parameters"; break;
case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A Statistics"; break;
case V4L2_META_FMT_RK_ISP1_EXT_PARAMS: descr = "Rockchip ISP1 Ext 3A Params"; break;
+ case V4L2_META_FMT_RKISP2_PARAMS: descr = "Rockchip ISP2 3A Parameters"; break;
case V4L2_META_FMT_C3ISP_PARAMS: descr = "Amlogic C3 ISP Parameters"; break;
case V4L2_META_FMT_C3ISP_STATS: descr = "Amlogic C3 ISP Statistics"; break;
case V4L2_META_FMT_MALI_C55_PARAMS: descr = "ARM Mali-C55 ISP Parameters"; break;
diff --git a/include/uapi/linux/rkisp2-config.h b/include/uapi/linux/rkisp2-config.h
index ce8093db5998..0e42dbf2c9f2 100644
--- a/include/uapi/linux/rkisp2-config.h
+++ b/include/uapi/linux/rkisp2-config.h
@@ -8,6 +8,18 @@
#ifndef _UAPI_RKISP2_CONFIG_H
#define _UAPI_RKISP2_CONFIG_H
+#ifdef __KERNEL__
+#include <linux/build_bug.h>
+#endif /* __KERNEL__ */
+#include <linux/types.h>
+
+#include <linux/media/v4l2-isp.h>
+
+#define RKISP2_ISP_GAMMA_OUT_MAX_SEGMENTS 49
+
+#define RKISP2_ISP_LSC_SAMPLES_MAX 17
+#define RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX 16
+
/**
* enum rkisp2_isp_version - ISP variants
*
@@ -17,4 +29,306 @@ enum rkisp2_isp_version {
RKISP3_V0 = 30,
};
+/* See enum rkisp2_isp_goc_segments for logarithmic segment sizes */
+enum rkisp2_isp_goc_mode {
+ RKISP2_ISP_GOC_MODE_LOGARITHMIC,
+ RKISP2_ISP_GOC_MODE_EQUIDISTANT
+};
+
+/*
+ * The segments are:
+ * 1 x8, 2 x4, 4 x4, 8 x4, 16 x4, 32 x4, 64 x4, 128 x4, 256 x4, 512 x4
+ * In 48-segment mode, the last group of 512 x4 becomes 256 x8
+ */
+enum rkisp2_isp_goc_segments {
+ RKISP2_ISP_GOC_SEGMENTS_44,
+ RKISP2_ISP_GOC_SEGMENTS_48
+};
+
+enum rkisp2_isp_lsc_config {
+ RKISP2_ISP_LSC_CONFIG_8X8,
+ RKISP2_ISP_LSC_CONFIG_16X16
+};
+
+enum rkisp2_isp_set_active_table_when {
+ RKISP2_ISP_LSC_SET_ACTIVE_TABLE_AFTER,
+ RKISP2_ISP_LSC_SET_ACTIVE_TABLE_BEFORE,
+};
+
+/*---------- Parameters ------------*/
+
+/**
+ * enum rkisp2_params_block_type - RkISP1 extensible params block type
+ *
+ * @RKISP2_PARAMS_BLOCK_BLS: Black level subtraction
+ * @RKISP2_PARAMS_BLOCK_AWB_GAINS: AWB gains
+ * @RKISP2_PARAMS_BLOCK_CSM: Color conversion coefficients (in the ISP block)
+ * @RKISP2_PARAMS_BLOCK_CCM: Color correction matrix (in the CCM block)
+ * @RKISP2_PARAMS_BLOCK_GOC: Gamma out correction
+ * @RKISP2_PARAMS_BLOCK_LSC: Lens shading correction
+ * */
+enum rkisp2_params_block_type {
+ RKISP2_PARAMS_BLOCK_BLS,
+ RKISP2_PARAMS_BLOCK_AWB_GAINS,
+ RKISP2_PARAMS_BLOCK_CSM,
+ RKISP2_PARAMS_BLOCK_CCM,
+ RKISP2_PARAMS_BLOCK_GOC,
+ RKISP2_PARAMS_BLOCK_LSC,
+};
+
+/**
+ * struct rkisp2_isp_window - measurement window.
+ *
+ * Measurements are calculated per window inside the frame.
+ * This struct represents a window for a measurement.
+ *
+ * @h_offs: the horizontal offset of the window from the left of the frame in pixels.
+ * @v_offs: the vertical offset of the window from the top of the frame in pixels.
+ * @h_size: the horizontal size of the window in pixels
+ * @v_size: the vertical size of the window in pixels.
+ */
+struct rkisp2_isp_window {
+ __u16 h_offs;
+ __u16 v_offs;
+ __u16 h_size;
+ __u16 v_size;
+};
+
+/**
+ * struct rkisp2_isp_bls_fixed_val - BLS fixed subtraction values
+ *
+ * These are signed 13-bit (-4096 to +4095).
+ *
+ * @a: Fixed black level value for Bayer channel 0
+ * @b: Fixed black level value for Bayer channel 1
+ * @c: Fixed black level value for Bayer channel 2
+ * @d: Fixed black level value for Bayer channel 3
+ */
+struct rkisp2_isp_bls_fixed_val {
+ __s16 a;
+ __s16 b;
+ __s16 c;
+ __s16 d;
+};
+
+/**
+ * struct rkisp2_isp_awb_gains - Auto white balance gain in the ISP block
+ *
+ * All fields in this struct are 16 bit, where:
+ * 0x100h = 1, unsigned integer value, range 0 to 63 with 8 bit fractional part.
+ *
+ * This leaves the upper two msb unaccounted for; it is unknown if these are
+ * unused or misdocumented.
+ *
+ * TODO investigate the upper two bits
+ *
+ * @r: gain value for red component.
+ * @gr: gain value for green component in red line.
+ * @b: gain value for blue component.
+ * @gb: gain value for green component in blue line.
+ */
+struct rkisp2_isp_awb_gains {
+ __u16 r;
+ __u16 gr;
+ __u16 b;
+ __u16 gb;
+};
+
+/**
+ * struct rkisp2_params_bls - RkISP2 params BLS config
+ *
+ * RkISP2 parameters Black Level Subtraction configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_BLS`.
+ *
+ * TODO Check if auto-mode and window selection is for both blocks or just for
+ * one block (it might be the same as 2.x)
+ *
+ * @header: The RkISP2 parameters block header
+ * @enable_auto: Automatic mode activated means that the measured values
+ * are subtracted. Otherwise the fixed subtraction
+ * values will be subtracted.
+ * @enabled_windows: enabled window (bit 0 for window 1, bit 1 for window 2)
+ * @bls_window1: Measurement window 1 size
+ * @bls_window2: Measurement window 2 size
+ * @bls_samples: Set amount of measured pixels for each Bayer position
+ * (A, B, C and D) to 2^bls_samples. (TODO needs confirmation)
+ * @bls_fixed_val: Black Level Subtraction fixed values for the BLS module at
+ * the front of the pipeline
+ * @bls1_fixed_val: Black Level Subtraction fixed values for the BLS module after
+ * bayer noise reduction
+ */
+struct rkisp2_params_bls {
+ struct v4l2_isp_params_block_header header;
+ __u8 enable_auto;
+ __u8 enabled_windows;
+ struct rkisp2_isp_window bls_window1;
+ struct rkisp2_isp_window bls_window2;
+ __u8 bls_samples;
+ struct rkisp2_isp_bls_fixed_val bls_fixed_val;
+ struct rkisp2_isp_bls_fixed_val bls1_fixed_val;
+} __attribute__((aligned(8)));
+
+/**
+ * struct rkisp2_params_awb_gains - RKISP2 params AWB gains config
+ *
+ * RkISP2 parameters auto white balance gains configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_AWB_GAINS`.
+ *
+ * TODO investigate what the different blocks mean
+ *
+ * Block 0 is equivalent to the awb gains block on 2.x, but blocks 1 and
+ * 2 do not exist on 2.x.
+ *
+ * @header: The RkISP2 parameters block header
+ * @gains: Gains configuration for block i
+ */
+struct rkisp2_params_awb_gains {
+ struct v4l2_isp_params_block_header header;
+ struct rkisp2_isp_awb_gains gains[3];
+} __attribute__((aligned(8)));
+
+/**
+ * struct rkisp2_params_csm - Configuration used by Color Space Conversion
+ *
+ * RkISP2 parameters histogram configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_CSM`.
+ *
+ * @header: The RkISP2 parameters block header
+ * @coeff: color correction matrix. Values are 9-bit signed fixed-point numbers with 2 bit integer
+ * and 7 bit fractional part, ranging from -2 (0x100) to +1.992 (0x0FF). 0 is
+ * represented by 0x000 and a coefficient value of 1 as 0x080.
+ */
+struct rkisp2_params_csm {
+ struct v4l2_isp_params_block_header header;
+ __u16 coeff[3][3];
+};
+
+/**
+ * struct rkisp2_params_ccm - Configuration used by Color Correction Matrix
+ *
+ * RkISP2 parameters histogram configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_CCM`.
+ *
+ * @header: The RkISP2 parameters block header
+ * @high_y_alpha_adj_en: Enable CCM high Y alpha adjustment (TODO figure out what this does)
+ * @coeff: color correction matrix. Values are 11-bit signed fixed-point numbers with 4 bit integer
+ * and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF). 0 is
+ * represented by 0x000 and a coefficient value of 1 as 0x080. The
+ * value is expanded 128 times (TODO figure out what this means).
+ * @offset: Red, Green, Blue offsets for the color correction matrix. 12-bits
+ * wide ranging from -4096 to 4095, but only for red; green and blue are 11-bit
+ * signed fixed-point like coeff, but are still 12-bits wide.
+ * @y_coeff: Red, Green, Blue coefficients for RGB2Y calculation. red and green
+ * are 11-bits wide and blue is 12-bits wide. The value is expanded 128 times.
+ * @alp: CCM curve y-axis point definition for ccm input pixel's luminance.
+ * 11-bit unsigned ranging from 0 to 1024. The value is expanded 128 times.
+ * @inflection_point: Inflection point of the ccm alpha interpolation curve.
+ * The inflection point is 2^inflection_point. Since the maximum y-value is
+ * 1024, the maximum value of this field is expected to be 10 (0xa), but the
+ * documentation says 4'b10.
+ */
+struct rkisp2_params_ccm {
+ struct v4l2_isp_params_block_header header;
+ __u8 high_y_alpha_adj_en;
+ __u16 coeff[3][3];
+ __u16 offset[3];
+ __u16 y_coeff[3];
+ __u16 alp[17];
+ __u8 inflection_point;
+};
+
+/**
+ * struct rkisp2_params_goc - Configuration used by Gamma Out correction
+ *
+ * RkISP2 parameters gamma out correction configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_GOC`.
+ *
+ * @header: The RkISP2 parameters block header
+ * @mode: goc mode (from enum rkisp2_isp_goc_mode)
+ * @segments: segments mode (from enum rkisp2_isp_goc_segments)
+ * @offset: offset value of the gamma out curve
+ * @gamma_y: gamma out curve y-axis for all color components
+ *
+ * The number of entries of @gamma_y depends on the segments mode. The entries
+ * are 12-bit unsigned.
+ */
+struct rkisp2_params_goc {
+ struct v4l2_isp_params_block_header header;
+ __u8 mode;
+ __u8 segments;
+ __u16 offset;
+ __u16 gamma_y[RKISP2_ISP_GAMMA_OUT_MAX_SEGMENTS];
+};
+
+/**
+ * struct rkisp2_params_lsc - Configuration used by Lens shading correction
+ *
+ * RkISP2 parameters lens shading correction configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_LSC`.
+ *
+ * The LSC module on the rkisp2 two tables: the 0th table and the 1th table.
+ * They can be programmed independently and (somewhat) simultaneously, and can be
+ * swapped by setting a single register. Hence the UAPI here is designed so
+ * that all these components can be controlled independently.
+ *
+ * In the first dimension of {r,gr,gb,b}_data_tbl we can designate which table
+ * to write the data to. write_table is then used to signal whether to write
+ * the data, and this can be controlled for both tables. active_table chooses
+ * which table to activate. set_active_table_when signals whether to set the
+ * active_table before or after programming the table. This allows
+ * optimizations such as setting a future table in one parameter buffer while
+ * swapping before setting it.
+ *
+ * This design gives us more control. For example, if we want to only program
+ * the 0th table without modifying the 1th table, we do not need to also
+ * populate the 1th table and we can use write_table to designate that we only
+ * want to program the 0th table. We can also swap tables without needing to
+ * re-populate the tables by setting active_table and unsetting write_table.
+ *
+ * {x,y}_sizes designates the grid of the LSC, and the table entries above
+ * correspond to the *vertices* of the grid. {x,y}_grads control the bilinear
+ * interpolation within the grid.
+ *
+ * @header: The RkISP2 parameters block header
+ * @r_data_tbl: Sample table red
+ * @gr_data_tbl: Sample table green (red)
+ * @gb_data_tbl: Sample table green (blue)
+ * @b_data_tbl: Sample table blue
+ * @write_table: Set to 1 to signal to write the respective table from above
+ * @active_table: Choose which of the two tables is active (0 or 1)
+ * @set_active_table_when: From rkisp2_isp_set_active_table_when; switch to the
+ * active table before or after programming the table
+ * @x_sizes: Sizes x
+ * @y_sizes: Sizes y
+ * @x_grads: Gradients x
+ * @y_grads: Gradients y
+ * @window_mode: From enum rkisp2_isp_lsc_config
+ */
+struct rkisp2_params_lsc {
+ struct v4l2_isp_params_block_header header;
+
+ __u16 r_data_tbl[2][RKISP2_ISP_LSC_SAMPLES_MAX][RKISP2_ISP_LSC_SAMPLES_MAX];
+ __u16 gr_data_tbl[2][RKISP2_ISP_LSC_SAMPLES_MAX][RKISP2_ISP_LSC_SAMPLES_MAX];
+ __u16 gb_data_tbl[2][RKISP2_ISP_LSC_SAMPLES_MAX][RKISP2_ISP_LSC_SAMPLES_MAX];
+ __u16 b_data_tbl[2][RKISP2_ISP_LSC_SAMPLES_MAX][RKISP2_ISP_LSC_SAMPLES_MAX];
+ __u8 write_table[2];
+ __u8 active_table;
+ __u8 set_active_table_when;
+
+ __u16 x_sizes[RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX];
+ __u16 y_sizes[RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX];
+ __u16 x_grads[RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX];
+ __u16 y_grads[RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX];
+
+ __u8 window_mode;
+};
+
+#define RKISP2_PARAMS_MAX_SIZE \
+ (sizeof(struct rkisp2_params_bls) +\
+ sizeof(struct rkisp2_params_awb_gains) +\
+ sizeof(struct rkisp2_params_csm) +\
+ sizeof(struct rkisp2_params_ccm) +\
+ sizeof(struct rkisp2_params_goc) +\
+ sizeof(struct rkisp2_params_lsc))
+
#endif /* _UAPI_RKISP2_CONFIG_H */
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index eda4492e40dc..1d418a752d89 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -876,6 +876,9 @@ struct v4l2_pix_format {
#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A Statistics */
#define V4L2_META_FMT_RK_ISP1_EXT_PARAMS v4l2_fourcc('R', 'K', '1', 'E') /* Rockchip ISP1 3a Extensible Parameters */
+/* Vendor specific - used for RKISP2 camera sub-system */
+#define V4L2_META_FMT_RKISP2_PARAMS v4l2_fourcc('R', 'K', '2', 'P') /* Rockchip ISP2 Parameters */
+
/* Vendor specific - used for C3_ISP */
#define V4L2_META_FMT_C3ISP_PARAMS v4l2_fourcc('C', '3', 'P', 'M') /* Amlogic C3 ISP Parameters */
#define V4L2_META_FMT_C3ISP_STATS v4l2_fourcc('C', '3', 'S', 'T') /* Amlogic C3 ISP Statistics */
--
2.47.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [RFC PATCH 5/5] media: rkisp2: Add statistics capture video node
2026-04-24 17:58 [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588 Paul Elder
` (3 preceding siblings ...)
2026-04-24 17:58 ` [RFC PATCH 4/5] media: rkisp2: Add parameters output video node Paul Elder
@ 2026-04-24 17:58 ` Paul Elder
4 siblings, 0 replies; 8+ messages in thread
From: Paul Elder @ 2026-04-24 17:58 UTC (permalink / raw)
To: laurent.pinchart
Cc: Paul Elder, michael.riesch, xuhf, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel
Implement support for getting statistics out of the ISP by dequeueing
statistics buffers from rkisp2.
Support for configuring the statistics engines in the ISP is added as
well, implemented as configurations in parameter buffers.
Support for the following statistics engines is added:
- AE (auto exposure) lite
- Histogram lite
- Histogram big
- AWB (auto white balance)
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
---
I've kept the debug counters that helped me debug interrupts for the
stats engines.
---
.../media/platform/rockchip/rkisp2/Makefile | 3 +-
.../platform/rockchip/rkisp2/rkisp2-common.h | 56 ++
.../platform/rockchip/rkisp2/rkisp2-debug.c | 16 +
.../platform/rockchip/rkisp2/rkisp2-dev.c | 13 +
.../platform/rockchip/rkisp2/rkisp2-isp.c | 6 +
.../platform/rockchip/rkisp2/rkisp2-params.c | 238 +++++++++
.../rockchip/rkisp2/rkisp2-regs-v2x.h | 39 +-
.../rockchip/rkisp2/rkisp2-regs-v3x.h | 13 +
.../platform/rockchip/rkisp2/rkisp2-stats.c | 482 ++++++++++++++++++
drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
include/uapi/linux/rkisp2-config.h | 233 ++++++++-
include/uapi/linux/videodev2.h | 1 +
12 files changed, 1098 insertions(+), 3 deletions(-)
create mode 100644 drivers/media/platform/rockchip/rkisp2/rkisp2-stats.c
diff --git a/drivers/media/platform/rockchip/rkisp2/Makefile b/drivers/media/platform/rockchip/rkisp2/Makefile
index 0fa014afcae4..8e323a560a39 100644
--- a/drivers/media/platform/rockchip/rkisp2/Makefile
+++ b/drivers/media/platform/rockchip/rkisp2/Makefile
@@ -5,7 +5,8 @@ rockchip-isp2-y := rkisp2-capture.o \
rkisp2-dev.o \
rkisp2-dmarx.o \
rkisp2-isp.o \
- rkisp2-params.o
+ rkisp2-params.o \
+ rkisp2-stats.o
rockchip-isp2-$(CONFIG_DEBUG_FS) += rkisp2-debug.o
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
index 7473dae6c525..742954e8b569 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-common.h
@@ -91,6 +91,7 @@ enum rkisp2_isp_pad {
RKISP2_ISP_PAD_SINK_VIDEO,
RKISP2_ISP_PAD_SINK_PARAMS,
RKISP2_ISP_PAD_SOURCE_VIDEO,
+ RKISP2_ISP_PAD_SOURCE_STATS,
RKISP2_ISP_PAD_MAX
};
@@ -314,6 +315,46 @@ struct rkisp2_capture {
struct v4l2_rect crop;
};
+/*
+ * struct rkisp2_stats - ISP Statistics device
+ *
+ * @vnode: video node
+ * @rkisp2: pointer to the rkisp2 device
+ * @lock: locks the buffer list 'stat'
+ * @stat: queue of rkisp2_buffer
+ * @vdev_fmt: v4l2_format of the metadata format
+ * @imsc: interrupts that the stats is listening for (for stats 3a)
+ * @icr: interrupts that the stats has handled for the current frame (for stats 3a)
+ * @cur_buf: the current buffer to accumulate stats over multiple interrupts
+ *
+ * The imsc and icr fields are necessary to accumulate the stats because there
+ * seem to be separate interrupts in stats 3a for big modules and non-big
+ * modules. The conditions that cause separate interrupts are not yet fully
+ * understood, but is hypothesized to be big-mode & different window size
+ * compared to lite mode. We may need a similar construct for the core stats,
+ * but they have not been implemented yet (and they may not even exist).
+ *
+ * The imsc field is filled at v_start time to store what stats 3a interrupts
+ * we expect, then as they come in they are cleared by signalling in icr. The
+ * interrupt that fully sets icr (compared to imsc) will complete the stats
+ * buffer. On the next v_start any leftovers are cleared and logged as a
+ * counter to debugfs.
+ */
+struct rkisp2_stats {
+ struct rkisp2_vdev_node vnode;
+ struct rkisp2_device *rkisp2;
+
+ spinlock_t lock; /* locks the buffers list 'stats' */
+ struct list_head stat;
+ struct v4l2_format vdev_fmt;
+
+ u32 imsc;
+ u32 icr;
+ struct rkisp2_buffer *cur_buf;
+
+ unsigned int awb_window_offset;
+};
+
/*
* struct rkisp2_params - ISP input parameters device
*
@@ -342,9 +383,17 @@ struct rkisp2_debug {
unsigned long irq_delay;
unsigned long mipi_error;
unsigned long stats_error;
+ unsigned long stats3a_irq;
+ unsigned long stats_irq_delay;
unsigned long stop_timeout[2];
unsigned long frame_drop[2];
unsigned long complete_frames;
+ unsigned long stats3a_hist_ch0_count;
+ unsigned long stats3a_hist_ch1_count;
+ unsigned long stats3a_hist_ch2_count;
+ unsigned long stats3a_hist_big_count;
+ unsigned long stats3a_awb_count;
+ unsigned long stats3a_awb_done_count;
};
/*
@@ -366,6 +415,7 @@ struct rkisp2_debug {
* @capture_devs: capture devices
* @dmarx: ISP memory read device
* @params: ISP parameters metadata output device
+ * @stats: ISP statistics metadata capture device
* @pipe: media pipeline
* @stream_lock: serializes {start/stop}_streaming callbacks between the capture devices.
* @debug: debug params to be exposed on debugfs
@@ -388,6 +438,7 @@ struct rkisp2_device {
struct rkisp2_capture capture_devs[2];
struct rkisp2_dmarx dmarx;
struct rkisp2_params params;
+ struct rkisp2_stats stats;
struct media_pipeline pipe;
struct mutex stream_lock; /* serialize {start/stop}_streaming cb between capture devices */
struct rkisp2_debug debug;
@@ -478,6 +529,8 @@ irqreturn_t rkisp2_capture_isr(int irq, void *ctx);
irqreturn_t rkisp2_mipi_isr(int irq, void *ctx);
void rkisp2_dmarx_isr(struct rkisp2_device *rkisp2, u32 status);
void rkisp2_params_isr(struct rkisp2_params *params);
+void rkisp2_stats_isr_v_start(struct rkisp2_stats *);
+irqreturn_t rkisp2_stats_isr_3a(struct rkisp2_stats *);
/* register/unregisters functions of the entities */
int rkisp2_capture_devs_register(struct rkisp2_device *rkisp2);
@@ -494,6 +547,9 @@ void rkisp2_params_pre_configure(struct rkisp2_params *params,
enum rkisp2_fmt_raw_pat_type bayer_pat);
void rkisp2_params_post_configure(struct rkisp2_params *params);
+int rkisp2_stats_register(struct rkisp2_device *rkisp2);
+void rkisp2_stats_unregister(struct rkisp2_device *rkisp2);
+
#if IS_ENABLED(CONFIG_DEBUG_FS)
void rkisp2_debug_init(struct rkisp2_device *rkisp2);
void rkisp2_debug_cleanup(struct rkisp2_device *rkisp2);
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
index 4f439bd9156b..92beae3530c4 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-debug.c
@@ -191,6 +191,10 @@ void rkisp2_debug_init(struct rkisp2_device *rkisp2)
&debug->mipi_error);
debugfs_create_ulong("stats_error", 0444, debug->debugfs_dir,
&debug->stats_error);
+ debugfs_create_ulong("stats3a_irq", 0444, debug->debugfs_dir,
+ &debug->stats3a_irq);
+ debugfs_create_ulong("stats_irq_delay", 0444, debug->debugfs_dir,
+ &debug->stats_irq_delay);
debugfs_create_ulong("mp_stop_timeout", 0444, debug->debugfs_dir,
&debug->stop_timeout[RKISP2_MAINPATH]);
debugfs_create_ulong("sp_stop_timeout", 0444, debug->debugfs_dir,
@@ -201,6 +205,18 @@ void rkisp2_debug_init(struct rkisp2_device *rkisp2)
&debug->frame_drop[RKISP2_SELFPATH]);
debugfs_create_ulong("complete_frames", 0444, debug->debugfs_dir,
&debug->complete_frames);
+ debugfs_create_ulong("stats3a_hist_ch0_count", 0444, debug->debugfs_dir,
+ &debug->stats3a_hist_ch0_count);
+ debugfs_create_ulong("stats3a_hist_ch1_count", 0444, debug->debugfs_dir,
+ &debug->stats3a_hist_ch1_count);
+ debugfs_create_ulong("stats3a_hist_ch2_count", 0444, debug->debugfs_dir,
+ &debug->stats3a_hist_ch2_count);
+ debugfs_create_ulong("stats3a_hist_big_count", 0444, debug->debugfs_dir,
+ &debug->stats3a_hist_big_count);
+ debugfs_create_ulong("stats3a_awb_count", 0444, debug->debugfs_dir,
+ &debug->stats3a_awb_count);
+ debugfs_create_ulong("stats3a_awb_done_count", 0444, debug->debugfs_dir,
+ &debug->stats3a_awb_done_count);
debugfs_create_file("input_status", 0444, debug->debugfs_dir, rkisp2,
&rkisp2_debug_input_status_fops);
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
index 0356ef2a1cf1..4042bf43d287 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-dev.c
@@ -138,12 +138,21 @@ static int rkisp2_create_links(struct rkisp2_device *rkisp2)
if (ret)
return ret;
+ /* stats links */
+ ret = media_create_pad_link(&rkisp2->isp.sd.entity,
+ RKISP2_ISP_PAD_SOURCE_STATS,
+ &rkisp2->stats.vnode.vdev.entity, 0,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (ret)
+ return ret;
return 0;
}
static void rkisp2_entities_unregister(struct rkisp2_device *rkisp2)
{
+ rkisp2_stats_unregister(rkisp2);
rkisp2_params_unregister(rkisp2);
rkisp2_dmarx_unregister(rkisp2);
rkisp2_capture_devs_unregister(rkisp2);
@@ -170,6 +179,10 @@ static int rkisp2_entities_register(struct rkisp2_device *rkisp2)
if (ret)
goto error;
+ ret = rkisp2_stats_register(rkisp2);
+ if (ret)
+ goto error;
+
ret = rkisp2_create_links(rkisp2);
if (ret)
goto error;
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
index 0967d5772bc9..f8f34f4f5919 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-isp.c
@@ -812,6 +812,7 @@ int rkisp2_isp_register(struct rkisp2_device *rkisp2)
MEDIA_PAD_FL_MUST_CONNECT;
pads[RKISP2_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
pads[RKISP2_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
+ pads[RKISP2_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&sd->entity, RKISP2_ISP_PAD_MAX, pads);
if (ret)
@@ -876,6 +877,9 @@ irqreturn_t rkisp2_isp_isr(int irq, void *ctx)
if (!status)
return IRQ_NONE;
+ /* This is in a separate register so we need to check it separately */
+ rkisp2_stats_isr_3a(&rkisp2->stats);
+
/* Vertical sync signal, starting generating new frame */
if (status & RKISP2_CIF_ISP_V_START) {
rkisp2->isp.frame_sequence++;
@@ -884,6 +888,8 @@ irqreturn_t rkisp2_isp_isr(int irq, void *ctx)
WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n");
rkisp2->debug.irq_delay++;
}
+
+ rkisp2_stats_isr_v_start(&rkisp2->stats);
}
if (status & RKISP2_CIF_ISP_PIC_SIZE_ERROR) {
/* Clear pic_size_error */
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
index b7b27d0e90c6..b149c20a4763 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-params.c
@@ -33,6 +33,10 @@
.priority = RKISP2_PARAMS_CONFIG_PRIO_ ## prio_postfix, \
}
+/*
+ * We only need one instance of hist_big here since it's only for accessing the
+ * members of the union
+ */
union rkisp2_params_block {
const struct v4l2_isp_params_block_header *header;
const struct rkisp2_params_bls *bls;
@@ -41,6 +45,10 @@ union rkisp2_params_block {
const struct rkisp2_params_ccm *ccm;
const struct rkisp2_params_goc *goc;
const struct rkisp2_params_lsc *lsc;
+ const struct rkisp2_params_ae_lite *ae_lite;
+ const struct rkisp2_params_hist_lite *hist_lite;
+ const struct rkisp2_params_hist_big *hist_big;
+ const struct rkisp2_params_awb_meas *awb_meas;
const __u8 *data;
};
@@ -56,6 +64,14 @@ static void rkisp2_params_goc(struct rkisp2_params *params,
union rkisp2_params_block block);
static void rkisp2_params_lsc(struct rkisp2_params *params,
union rkisp2_params_block block);
+static void rkisp2_params_ae_lite(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_hist_lite(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_hist_big(struct rkisp2_params *params,
+ union rkisp2_params_block block);
+static void rkisp2_params_awb_meas(struct rkisp2_params *params,
+ union rkisp2_params_block block);
typedef void (*rkisp2_params_handler)(struct rkisp2_params *params,
const union rkisp2_params_block block);
@@ -79,6 +95,12 @@ rkisp2_params_handlers[] = {
RKISP2_PARAMS_BLOCK_HANDLER_INFO(CCM, ccm, PRE),
RKISP2_PARAMS_BLOCK_HANDLER_INFO(GOC, goc, PRE),
RKISP2_PARAMS_BLOCK_HANDLER_INFO(LSC, lsc, POST),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(AE_LITE, ae_lite, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(HIST_LITE, hist_lite, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(HIST_BIG0, hist_big, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(HIST_BIG1, hist_big, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(HIST_BIG2, hist_big, PRE),
+ RKISP2_PARAMS_BLOCK_HANDLER_INFO(AWB_MEAS, awb_meas, PRE),
};
static const struct v4l2_isp_params_block_type_info
@@ -89,6 +111,12 @@ rkisp2_params_block_types_info[] = {
RKISP2_PARAMS_BLOCK_INFO(CCM, ccm),
RKISP2_PARAMS_BLOCK_INFO(GOC, goc),
RKISP2_PARAMS_BLOCK_INFO(LSC, lsc),
+ RKISP2_PARAMS_BLOCK_INFO(AE_LITE, ae_lite),
+ RKISP2_PARAMS_BLOCK_INFO(HIST_LITE, hist_lite),
+ RKISP2_PARAMS_BLOCK_INFO(HIST_BIG0, hist_big),
+ RKISP2_PARAMS_BLOCK_INFO(HIST_BIG1, hist_big),
+ RKISP2_PARAMS_BLOCK_INFO(HIST_BIG2, hist_big),
+ RKISP2_PARAMS_BLOCK_INFO(AWB_MEAS, awb_meas),
};
static_assert(ARRAY_SIZE(rkisp2_params_handlers) ==
@@ -415,6 +443,216 @@ static void rkisp2_params_lsc(struct rkisp2_params *params,
rkisp2_param_set_bits(params, ISP3X_LSC_CTRL, data);
}
+static void rkisp2_params_ae_lite(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_ae_lite *arg = block.ae_lite;
+ u32 control;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP_RAWAE_LITE_CTRL,
+ ISP3X_RAWAE_LITE_EN);
+ rkisp2_param_clear_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWAE_CH0);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ /*
+ * \todo clamp these: width and height must be even, min size is 16x4,
+ * and total height must be < frame height
+ */
+ rkisp2_write(params->rkisp2, ISP_RAWAE_LITE_BLK_SIZ,
+ ISP3X_RAWAE_LITE_H(arg->meas_window.h_size) |
+ ISP3X_RAWAE_LITE_V(arg->meas_window.v_size));
+
+ rkisp2_write(params->rkisp2, ISP_RAWAE_LITE_OFFSET,
+ ISP3X_RAWAE_LITE_H(arg->meas_window.h_offs) |
+ ISP3X_RAWAE_LITE_V(arg->meas_window.v_offs));
+
+ control = arg->window_num ? ISP3X_RAWAE_LITE_WNDNUM : 0;
+ control |= ISP3X_RAWAE_LITE_EN;
+
+ rkisp2_param_set_bits(params, ISP_RAWAE_LITE_CTRL,
+ control);
+ /* TODO figure out CH1 and CH2 */
+ rkisp2_param_set_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWAE_CH0);
+}
+
+static void rkisp2_params_hist_lite(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_hist_lite *arg = block.hist_lite;
+ unsigned int i;
+ u32 control;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP_RAWHIST_LITE_BASE, ISP_RAWHIST_CTRL_EN);
+ rkisp2_param_clear_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWHIST_CH0);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ rkisp2_write(params->rkisp2, ISP_RAWHIST_LITE_SIZE,
+ ISP_RAWHIST_H_SIZE(arg->meas_window.h_size) |
+ ISP_RAWHIST_V_SIZE(arg->meas_window.v_size));
+
+ rkisp2_write(params->rkisp2, ISP_RAWHIST_LITE_OFFS,
+ ISP_RAWHIST_H_OFFS(arg->meas_window.h_offs) |
+ ISP_RAWHIST_V_OFFS(arg->meas_window.v_offs));
+
+ rkisp2_write(params->rkisp2, ISP_RAWHIST_LITE_RAW2Y_CC,
+ ISP_RAWHIST_RAW2Y_CC_RCC(arg->coeffs.r) |
+ ISP_RAWHIST_RAW2Y_CC_GCC(arg->coeffs.g) |
+ ISP_RAWHIST_RAW2Y_CC_BCC(arg->coeffs.b));
+
+ for (i = 0; i < 6; i++) {
+ rkisp2_write(params->rkisp2, ISP_RAWHIST_LITE_WEIGHT + 4 * i,
+ ISP_RAWHIST_LITE_WEIGHT_WND0(arg->weights[4 * i + 0]) |
+ ISP_RAWHIST_LITE_WEIGHT_WND1(arg->weights[4 * i + 1]) |
+ ISP_RAWHIST_LITE_WEIGHT_WND2(arg->weights[4 * i + 2]) |
+ ISP_RAWHIST_LITE_WEIGHT_WND3(arg->weights[4 * i + 3]));
+ }
+
+ rkisp2_write(params->rkisp2, ISP_RAWHIST_LITE_WEIGHT + 4 * 6,
+ ISP_RAWHIST_LITE_WEIGHT_WND0(arg->weights[24]));
+
+ control = ISP_RAWHIST_CTRL_EN |
+ ISP_RAWHIST_CTRL_STEPSIZE(arg->stepsize) |
+ ISP_RAWHIST_CTRL_MODE(arg->mode) |
+ ISP_RAWHIST_CTRL_WATERLINE(arg->waterline) |
+ ISP_RAWHIST_CTRL_DATA_SEL(arg->data_sel);
+ rkisp2_write(params->rkisp2, ISP_RAWHIST_LITE_CTRL, control);
+ // I think you can choose the channels in VI_ISP_PATH
+ rkisp2_param_set_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWHIST_CH0);
+}
+
+static void rkisp2_params_hist_big(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_hist_big *arg = block.hist_big;
+ unsigned int i, reg_base, ctrl;
+ u32 control;
+
+ switch (block.header->type) {
+ case RKISP2_PARAMS_BLOCK_HIST_BIG0:
+ reg_base = ISP_RAWHIST_BIG1_BASE;
+ break;
+ case RKISP2_PARAMS_BLOCK_HIST_BIG1:
+ reg_base = ISP_RAWHIST_BIG2_BASE;
+ break;
+ case RKISP2_PARAMS_BLOCK_HIST_BIG2:
+ reg_base = ISP_RAWHIST_BIG3_BASE;
+ break;
+ default:
+ WARN_ONCE(1, "invalid big histogram base %x\n", reg_base);
+ return;
+ }
+
+ ctrl = reg_base + ISP_RAWHIST_BIG_CTRL;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ctrl, ISP_RAWHIST_CTRL_EN);
+ rkisp2_param_clear_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWHIST_BIG);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ rkisp2_write(params->rkisp2, reg_base + ISP_RAWHIST_BIG_SIZE,
+ ISP_RAWHIST_H_SIZE(arg->meas_window.h_size) |
+ ISP_RAWHIST_V_SIZE(arg->meas_window.v_size));
+
+ rkisp2_write(params->rkisp2, reg_base + ISP_RAWHIST_BIG_OFFS,
+ ISP_RAWHIST_H_OFFS(arg->meas_window.h_offs) |
+ ISP_RAWHIST_V_OFFS(arg->meas_window.v_offs));
+
+ rkisp2_write(params->rkisp2, reg_base + ISP_RAWHIST_BIG_RAW2Y_CC,
+ ISP_RAWHIST_RAW2Y_CC_RCC(arg->coeffs.r) |
+ ISP_RAWHIST_RAW2Y_CC_GCC(arg->coeffs.g) |
+ ISP_RAWHIST_RAW2Y_CC_BCC(arg->coeffs.b));
+
+ /*
+ * TODO check if the other weights are programmed in the registers
+ * after the bins, or if it's sequential write
+ */
+ for (i = 0; i < 16; i++) {
+ rkisp2_write(params->rkisp2, reg_base + ISP_RAWHIST_BIG_WEIGHT_BASE + 4 * i,
+ ISP_RAWHIST_BIG_WEIGHT_WND0(arg->weights[5 * i + 0]) |
+ ISP_RAWHIST_BIG_WEIGHT_WND1(arg->weights[5 * i + 1]) |
+ ISP_RAWHIST_BIG_WEIGHT_WND2(arg->weights[5 * i + 2]) |
+ ISP_RAWHIST_BIG_WEIGHT_WND3(arg->weights[5 * i + 3]) |
+ ISP_RAWHIST_BIG_WEIGHT_WND4(arg->weights[5 * i + 4]));
+ }
+
+ rkisp2_param_set_bits(params, ISP_CTRL1, ISP21_BIGMODE_MODE | ISP21_BIGMODE_FORCE_EN);
+
+ control = ISP_RAWHIST_CTRL_EN |
+ ISP_RAWHIST_CTRL_STEPSIZE(arg->stepsize) |
+ ISP_RAWHIST_CTRL_MODE(arg->mode) |
+ ISP_RAWHIST_CTRL_WATERLINE(arg->waterline) |
+ ISP_RAWHIST_CTRL_DATA_SEL(arg->data_sel) |
+ (arg->window_num & ISP_RAWHIST_BIG_CTRL_WND_MASK);
+ rkisp2_write(params->rkisp2, ctrl, control);
+ rkisp2_param_set_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWHIST_BIG);
+}
+
+static void rkisp2_params_awb_meas(struct rkisp2_params *params,
+ union rkisp2_params_block block)
+{
+ const struct rkisp2_params_awb_meas *arg = block.awb_meas;
+ unsigned int i;
+ u32 val;
+ u32 control = 0;
+
+ if (block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) {
+ rkisp2_param_clear_bits(params, ISP3X_RAWAWB_CTRL,
+ ISP3X_RAWAWB_CTRL_EN);
+ rkisp2_param_clear_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWAWB);
+ rkisp2_param_clear_bits(params, ISP21_RAWAWB_BLK_CTRL, 0x1);
+ return;
+ }
+
+ if (!(block.header->flags & V4L2_ISP_PARAMS_FL_BLOCK_ENABLE))
+ return;
+
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_WIN_OFFS,
+ ISP3X_RAWAWB_WIN(arg->meas_window.h_offs,
+ arg->meas_window.v_offs));
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_WIN_SIZE,
+ ISP3X_RAWAWB_WIN(arg->meas_window.h_size,
+ arg->meas_window.v_size));
+
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_LIMIT_RG_MAX,
+ ISP3X_RAWAWB_LIMITS(arg->limits[1].r, arg->limits[1].g));
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_LIMIT_BY_MAX,
+ ISP3X_RAWAWB_LIMITS(arg->limits[1].b, arg->limits[1].y));
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_LIMIT_RG_MIN,
+ ISP3X_RAWAWB_LIMITS(arg->limits[0].r, arg->limits[0].g));
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_LIMIT_BY_MIN,
+ ISP3X_RAWAWB_LIMITS(arg->limits[0].b, arg->limits[0].y));
+
+ for (i = 0; i < RKISP2_ISP_AWB_COUNTS_SIZE / 5; i++) {
+ val = (arg->weights[5 * i] & 0x3f)
+ | ((arg->weights[5 * i + 1] & 0x3f) << 6)
+ | ((arg->weights[5 * i + 2] & 0x3f) << 12)
+ | ((arg->weights[5 * i + 3] & 0x3f) << 18)
+ | ((arg->weights[5 * i + 4] & 0x3f) << 24);
+ rkisp2_write(params->rkisp2, ISP21_RAWAWB_WRAM_DATA_BASE, val);
+ }
+
+ // This options looks like it's required to get "useful" data out
+ rkisp2_param_set_bits(params, ISP21_RAWAWB_BLK_CTRL, 0x1);
+
+ control |= ISP3X_RAWAWB_CTRL_EN;
+ rkisp2_write(params->rkisp2, ISP3X_RAWAWB_CTRL, control);
+ rkisp2_param_set_bits(params, ISP_ISP3A_IMSC, ISP2X_3A_RAWAWB);
+}
+
static void rkisp2_params_configure(struct rkisp2_params *params,
struct rkisp2_params_buffer *buf,
enum rkisp2_params_configure_priority prio)
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
index 883bdb7c2a61..26deacb0b63d 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v2x.h
@@ -1429,7 +1429,7 @@
#define ISP_RAWAE_LITE_BLK_SIZ (ISP_RAWAE_LITE_BASE + 0x00004)
#define ISP_RAWAE_LITE_OFFSET (ISP_RAWAE_LITE_BASE + 0x00008)
#define ISP_RAWAE_LITE_R2Y_CC (ISP_RAWAE_LITE_BASE + 0x0000c)
-#define ISP_RAWAE_LITE_RO_MEAN (ISP_RAWAE_LITE_BASE + 0x00010)
+#define ISP_RAWAE_LITE_RO_MEAN(i) (ISP_RAWAE_LITE_BASE + 0x00010 + ((i) * 4))
#define ISP_RAWAE_LITE_RO_DBG1 (ISP_RAWAE_LITE_BASE + 0x00074)
#define ISP_RAWAE_LITE_RO_DBG2 (ISP_RAWAE_LITE_BASE + 0x00078)
@@ -2585,4 +2585,41 @@
/* ISP21 DHAZ/DRC/BAY3D */
#define ISP21_SELF_FORCE_UPD BIT(31)
+/* RAWHIST */
+#define ISP_RAWHIST_CTRL_EN BIT(0)
+#define ISP_RAWHIST_CTRL_STEPSIZE(a) (((a) & 0x7) << 1)
+#define ISP_RAWHIST_CTRL_MODE(a) (((a) & 0x7) << 8)
+#define ISP_RAWHIST_CTRL_WATERLINE(a) (((a) & 0xfff) << 12)
+#define ISP_RAWHIST_CTRL_DATA_SEL(a) (((a) & 0x7) << 24)
+#define ISP_RAWHIST_CTRL_MEAS_DONE BIT(31)
+#define ISP_RAWHIST_BIG_CTRL_WND_5X5_1 BIT(28)
+#define ISP_RAWHIST_BIG_CTRL_WND_15X15_0 BIT(29)
+#define ISP_RAWHIST_BIG_CTRL_WND_15X15_1 (0x3 << 28)
+#define ISP_RAWHIST_BIG_CTRL_WND_MASK GENMASK(29, 28)
+
+#define ISP_RAWHIST_H_SIZE(a) ((a) & 0x7ff)
+#define ISP_RAWHIST_V_SIZE(a) (((a) & 0x7ff) << 16)
+#define ISP_RAWHIST_H_OFFS(a) ((a) & 0x1fff)
+#define ISP_RAWHIST_V_OFFS(a) (((a) & 0x1fff) << 16)
+
+#define ISP_RAWHIST_RAW2Y_CC_RCC(a) ((a) & 0xff)
+#define ISP_RAWHIST_RAW2Y_CC_GCC(a) (((a) & 0xff) << 8)
+#define ISP_RAWHIST_RAW2Y_CC_BCC(a) (((a) & 0xff) << 16)
+#define ISP_RAWHIST_RAW2Y_CC_OFF(a) (((a) & 0xff) << 24)
+
+#define ISP_RAWHIST_LITE_WEIGHT_WND0(a) ((a) & 0x3f)
+#define ISP_RAWHIST_LITE_WEIGHT_WND1(a) (((a) & 0x3f) << 8)
+#define ISP_RAWHIST_LITE_WEIGHT_WND2(a) (((a) & 0x3f) << 16)
+#define ISP_RAWHIST_LITE_WEIGHT_WND3(a) (((a) & 0x3f) << 24)
+
+#define ISP_RAWHIST_BIG_WEIGHT_WND0(a) ((a) & 0x3f)
+#define ISP_RAWHIST_BIG_WEIGHT_WND1(a) (((a) & 0x3f) << 6)
+#define ISP_RAWHIST_BIG_WEIGHT_WND2(a) (((a) & 0x3f) << 12)
+#define ISP_RAWHIST_BIG_WEIGHT_WND3(a) (((a) & 0x3f) << 18)
+#define ISP_RAWHIST_BIG_WEIGHT_WND4(a) (((a) & 0x3f) << 24)
+
+#define ISP_RAWHIST_BIN_MASK GENMASK(27, 0)
+
+#define ISP_RAWHIST_RAM_OFFSET(a) ((a) & 0xff)
+
#endif /* _RKISP_REGS_V2X_H */
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
index d27d9a48887e..73dc3b22873c 100644
--- a/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-regs-v3x.h
@@ -3367,6 +3367,13 @@
#define ISP3X_RAWAE_BIG_WND3_EN BIT(6)
#define ISP3X_RAWAE_BIG_WND4_EN BIT(7)
+#define ISP3X_RAWAE_LITE_H(a) ((a) & 0x1fff)
+#define ISP3X_RAWAE_LITE_V(a) (((a) & 0x1fff) << 16)
+
+#define ISP3X_RAWAE_LITE_RO_MEAN_R(a) (((a) >> 22) & 0x3ff)
+#define ISP3X_RAWAE_LITE_RO_MEAN_B(a) (((a) >> 12) & 0x3ff)
+#define ISP3X_RAWAE_LITE_RO_MEAN_G(a) ((a) & 0xfff)
+
/* RAWHIST */
#define ISP3X_RAWHIST_EN BIT(0)
#define ISP3X_RAWHIST_STEPSIZE(x) (((x) & 0x7) << 1)
@@ -3397,6 +3404,12 @@
#define ISP3X_RAWAF_INTLINE0_EN BIT(27)
/* RAWAWB */
+#define ISP3X_RAWAWB_CTRL_EN BIT(0)
+#define ISP3X_RAWAWB_CTRL_MEAS_DONE BIT(31)
+
+#define ISP3X_RAWAWB_WIN(h, v) (((h) & 0x1fff) | (((v) & 0x1fff) << 16))
+#define ISP3X_RAWAWB_LIMITS(a, b) (((a) & 0xff) | (((b) & 0xff) << 16))
+
#define ISP32_RAWAWB_2DDR_PATH_EN BIT(23)
#define ISP32_RAWAWB_2DDR_PATH_DS BIT(27)
#define ISP32_RAWAWB_2DDR_PATH_ERR BIT(29)
diff --git a/drivers/media/platform/rockchip/rkisp2/rkisp2-stats.c b/drivers/media/platform/rockchip/rkisp2/rkisp2-stats.c
new file mode 100644
index 000000000000..f9dbe05bf218
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp2/rkisp2-stats.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Rockchip ISP2 Driver - Stats subdevice
+ *
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2026 Ideas on Board Oy.
+ */
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "rkisp2-common.h"
+
+#define RKISP2_STATS_DEV_NAME RKISP2_DRIVER_NAME "_stats"
+
+static int rkisp2_stats_enum_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ if (f->index)
+ return -EINVAL;
+
+ f->pixelformat = V4L2_META_FMT_RKISP2_STATS;
+
+ return 0;
+}
+
+static int rkisp2_stats_g_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ static const struct v4l2_meta_format mfmt = {
+ .dataformat = V4L2_META_FMT_RKISP2_STATS,
+ .buffersize = sizeof(struct rkisp2_stats_buffer)
+ };
+
+ f->fmt.meta = mfmt;
+
+ return 0;
+}
+
+static int rkisp2_stats_querycap(struct file *file,
+ void *priv, struct v4l2_capability *cap)
+{
+ struct video_device *vdev = video_devdata(file);
+
+ strscpy(cap->driver, RKISP2_DRIVER_NAME, sizeof(cap->driver));
+ strscpy(cap->card, vdev->name, sizeof(cap->card));
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops rkisp2_stats_ioctl = {
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_enum_fmt_meta_cap = rkisp2_stats_enum_fmt_meta_cap,
+ .vidioc_g_fmt_meta_cap = rkisp2_stats_g_fmt_meta_cap,
+ .vidioc_s_fmt_meta_cap = rkisp2_stats_g_fmt_meta_cap,
+ .vidioc_try_fmt_meta_cap = rkisp2_stats_g_fmt_meta_cap,
+ .vidioc_querycap = rkisp2_stats_querycap,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct v4l2_file_operations rkisp2_stats_fops = {
+ .mmap = vb2_fop_mmap,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vb2_fop_poll,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release
+};
+
+static int rkisp2_stats_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ /* TODO num_buffers */
+
+ *num_planes = 1;
+
+ sizes[0] = sizeof(struct rkisp2_stats_buffer);
+
+ return 0;
+}
+
+static void rkisp2_stats_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp2_buffer *stats_buf =
+ container_of(vbuf, struct rkisp2_buffer, vb);
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct rkisp2_stats *stats_dev = vq->drv_priv;
+
+ spin_lock_irq(&stats_dev->lock);
+ list_add_tail(&stats_buf->queue, &stats_dev->stat);
+ spin_unlock_irq(&stats_dev->lock);
+}
+
+static int rkisp2_stats_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ if (vb2_plane_size(vb, 0) < sizeof(struct rkisp2_stats_buffer))
+ return -EINVAL;
+
+ vb2_set_plane_payload(vb, 0, sizeof(struct rkisp2_stats_buffer));
+
+ return 0;
+}
+
+static int rkisp2_stats_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct rkisp2_stats *stats = vq->drv_priv;
+ stats->imsc = 0;
+ stats->icr = 0;
+ stats->cur_buf = NULL;
+ stats->awb_window_offset = 0;
+
+ return 0;
+}
+
+static void rkisp2_stats_vb2_stop_streaming(struct vb2_queue *vq)
+{
+ struct rkisp2_stats *stats = vq->drv_priv;
+ struct rkisp2_buffer *buf;
+ LIST_HEAD(tmp_list);
+
+ spin_lock_irq(&stats->lock);
+ list_splice_init(&stats->stat, &tmp_list);
+ spin_unlock_irq(&stats->lock);
+
+ list_for_each_entry(buf, &tmp_list, queue)
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+
+ if (stats->cur_buf != NULL) {
+ vb2_buffer_done(&stats->cur_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+ stats->cur_buf = NULL;
+ }
+}
+
+static const struct vb2_ops rkisp2_stats_vb2_ops = {
+ .queue_setup = rkisp2_stats_vb2_queue_setup,
+ .buf_queue = rkisp2_stats_vb2_buf_queue,
+ .buf_prepare = rkisp2_stats_vb2_buf_prepare,
+ .start_streaming = rkisp2_stats_vb2_start_streaming,
+ .stop_streaming = rkisp2_stats_vb2_stop_streaming,
+};
+
+static int
+rkisp2_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp2_stats *stats)
+{
+ struct rkisp2_vdev_node *node;
+
+ node = container_of(q, struct rkisp2_vdev_node, buf_queue);
+
+ q->type = V4L2_BUF_TYPE_META_CAPTURE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->drv_priv = stats;
+ q->ops = &rkisp2_stats_vb2_ops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->buf_struct_size = sizeof(struct rkisp2_buffer);
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->vlock;
+ q->dev = stats->rkisp2->dev;
+
+ return vb2_queue_init(q);
+}
+
+static void rkisp2_stats_get_rawae_lite(struct rkisp2_stats *stats,
+ u32 status,
+ struct rkisp2_stats_buffer *pbuf)
+{
+ struct rkisp2_device *rkisp2 = stats->rkisp2;
+ struct rkisp2_isp_ae_lite *ae_lite;
+ unsigned int i;
+ u32 val;
+
+ /* TODO figure out a nicer way to synchronize this with params and imsc */
+ /* TODO figure out what the other channels are for */
+ if (!(status & ISP2X_3A_RAWAE_CH0))
+ return;
+ stats->icr |= ISP2X_3A_RAWAE_CH0;
+
+ ae_lite = &pbuf->ae_lite;
+
+ for (i = 0; i < RKISP2_ISP_AE_MEAN_MAX_LITE; i++) {
+ val = rkisp2_read(rkisp2, ISP_RAWAE_LITE_RO_MEAN(i));
+ ae_lite->exp_mean_r[i] = ISP3X_RAWAE_LITE_RO_MEAN_R(val);
+ ae_lite->exp_mean_g[i] = ISP3X_RAWAE_LITE_RO_MEAN_G(val);
+ ae_lite->exp_mean_b[i] = ISP3X_RAWAE_LITE_RO_MEAN_B(val);
+ }
+
+ /*
+ * The done bit is never set in the register; set it here to signal
+ * done to userspace
+ */
+ ae_lite->done = 1;
+}
+
+static void rkisp2_stats_hist_read(struct rkisp2_stats *stats, u32 reg_base,
+ struct rkisp2_isp_hist *hist)
+{
+ struct rkisp2_device *rkisp2 = stats->rkisp2;
+ unsigned int i;
+ u32 val, done;
+ unsigned int ctrl = reg_base + ISP_RAWHIST_BIG_CTRL;
+
+ /*
+ * Unlike rawae lite, this actually does get set, and we need to use it
+ * to determine which big block to process
+ */
+ done = rkisp2_read(rkisp2, ctrl) & ISP_RAWHIST_CTRL_MEAS_DONE;
+ hist->done = done ? 1 : 0;
+ if (!done)
+ return;
+
+ rkisp2_write(rkisp2, reg_base + ISP_RAWHIST_BIG_HRAM_CTRL,
+ ISP_RAWHIST_RAM_OFFSET(0));
+
+ for (i = 0; i < RKISP2_ISP_HIST_BIN_N_MAX; i++) {
+ val = rkisp2_read(rkisp2, reg_base + ISP_RAWHIST_BIG_RO_BASE_BIN);
+ hist->hist_bins[i] = val;
+ }
+
+ /* Set the done bit */
+ val = rkisp2_read(rkisp2, ctrl);
+ rkisp2_write(rkisp2, ctrl, val | ISP_RAWHIST_CTRL_MEAS_DONE);
+}
+
+static void rkisp2_stats_get_hist(struct rkisp2_stats *stats,
+ u32 status,
+ struct rkisp2_stats_buffer *pbuf)
+{
+ /*
+ * It seems that big only triggers the big interrupt, and lite only
+ * triggers the ch0 interrupts. ch1 and ch2 interrupts are therefore
+ * unknown, and we need to check the done bits of every big module to
+ * determine which to process
+ */
+
+ /*
+ * It looks like we get separate interrupts for big in big-mode (ie.
+ * using the 15x15 grid) and for non-big stuff
+ */
+
+ if (status & ISP2X_3A_RAWHIST_CH0) {
+ stats->rkisp2->debug.stats3a_hist_ch0_count++;
+ stats->icr |= ISP2X_3A_RAWHIST_CH0;
+ rkisp2_stats_hist_read(stats, ISP_RAWHIST_LITE_BASE, &pbuf->hist_lite);
+ }
+
+ if (status & ISP2X_3A_RAWHIST_BIG) {
+ stats->rkisp2->debug.stats3a_hist_big_count++;
+ stats->icr |= ISP2X_3A_RAWHIST_BIG;
+ rkisp2_stats_hist_read(stats, ISP_RAWHIST_BIG1_BASE, &pbuf->hist_big0);
+ rkisp2_stats_hist_read(stats, ISP_RAWHIST_BIG2_BASE, &pbuf->hist_big1);
+ rkisp2_stats_hist_read(stats, ISP_RAWHIST_BIG3_BASE, &pbuf->hist_big2);
+ }
+
+}
+
+static void rkisp2_stats_get_rawawb(struct rkisp2_stats *stats,
+ u32 status,
+ struct rkisp2_stats_buffer *pbuf)
+{
+ struct rkisp2_device *rkisp2 = stats->rkisp2;
+ struct rkisp2_isp_awb *awb = &pbuf->awb;
+ unsigned int ctrl = ISP21_RAWAWB_CTRL;
+ unsigned int i;
+ u32 val1, val2;
+ u32 done;
+
+ if (!(status & ISP2X_3A_RAWAWB))
+ return;
+ stats->icr |= ISP2X_3A_RAWAWB;
+
+ rkisp2->debug.stats3a_awb_count++;
+
+ done = rkisp2_read(rkisp2, ctrl) & ISP3X_RAWAWB_CTRL_MEAS_DONE;
+ awb->done = done ? 1 : 0;
+ if (!done)
+ return;
+
+ rkisp2->debug.stats3a_awb_done_count++;
+
+ for (i = 0; i < RKISP2_ISP_AWB_COUNTS_SIZE; i++) {
+ val1 = rkisp2_read(rkisp2, ISP21_RAWAWB_RAM_DATA_BASE);
+ val2 = rkisp2_read(rkisp2, ISP21_RAWAWB_RAM_DATA_BASE);
+ awb->counts_r[i] = (val2 >> 4) & 0x3ffff;
+ awb->counts_g[i] = (val1 >> 18) | ((val2 & 0xf) << 14);
+ awb->counts_b[i] = val1 & 0x3ffff;
+ awb->counts_w[i] = val2 >> 22;
+ }
+
+ /*
+ * Clear the done bit (reference says write 0 but writing 1 seems to be
+ * the correct reset, plus all the other stats 3a write 1 to reset)
+ */
+ val1 = rkisp2_read(rkisp2, ctrl);
+ rkisp2_write(rkisp2, ctrl, val1 | ISP3X_RAWAWB_CTRL_MEAS_DONE);
+}
+
+/* This is always called in an intterupt context */
+static struct rkisp2_buffer *rkisp2_stats_get_buf(struct rkisp2_stats *stats)
+{
+ struct rkisp2_buffer *ret = NULL;
+
+ if (stats->cur_buf != NULL)
+ return stats->cur_buf;
+
+ /* get one empty buffer */
+ if (!list_empty(&stats->stat)) {
+ ret = list_first_entry(&stats->stat, struct rkisp2_buffer, queue);
+ list_del(&ret->queue);
+ }
+
+ stats->cur_buf = ret;
+
+ return ret;
+}
+
+static void rkisp2_stats_complete_buf(struct rkisp2_stats *stats, struct rkisp2_buffer *buf)
+{
+ unsigned int frame_sequence = stats->rkisp2->isp.frame_sequence;
+ u64 timestamp = ktime_get_ns();
+
+ vb2_set_plane_payload(&buf->vb.vb2_buf, 0,
+ sizeof(struct rkisp2_stats_buffer));
+ buf->vb.sequence = frame_sequence;
+ buf->vb.vb2_buf.timestamp = timestamp;
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+
+ stats->cur_buf = NULL;
+}
+
+static void rkisp2_stats_send_measurement_3a(struct rkisp2_stats *stats, u32 status)
+{
+ struct rkisp2_stats_buffer *cur_stat_buf;
+ struct rkisp2_buffer *cur_buf;
+
+ cur_buf = rkisp2_stats_get_buf(stats);
+ if (!cur_buf)
+ return;
+
+ cur_stat_buf = (struct rkisp2_stats_buffer *)
+ vb2_plane_vaddr(&cur_buf->vb.vb2_buf, 0);
+
+ rkisp2_stats_get_rawae_lite(stats, status, cur_stat_buf);
+
+ rkisp2_stats_get_hist(stats, status, cur_stat_buf);
+
+ rkisp2_stats_get_rawawb(stats, status, cur_stat_buf);
+
+ rkisp2_write(stats->rkisp2, ISP_ISP3A_ICR, stats->icr);
+
+ if (stats->imsc == stats->icr) {
+ rkisp2_stats_complete_buf(stats, cur_buf);
+ stats->icr = 0;
+ }
+}
+
+void rkisp2_stats_isr_v_start(struct rkisp2_stats *stats)
+{
+ if (stats->imsc != stats->icr && stats->cur_buf != NULL) {
+ WARN_ONCE(1, "unhandled stats irq: expected %x got %x\n",
+ stats->imsc, stats->icr);
+ stats->rkisp2->debug.stats_irq_delay++;
+
+ /*
+ * If we are in this block then it means the stats buffer has
+ * not been completed in rkisp2_stats_send_measurement_3a, so
+ * complete it here.
+ */
+ spin_lock(&stats->lock);
+ rkisp2_stats_complete_buf(stats, stats->cur_buf);
+ spin_unlock(&stats->lock);
+ }
+
+ /* TODO do we need locking for these two fields? */
+ stats->imsc = rkisp2_read(stats->rkisp2, ISP_ISP3A_IMSC);
+ stats->icr = 0;
+}
+
+/* TODO maybe we can just return void */
+irqreturn_t rkisp2_stats_isr_3a(struct rkisp2_stats *stats)
+{
+ struct rkisp2_device *rkisp2 = stats->rkisp2;
+ u32 status;
+
+ status = rkisp2_read(rkisp2, ISP_ISP3A_MIS);
+ if (!status)
+ return IRQ_NONE;
+
+ spin_lock(&stats->lock);
+
+ rkisp2->debug.stats3a_irq++;
+
+ if (status & stats->imsc)
+ rkisp2_stats_send_measurement_3a(stats, status);
+
+ spin_unlock(&stats->lock);
+
+ return IRQ_HANDLED;
+}
+
+static void rkisp2_init_stats(struct rkisp2_stats *stats)
+{
+ stats->vdev_fmt.fmt.meta.dataformat =
+ V4L2_META_FMT_RKISP2_STATS;
+ stats->vdev_fmt.fmt.meta.buffersize =
+ sizeof(struct rkisp2_stats_buffer);
+}
+
+int rkisp2_stats_register(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_stats *stats = &rkisp2->stats;
+ struct rkisp2_vdev_node *node = &stats->vnode;
+ struct video_device *vdev = &node->vdev;
+ int ret;
+
+ stats->rkisp2 = rkisp2;
+ mutex_init(&node->vlock);
+ INIT_LIST_HEAD(&stats->stat);
+ spin_lock_init(&stats->lock);
+
+ strscpy(vdev->name, RKISP2_STATS_DEV_NAME, sizeof(vdev->name));
+
+ video_set_drvdata(vdev, stats);
+ vdev->ioctl_ops = &rkisp2_stats_ioctl;
+ vdev->fops = &rkisp2_stats_fops;
+ vdev->release = video_device_release_empty;
+ vdev->lock = &node->vlock;
+ vdev->v4l2_dev = &rkisp2->v4l2_dev;
+ vdev->queue = &node->buf_queue;
+ vdev->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING;
+ vdev->vfl_dir = VFL_DIR_RX;
+ rkisp2_stats_init_vb2_queue(vdev->queue, stats);
+ rkisp2_init_stats(stats);
+ video_set_drvdata(vdev, stats);
+
+ node->pad.flags = MEDIA_PAD_FL_SINK;
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret)
+ goto error;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(&vdev->dev,
+ "failed to register %s, ret=%d\n", vdev->name, ret);
+ goto error;
+ }
+
+ return 0;
+
+error:
+ media_entity_cleanup(&vdev->entity);
+ mutex_destroy(&node->vlock);
+ stats->rkisp2 = NULL;
+ return ret;
+}
+
+void rkisp2_stats_unregister(struct rkisp2_device *rkisp2)
+{
+ struct rkisp2_stats *stats = &rkisp2->stats;
+ struct rkisp2_vdev_node *node = &stats->vnode;
+ struct video_device *vdev = &node->vdev;
+
+ if (!stats->rkisp2)
+ return;
+
+ vb2_video_unregister_device(vdev);
+ media_entity_cleanup(&vdev->entity);
+ mutex_destroy(&node->vlock);
+}
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index 470e5b84ed15..1b5776487991 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1468,6 +1468,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A Statistics"; break;
case V4L2_META_FMT_RK_ISP1_EXT_PARAMS: descr = "Rockchip ISP1 Ext 3A Params"; break;
case V4L2_META_FMT_RKISP2_PARAMS: descr = "Rockchip ISP2 3A Parameters"; break;
+ case V4L2_META_FMT_RKISP2_STATS: descr = "Rockchip ISP2 3A Statistics"; break;
case V4L2_META_FMT_C3ISP_PARAMS: descr = "Amlogic C3 ISP Parameters"; break;
case V4L2_META_FMT_C3ISP_STATS: descr = "Amlogic C3 ISP Statistics"; break;
case V4L2_META_FMT_MALI_C55_PARAMS: descr = "ARM Mali-C55 ISP Parameters"; break;
diff --git a/include/uapi/linux/rkisp2-config.h b/include/uapi/linux/rkisp2-config.h
index 0e42dbf2c9f2..a45fe79a7716 100644
--- a/include/uapi/linux/rkisp2-config.h
+++ b/include/uapi/linux/rkisp2-config.h
@@ -20,6 +20,17 @@
#define RKISP2_ISP_LSC_SAMPLES_MAX 17
#define RKISP2_ISP_LSC_SECTORS_TBL_SIZE_MAX 16
+#define RKISP2_ISP_AE_MEAN_MAX_LITE 25
+#define RKISP2_ISP_AE_MEAN_MAX_BIG 225
+
+#define RKISP2_ISP_HIST_WEIGHT_GRIDS_SIZE_LITE 25
+#define RKISP2_ISP_HIST_WEIGHT_GRIDS_SIZE_BIG 225
+#define RKISP2_ISP_HIST_WEIGHT_GRIDS_SIZE_MAX RKISP2_ISP_HIST_WEIGHT_GRIDS_SIZE_BIG
+
+#define RKISP2_ISP_HIST_BIN_N_MAX 256
+
+#define RKISP2_ISP_AWB_COUNTS_SIZE 225
+
/**
* enum rkisp2_isp_version - ISP variants
*
@@ -55,6 +66,98 @@ enum rkisp2_isp_set_active_table_when {
RKISP2_ISP_LSC_SET_ACTIVE_TABLE_BEFORE,
};
+enum rkisp2_isp_histogram_mode {
+ RKISP2_ISP_HISTOGRAM_MODE_DISABLE,
+ RKISP2_ISP_HISTOGRAM_MODE_R_HISTOGRAM = 2,
+ RKISP2_ISP_HISTOGRAM_MODE_G_HISTOGRAM,
+ RKISP2_ISP_HISTOGRAM_MODE_B_HISTOGRAM,
+ RKISP2_ISP_HISTOGRAM_MODE_Y_HISTOGRAM
+};
+
+/*
+ * This selects which bits are used from the input data to compute the
+ * histogram
+ */
+enum rkisp2_isp_histogram_data_sel {
+ RKISP2_ISP_HISTOGRAM_DATA_SEL_11_4,
+ RKISP2_ISP_HISTOGRAM_DATA_SEL_10_3,
+ RKISP2_ISP_HISTOGRAM_DATA_SEL_9_2,
+ RKISP2_ISP_HISTOGRAM_DATA_SEL_8_1,
+ RKISP2_ISP_HISTOGRAM_DATA_SEL_7_0,
+};
+
+/*---------- Statistics ------------*/
+
+/**
+ * struct rkisp2_isp_ae_lite - statistics auto exposure data
+ *
+ * @exp_mean_r: Mean luminance value of block xy for r channel
+ * @exp_mean_g: Mean luminance value of block xy for g channel
+ * @exp_mean_b: Mean luminance value of block xy for b channel
+ * @done: This set to nonzero when the stats are ready
+ *
+ * Image is divided into 5x5 blocks on lite and 15x15 blocks on big.
+ */
+struct rkisp2_isp_ae_lite {
+ __u16 exp_mean_r[RKISP2_ISP_AE_MEAN_MAX_LITE];
+ __u16 exp_mean_g[RKISP2_ISP_AE_MEAN_MAX_LITE];
+ __u16 exp_mean_b[RKISP2_ISP_AE_MEAN_MAX_LITE];
+ __u8 done;
+};
+
+/**
+ * struct rkisp2_cif_isp_hist_stat - statistics histogram data
+ *
+ * @hist_bins: measured bin counters. Each bin is a 28 bits unsigned fixed point
+ * type. Bits 0-4 are the fractional part and bits 5-27 are the
+ * integer part.
+ * @done: This set to nonzero when the stats are ready
+ *
+ * There are 256 bins, at least on 3.x.
+ */
+struct rkisp2_isp_hist {
+ __u32 hist_bins[RKISP2_ISP_HIST_BIN_N_MAX];
+ __u8 done;
+};
+
+/**
+ * struct rkisp2_isp_awb - statistics auto white balance data
+ *
+ * @counts_r: Counts of red (18-bits)
+ * @counts_g: Counts of green (18-bits)
+ * @counts_b: Counts of blue (18-bits)
+ * @counts_w: Counts of white point (10-bits)
+ * @done: This set to nonzero when the stats are ready
+ *
+ * TODO Figure out what is being counted
+ */
+struct rkisp2_isp_awb {
+ __u32 counts_r[RKISP2_ISP_AWB_COUNTS_SIZE];
+ __u32 counts_g[RKISP2_ISP_AWB_COUNTS_SIZE];
+ __u32 counts_b[RKISP2_ISP_AWB_COUNTS_SIZE];
+ __u16 counts_w[RKISP2_ISP_AWB_COUNTS_SIZE];
+ __u8 done;
+};
+
+/**
+ * struct rkisp2_stats_buffer - 3A statistics for the RkISP2
+ *
+ * @ae_lite: ae lite stats
+ * @hist_lite: histogram lite stats
+ * @hist_big0: histogram big0 stats
+ * @hist_big1: histogram big0 stats
+ * @hist_big2: histogram big0 stats
+ * @awb: awb stats
+ */
+struct rkisp2_stats_buffer {
+ struct rkisp2_isp_ae_lite ae_lite;
+ struct rkisp2_isp_hist hist_lite;
+ struct rkisp2_isp_hist hist_big0;
+ struct rkisp2_isp_hist hist_big1;
+ struct rkisp2_isp_hist hist_big2;
+ struct rkisp2_isp_awb awb;
+};
+
/*---------- Parameters ------------*/
/**
@@ -66,6 +169,12 @@ enum rkisp2_isp_set_active_table_when {
* @RKISP2_PARAMS_BLOCK_CCM: Color correction matrix (in the CCM block)
* @RKISP2_PARAMS_BLOCK_GOC: Gamma out correction
* @RKISP2_PARAMS_BLOCK_LSC: Lens shading correction
+ * @RKISP2_PARAMS_BLOCK_AE_LITE: AE measurement config (lite)
+ * @RKISP2_PARAMS_BLOCK_HIST_LITE: Histogram measurement config (lite)
+ * @RKISP2_PARAMS_BLOCK_HIST_BIG0: Histogram measurement config (zeroth big block)
+ * @RKISP2_PARAMS_BLOCK_HIST_BIG1: Histogram measurement config (first big block)
+ * @RKISP2_PARAMS_BLOCK_HIST_BIG2: Histogram measurement config (second big block)
+ * @RKISP2_PARAMS_BLOCK_AWB_MEAS: AWB measurements config
* */
enum rkisp2_params_block_type {
RKISP2_PARAMS_BLOCK_BLS,
@@ -74,6 +183,12 @@ enum rkisp2_params_block_type {
RKISP2_PARAMS_BLOCK_CCM,
RKISP2_PARAMS_BLOCK_GOC,
RKISP2_PARAMS_BLOCK_LSC,
+ RKISP2_PARAMS_BLOCK_AE_LITE,
+ RKISP2_PARAMS_BLOCK_HIST_LITE,
+ RKISP2_PARAMS_BLOCK_HIST_BIG0,
+ RKISP2_PARAMS_BLOCK_HIST_BIG1,
+ RKISP2_PARAMS_BLOCK_HIST_BIG2,
+ RKISP2_PARAMS_BLOCK_AWB_MEAS,
};
/**
@@ -134,6 +249,36 @@ struct rkisp2_isp_awb_gains {
__u16 gb;
};
+/**
+ * struct rkisp2_isp_color_cc - Color coefficients
+ *
+ * @r: Red coefficient
+ * @g: Green coefficient
+ * @b: Blue coefficient
+ */
+struct rkisp2_isp_color_cc {
+ __u8 r;
+ __u8 g;
+ __u8 b;
+};
+
+/**
+ * struct rkisp2_isp_awb_color_quad - Group of RGB and luminance for AWB
+ *
+ * TODO redesign this?
+ *
+ * @r: Red
+ * @g: Green
+ * @b: Blue
+ * @y: Y (luminance)
+ */
+struct rkisp2_isp_awb_color_quad {
+ __u8 r;
+ __u8 g;
+ __u8 b;
+ __u8 y;
+};
+
/**
* struct rkisp2_params_bls - RkISP2 params BLS config
*
@@ -323,12 +468,98 @@ struct rkisp2_params_lsc {
__u8 window_mode;
};
+/**
+ * struct rkisp2_params_ae_lite - RKISP2 params AE lite config
+ *
+ * RkISP2 parameters auto exposure measurement configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_AE_LITE`.
+ *
+ * TODO change window_num to enum?
+ *
+ * @header: The RkISP2 parameters block header
+ * @window_num: 0 for 1x1, 1 for 5x5
+ * @meas_window: Size of measurement window. First window for 5x5.
+ */
+struct rkisp2_params_ae_lite {
+ struct v4l2_isp_params_block_header header;
+ __u8 window_num;
+ struct rkisp2_isp_window meas_window;
+} __attribute__((aligned(8)));
+
+/**
+ * struct rkisp2_params_hist_lite RKISP2 params histogram lite config
+ *
+ * RkISP2 parameters histogram configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_HIST_LITE`.
+ *
+ * @header: The RkISP2 parameters block header
+ * @data_sel: Data selection mode (from enum rkisp2_isp_histogram_data_sel)
+ * @mode: Histogram mode (from enum rkisp2_isp_histogram_mode)
+ * @stepsize: Predivider (count every <stepsize> pixel)
+ * @waterline: Waterline for region statics
+ * @coeffs: Coefficients for raw2y formula
+ * @meas_window: Size of first measurement subwindow
+ * @weights: Weights
+ */
+struct rkisp2_params_hist_lite {
+ struct v4l2_isp_params_block_header header;
+ __u8 data_sel;
+ __u8 mode;
+ __u8 stepsize;
+ __u16 waterline;
+ struct rkisp2_isp_color_cc coeffs;
+ struct rkisp2_isp_window meas_window;
+ __u8 weights[RKISP2_ISP_HIST_WEIGHT_GRIDS_SIZE_LITE];
+} __attribute__((aligned(8)));
+
+/**
+ * Same as struct rkisp2_params_hist_lite but for big channel
+ *
+ * RkISP2 parameters histogram configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_HIST_BIG{0,1,2}`.
+ *
+ * @window_num: 0 or 1 for 5x5, 2 or 3 for 15x15
+ */
+struct rkisp2_params_hist_big {
+ struct v4l2_isp_params_block_header header;
+ __u8 window_num;
+ __u8 data_sel;
+ __u8 mode;
+ __u8 stepsize;
+ __u16 waterline;
+ struct rkisp2_isp_color_cc coeffs;
+ struct rkisp2_isp_window meas_window;
+ __u8 weights[RKISP2_ISP_HIST_WEIGHT_GRIDS_SIZE_BIG];
+} __attribute__((aligned(8)));
+
+/**
+ * struct rkisp2_params_awb_meas - Configuration used by rawawb
+ *
+ * RkISP2 parameters AWB measurement configuration block.
+ * Identified by :c:type:`RKISP2_PARAMS_BLOCK_AWB_MEAS`.
+ *
+ * @header: The RkISP2 parameters block header
+ * @meas_window: Size of first measurement subwindow (13 bits)
+ * @limits: Limits for white point detection [min, max] (8 bits)
+ * @weights: Weights (6-bits)
+ */
+struct rkisp2_params_awb_meas {
+ struct v4l2_isp_params_block_header header;
+ struct rkisp2_isp_window meas_window;
+ struct rkisp2_isp_awb_color_quad limits[2];
+ __u8 weights[RKISP2_ISP_AWB_COUNTS_SIZE];
+};
+
#define RKISP2_PARAMS_MAX_SIZE \
(sizeof(struct rkisp2_params_bls) +\
sizeof(struct rkisp2_params_awb_gains) +\
sizeof(struct rkisp2_params_csm) +\
sizeof(struct rkisp2_params_ccm) +\
sizeof(struct rkisp2_params_goc) +\
- sizeof(struct rkisp2_params_lsc))
+ sizeof(struct rkisp2_params_lsc) +\
+ sizeof(struct rkisp2_params_ae_lite) +\
+ sizeof(struct rkisp2_params_hist_lite) +\
+ sizeof(struct rkisp2_params_hist_big) * 3 +\
+ sizeof(struct rkisp2_params_awb_meas))
#endif /* _UAPI_RKISP2_CONFIG_H */
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 1d418a752d89..399f4d73af15 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -878,6 +878,7 @@ struct v4l2_pix_format {
/* Vendor specific - used for RKISP2 camera sub-system */
#define V4L2_META_FMT_RKISP2_PARAMS v4l2_fourcc('R', 'K', '2', 'P') /* Rockchip ISP2 Parameters */
+#define V4L2_META_FMT_RKISP2_STATS v4l2_fourcc('R', 'K', '2', 'S') /* Rockchip ISP2 3A Statistics */
/* Vendor specific - used for C3_ISP */
#define V4L2_META_FMT_C3ISP_PARAMS v4l2_fourcc('C', '3', 'P', 'M') /* Amlogic C3 ISP Parameters */
--
2.47.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings
2026-04-24 17:58 ` [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings Paul Elder
@ 2026-04-24 18:05 ` Paul Elder
0 siblings, 0 replies; 8+ messages in thread
From: Paul Elder @ 2026-04-24 18:05 UTC (permalink / raw)
To: laurent.pinchart
Cc: michael.riesch, xuhf, stefan.klug, linux-media, linux-arm-kernel,
linux-rockchip, linux-kernel, Heiko Stuebner
Hi me,
Quoting Paul Elder (2026-04-25 02:58:46)
> Add documentation for the Rockchip rkisp2 bindings. This is meant to
> support multiple versions of Rockchip ISPs going forward, including the
> 2.x series and 3.x series. The current version only adds the compatible
> for the RK3588, which is a 3.0.
>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> ---
> .../bindings/media/rockchip-isp2.yaml | 127 ++++++++++++++++++
> 1 file changed, 127 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp2.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/rockchip-isp2.yaml b/Documentation/devicetree/bindings/media/rockchip-isp2.yaml
> new file mode 100644
> index 000000000000..f4ef089adf6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/rockchip-isp2.yaml
> @@ -0,0 +1,127 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/rockchip-isp2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip SoC Image Signal Processing unit v2
> +
> +maintainers:
> + - Paul Elder <paul.elder@ideasonboard.com>
> +
> +description: |
> + Rockchip ISP2 is the Camera interface for the Rockchip series of SoCs which
> + contains image processing, scaling, and compression functions.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3588-isp
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 3
> + maxItems: 3
These should be 2.
> +
> + interrupt-names:
> + items:
> + - const: isp_irq
> + - const: mi_irq
> +
> + clocks:
> + minItems: 3
> + items:
> + - description: ISP AXI clock (aclk)
> + - description: ISP AHB clock (hclk)
> + - description: ISP core clock (isp)
> + # for rk3588
> + - description: ISP core clock (marvin)
> + - description: ISP core clock (vicap)
> +
> + clock-names:
> + minItems: 3
> + items:
> + - const: aclk
> + - const: hclk
> + - const: clk_core
> + # for rk3588
> + - const: clk_core_marvin
> + - const: clk_core_vicap
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + minItems: 1
This can be removed.
> + items:
> + - description: ISP power domain
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: connection point for VICAP in inline mode
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + required:
> + - port@0
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - power-domains
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: rockchip,rk3588-isp
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + clock-names:
> + minItems: 5
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/rk3588-power.h>
> +
> + parent0: parent {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp0: isp@fdcb0000 {
> + compatible = "rockchip,rk3588-isp";
> + reg = <0x0 0xfdcb0000 0x0 0x7f00>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "isp_irq", "mi_irq";
I removed the interrupt name and forgot to remove the interrupt.
I think the same problem is present in the dt node in the next patch.
Paul
> + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
> + <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
> + <&cru CLK_ISP0_CORE_VICAP>;
> + clock-names = "aclk", "hclk", "clk_core",
> + "clk_core_marvin", "clk_core_vicap";
> + power-domains = <&power RK3588_PD_VI>;
> + iommus = <&isp0_mmu>;
> + };
> + };
> --
> 2.47.2
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588
2026-04-24 17:58 ` [RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588 Paul Elder
@ 2026-04-24 23:00 ` Laurent Pinchart
0 siblings, 0 replies; 8+ messages in thread
From: Laurent Pinchart @ 2026-04-24 23:00 UTC (permalink / raw)
To: Paul Elder
Cc: Xu Hongfei, michael.riesch, stefan.klug, linux-media,
linux-arm-kernel, linux-rockchip, linux-kernel, Heiko Stuebner
Hi Paul,
Thank you for the patch.
On Sat, Apr 25, 2026 at 02:58:47AM +0900, Paul Elder wrote:
> From: Xu Hongfei <xuhf@rock-chips.com>
>
> Add device tree nodes for the ISP and their iommus on the RK3588.
>
> Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 8b98e5c3cc8b..607b03d55dfd 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -3535,6 +3535,66 @@ gpio4: gpio@fec50000 {
> #interrupt-cells = <2>;
> };
> };
> +
> + isp0: isp@fdcb0000 {
> + compatible = "rockchip,rk3588-isp";
> + reg = <0x0 0xfdcb0000 0x0 0x7f00>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "isp_irq", "mi_irq";
> + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
> + <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
> + <&cru CLK_ISP0_CORE_VICAP>;
> + clock-names = "aclk", "hclk", "clk_core",
> + "clk_core_marvin", "clk_core_vicap";
> + power-domains = <&power RK3588_PD_VI>;
> + iommus = <&isp0_mmu>;
> + status = "disabled";
> + };
> +
> + isp0_mmu: iommu@fdcb7f00 {
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdcb7f00 0x0 0x100>;
> + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "isp0_mmu";
I don't think interrupt-names is needed. Same for the second IOMMU.
> + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3588_PD_VI>;
> + #iommu-cells = <0>;
> + rockchip,disable-mmu-reset;
> + status = "disabled";
> + };
> +
> + isp1: isp@fdcc0000 {
> + compatible = "rockchip,rk3588-isp";
> + reg = <0x0 0xfdcc0000 0x0 0x7f00>;
> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "isp_irq", "mi_irq";
> + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
> + <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>,
> + <&cru CLK_ISP1_CORE_VICAP>;
> + clock-names = "aclk", "hclk", "clk_core",
> + "clk_core_marvin", "clk_core_vicap";
> + power-domains = <&power RK3588_PD_ISP1>;
> + iommus = <&isp1_mmu>;
> + status = "disabled";
> + };
> +
> + isp1_mmu: iommu@fdcc7f00 {
> + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> + reg = <0x0 0xfdcc7f00 0x0 0x100>;
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "isp1_mmu";
> + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
> + clock-names = "aclk", "iface";
> + power-domains = <&power RK3588_PD_ISP1>;
> + #iommu-cells = <0>;
> + rockchip,disable-mmu-reset;
> + status = "disabled";
> + };
> };
>
> #include "rk3588-base-pinctrl.dtsi"
--
Regards,
Laurent Pinchart
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-04-24 23:00 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-04-24 17:58 [RFC PATCH 0/5] media: rockchip: rkisp2: Add driver for ISP on Rk3588 Paul Elder
2026-04-24 17:58 ` [RFC PATCH 1/5] media: dt-bindings: Add rockchip rkisp2 bindings Paul Elder
2026-04-24 18:05 ` Paul Elder
2026-04-24 17:58 ` [RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588 Paul Elder
2026-04-24 23:00 ` Laurent Pinchart
2026-04-24 17:58 ` [RFC PATCH 3/5] media: rockchip: rkisp2: Add rkisp2 driver Paul Elder
2026-04-24 17:58 ` [RFC PATCH 4/5] media: rkisp2: Add parameters output video node Paul Elder
2026-04-24 17:58 ` [RFC PATCH 5/5] media: rkisp2: Add statistics capture " Paul Elder
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