From: Robin Murphy <robin.murphy@arm.com>
To: Sebastian Reichel <sebastian.reichel@collabora.com>,
Tomeu Vizoso <tomeu@tomeuvizoso.net>
Cc: "Joerg Roedel" <joro@8bytes.org>, "Will Deacon" <will@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Oded Gabbay" <ogabbay@kernel.org>,
"Tomeu Vizoso" <tomeu.vizoso@tomeuvizoso.net>,
"David Airlie" <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org
Subject: Re: [PATCH 2/9] iommu/rockchip: Attach multiple power domains
Date: Fri, 14 Jun 2024 13:07:29 +0100 [thread overview]
Message-ID: <3516994c-7b06-4409-b9a9-975b9f7a60eb@arm.com> (raw)
In-Reply-To: <vmgk4wmlxbsb7lphq2ep3xnxx3mbv6e6lecihtftxoyp5lidvy@mectcwirrlek>
On 2024-06-13 10:38 pm, Sebastian Reichel wrote:
> Hi,
>
> On Thu, Jun 13, 2024 at 11:34:02AM GMT, Tomeu Vizoso wrote:
>> On Thu, Jun 13, 2024 at 11:24 AM Tomeu Vizoso <tomeu@tomeuvizoso.net> wrote:
>>> On Thu, Jun 13, 2024 at 2:05 AM Sebastian Reichel
>>> <sebastian.reichel@collabora.com> wrote:
>>>> On Wed, Jun 12, 2024 at 03:52:55PM GMT, Tomeu Vizoso wrote:
>>>>> IOMMUs with multiple base addresses can also have multiple power
>>>>> domains.
>>>>>
>>>>> The base framework only takes care of a single power domain, as some
>>>>> devices will need for these power domains to be powered on in a specific
>>>>> order.
>>>>>
>>>>> Use a helper function to stablish links in the order in which they are
>>>>> in the DT.
>>>>>
>>>>> This is needed by the IOMMU used by the NPU in the RK3588.
>>>>>
>>>>> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
>>>>> ---
>>>>
>>>> To me it looks like this is multiple IOMMUs, which should each get
>>>> their own node. I don't see a good reason for merging these
>>>> together.
>>>
>>> I have made quite a few attempts at splitting the IOMMUs and also the
>>> cores, but I wasn't able to get things working stably. The TRM is
>>> really scant about how the 4 IOMMU instances relate to each other, and
>>> what the fourth one is for.
>>>
>>> Given that the vendor driver treats them as a single IOMMU with four
>>> instances and we don't have any information on them, I resigned myself
>>> to just have them as a single device.
>>>
>>> I would love to be proved wrong though and find a way fo getting
>>> things stably as different devices so they can be powered on and off
>>> as needed. We could save quite some code as well.
>>
>> FWIW, here a few ways how I tried to structure the DT nodes, none of
>> these worked reliably:
>>
>> https://gitlab.freedesktop.org/tomeu/linux/-/blob/6.10-rocket-multiple-devices-power/arch/arm64/boot/dts/rockchip/rk3588s.dtsi?ref_type=heads#L1163
>> https://gitlab.freedesktop.org/tomeu/linux/-/blob/6.10-rocket-schema-subnodes//arch/arm64/boot/dts/rockchip/rk3588s.dtsi?ref_type=heads#L1162
>> https://gitlab.freedesktop.org/tomeu/linux/-/blob/6.10-rocket-multiple-devices//arch/arm64/boot/dts/rockchip/rk3588s.dtsi?ref_type=heads#L1163
>> https://gitlab.freedesktop.org/tomeu/linux/-/blob/6.10-rocket-multiple-iommus//arch/arm64/boot/dts/rockchip/rk3588s.dtsi?ref_type=heads#L2669
>>
>> I can very well imagine I missed some way of getting this to work, but
>> for every attempt, the domains, iommus and cores were resumed in
>> different orders that presumably caused problems during concurrent
>> execution fo workloads.
>>
>> So I fell back to what the vendor driver does, which works reliably
>> (but all cores have to be powered on at the same time).
>
> Mh. The "6.10-rocket-multiple-iommus" branch seems wrong. There is
> only one iommu node in that. I would have expected a test with
>
> rknn {
> // combined device
>
> iommus = <&iommu1>, <&iommu2>, ...;
> };
>
> Otherwise I think I would go with the schema-subnodes variant. The
> driver can initially walk through the sub-nodes and collect the
> resources into the main device, so on the driver side nothing would
> really change. But that has a couple of advantages:
>
> 1. DT and DT binding are easier to read
> 2. It's similar to e.g. CPU cores each having their own node
> 3. Easy to extend to more cores in the future
> 4. The kernel can easily switch to proper per-core device model when
> the problem has been identified
It also would seem to permit describing and associating the per-core
IOMMUs individually - apart from core 0's apparent coupling to whatever
shared "uncore" stuff exists for the whole thing, from the distinct
clocks, interrupts, power domains etc. lining up with each core I'd
guess those IOMMUs are not interrelated the same way the ISP's
read/write IOMMUs are (which was the main justification for adopting the
multiple-reg design originally vs. distinct DT nodes like Exynos does).
However, practically that would require the driver to at least populate
per-core child devices to make DMA API or IOMMU API mappings with, since
we couldn't spread the "collect the resources" trick into those
subsystems as well.
Thanks,
Robin.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2024-06-14 12:07 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 13:52 [PATCH 0/9] New DRM accel driver for Rockchip's RKNN NPU Tomeu Vizoso
2024-06-12 13:52 ` [PATCH 1/9] iommu/rockchip: Add compatible for rockchip,rk3588-iommu Tomeu Vizoso
2024-06-12 23:37 ` Sebastian Reichel
2024-06-12 13:52 ` [PATCH 2/9] iommu/rockchip: Attach multiple power domains Tomeu Vizoso
2024-06-13 0:05 ` Sebastian Reichel
2024-06-13 9:24 ` Tomeu Vizoso
2024-06-13 9:34 ` Tomeu Vizoso
2024-06-13 21:38 ` Sebastian Reichel
2024-06-14 12:07 ` Robin Murphy [this message]
2024-09-11 11:07 ` Tomeu Vizoso
2024-09-11 11:03 ` Tomeu Vizoso
2024-06-12 13:52 ` [PATCH 3/9] dt-bindings: mailbox: rockchip,rknn: Add bindings Tomeu Vizoso
2024-06-12 16:33 ` Conor Dooley
2024-06-13 19:15 ` Rob Herring
2024-06-12 13:52 ` [PATCH 4/9] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588s Tomeu Vizoso
2024-06-12 14:24 ` Diederik de Haas
2024-06-13 22:16 ` Sebastian Reichel
2024-06-15 3:32 ` kernel test robot
2024-06-12 13:52 ` [PATCH 5/9] arm64: dts: rockchip: Enable the NPU on quartzpro64 Tomeu Vizoso
2024-06-13 21:48 ` Sebastian Reichel
2024-06-12 13:52 ` [PATCH 6/9] accel/rocket: Add a new driver for Rockchip's NPU Tomeu Vizoso
2024-06-13 2:05 ` kernel test robot
2024-06-13 2:27 ` kernel test robot
2024-06-13 10:55 ` kernel test robot
2024-06-14 16:16 ` Jeffrey Hugo
2024-06-14 20:30 ` Nicolas Dufresne
2024-07-09 7:29 ` Zenghui Yu
2024-06-12 13:53 ` [PATCH 7/9] accel/rocket: Add IOCTL for BO creation Tomeu Vizoso
2024-06-14 16:21 ` Jeffrey Hugo
2024-06-12 13:53 ` [PATCH 8/9] accel/rocket: Add job submission IOCTL Tomeu Vizoso
2024-06-13 9:08 ` kernel test robot
2024-06-14 16:33 ` Jeffrey Hugo
2024-09-11 11:27 ` Markus Elfring
2024-09-11 12:02 ` Markus Elfring
2024-06-12 13:53 ` [PATCH 9/9] accel/rocket: Add IOCTLs for synchronizing memory accesses Tomeu Vizoso
2024-06-12 19:44 ` Friedrich Vock
2024-06-14 16:39 ` Jeffrey Hugo
2024-06-13 17:27 ` [PATCH 0/9] New DRM accel driver for Rockchip's RKNN NPU Rob Herring (Arm)
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