From: Hans Zhang <hans.zhang@cixtech.com>
To: Shawn Lin <shawn.lin@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>,
Manivannan Sadhasivam <mani@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
linux-rockchip@lists.infradead.org,
Niklas Cassel <cassel@kernel.org>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH 3/4] PCI: dw-rockchip: Add L1sub support
Date: Tue, 21 Oct 2025 16:01:51 +0800 [thread overview]
Message-ID: <3f90b0f9-06bb-44d3-97a3-a13ced9b1c3a@cixtech.com> (raw)
In-Reply-To: <1761032907-154829-4-git-send-email-shawn.lin@rock-chips.com>
On 10/21/2025 3:48 PM, Shawn Lin wrote:
> EXTERNAL EMAIL
>
> The driver should set app_clk_req_n(clkreq ready) of PCIE_CLIENT_POWER reg
> to support L1sub. Otherwise, unset app_clk_req_n and pull down CLKREQ#.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 31 ++++++++++++++-----
> 1 file changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 87dd2dd188b4..8a52ff73ec46 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -62,6 +62,12 @@
> /* Interrupt Mask Register Related to Miscellaneous Operation */
> #define PCIE_CLIENT_INTR_MASK_MISC 0x24
>
> +/* Power Management Control Register */
> +#define PCIE_CLIENT_POWER 0x2c
> +#define PCIE_CLKREQ_READY 0x10001
> +#define PCIE_CLKREQ_NOT_READY 0x10000
> +#define PCIE_CLKREQ_PULL_DOWN 0x30001000
> +
> /* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> #define PCIE_LTSSM_APP_DLY2_EN BIT(1)
> @@ -84,6 +90,7 @@ struct rockchip_pcie {
> struct gpio_desc *rst_gpio;
> struct irq_domain *irq_domain;
> const struct rockchip_pcie_of_data *data;
> + bool supports_clkreq;
> };
>
> struct rockchip_pcie_of_data {
> @@ -199,15 +206,21 @@ static bool rockchip_pcie_link_up(struct dw_pcie *pci)
> return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP;
> }
>
> -/*
> - * See e.g. section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0 for the steps
> - * needed to support L1 substates. Currently, not a single rockchip platform
> - * performs these steps, so disable L1 substates until there is proper support.
> - */
> -static void rockchip_pcie_disable_l1sub(struct dw_pcie *pci)
Hi,
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dw-rockchip&id=40331c63e7901a2cc75ce6b5d24d50601efb833d
Mani has already placed this part in the above branch. Can it be removed?
Best regards,
Hans
> +static void rockchip_pcie_enable_l1sub(struct dw_pcie *pci)
> {
> + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> u32 cap, l1subcap;
>
> + /* Enable L1 substates if CLKREQ# is properly connected */
> + if (rockchip->supports_clkreq) {
> + /* Ready to have reference clock removed */
> + rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_READY, PCIE_CLIENT_POWER);
> + return;
> + }
> +
> + /* Otherwise, pull down CLKREQ# and disable L1 substates */
> + rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_PULL_DOWN | PCIE_CLKREQ_NOT_READY,
> + PCIE_CLIENT_POWER);
> cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
> if (cap) {
> l1subcap = dw_pcie_readl_dbi(pci, cap + PCI_L1SS_CAP);
> @@ -282,7 +295,7 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
> irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
> rockchip);
>
> - rockchip_pcie_disable_l1sub(pci);
> + rockchip_pcie_enable_l1sub(pci);
> rockchip_pcie_enable_l0s(pci);
>
> return 0;
> @@ -320,7 +333,7 @@ static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> enum pci_barno bar;
>
> - rockchip_pcie_disable_l1sub(pci);
> + rockchip_pcie_enable_l1sub(pci);
> rockchip_pcie_enable_l0s(pci);
> rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
>
> @@ -432,6 +445,8 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev,
> return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
> "failed to get reset lines\n");
>
> + rockchip->supports_clkreq = of_pci_clkreq_present(pdev->dev.of_node);
> +
> return 0;
> }
>
> --
> 2.43.0
>
>
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next prev parent reply other threads:[~2025-10-21 8:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 7:48 [PATCH 0/4] Add L1 substates support for Rockchip platforms Shawn Lin
2025-10-21 7:48 ` [PATCH 1/4] PCI: of: Add of_pci_clkreq_present() Shawn Lin
2025-10-21 16:16 ` Frank Li
2025-10-22 9:17 ` Shawn Lin
2025-10-22 10:02 ` Manivannan Sadhasivam
2025-10-22 10:13 ` Shawn Lin
2025-10-22 10:29 ` Manivannan Sadhasivam
2025-10-22 16:22 ` Bjorn Helgaas
2025-10-22 17:35 ` Manivannan Sadhasivam
2025-10-22 18:14 ` Bjorn Helgaas
2025-10-21 7:48 ` [PATCH 2/4] PCI: tegra194: Use of_pci_clkreq_present() instead Shawn Lin
2025-10-21 7:48 ` [PATCH 3/4] PCI: dw-rockchip: Add L1sub support Shawn Lin
2025-10-21 8:01 ` Hans Zhang [this message]
2025-10-21 8:42 ` Shawn Lin
2025-10-21 9:03 ` Hans Zhang
2025-10-22 10:34 ` Manivannan Sadhasivam
2025-10-21 7:48 ` [PATCH 4/4] arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1 Shawn Lin
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