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From: "Andy Yan" <andyshrk@163.com>
To: "Heiko Stuebner" <heiko@sntech.de>
Cc: quentin.schulz@theobroma-systems.com, hjc@rock-chips.com,
	 andy.yan@rock-chips.com, dri-devel@lists.freedesktop.org,
	 linux-arm-kernel@lists.infradead.org,
	 linux-rockchip@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	 "Heiko Stuebner" <heiko.stuebner@cherry.de>,
	 sebastian.reichel@collabora.com
Subject: Re:[PATCH 1/2] drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification
Date: Wed, 13 Nov 2024 09:16:49 +0800 (CST)	[thread overview]
Message-ID: <4cbc446f.f07.193231835a1.Coremail.andyshrk@163.com> (raw)
In-Reply-To: <20240425195506.2935955-2-heiko@sntech.de>


+ Sebastina,
Hi Sebastian,  I think you also need this patch when you test DSI on rk3588 with  DSI2 support patch from Heiko.

At 2024-04-26 03:55:05, "Heiko Stuebner" <heiko@sntech.de> wrote:
>From: Heiko Stuebner <heiko.stuebner@cherry.de>
>
>The clock is in Hz while the value checked against is in kHz, so
>actual frequencies will never be able to be below to max value.
>Fix this by specifying the max-value in Hz too.
>
>Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
>Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
>---
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>index 9bee1fd88e6a2..523880a4e8e74 100644
>--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>@@ -1719,7 +1719,7 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
> 		else
> 			dclk_out_rate = v_pixclk >> 2;
> 
>-		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
>+		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
> 		if (!dclk_rate) {
> 			drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
> 				dclk_out_rate);
>@@ -1736,7 +1736,7 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
> 		 * dclk_rate = N * dclk_core_rate N = (1,2,4 ),
> 		 * we get a little factor here
> 		 */
>-		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
>+		dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
> 		if (!dclk_rate) {
> 			drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
> 				dclk_out_rate);
>-- 
>2.39.2
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  parent reply	other threads:[~2024-11-13  1:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-25 19:55 [PATCH 0/2] drm/rockchip: vop2: two fixes from working on DSI enablement Heiko Stuebner
2024-04-25 19:55 ` [PATCH 1/2] drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification Heiko Stuebner
2024-05-03 12:13   ` Quentin Schulz
2024-11-14  0:50     ` Andy Yan
2024-11-14  9:38       ` Quentin Schulz
2024-11-14 10:16         ` Andy Yan
2024-11-13  1:16   ` Andy Yan [this message]
2024-04-25 19:55 ` [PATCH 2/2] drm/rockchip: vop2: configure layers for vp3 on rk3588 Heiko Stuebner
2024-05-03 12:57   ` Quentin Schulz
2024-05-03 13:02     ` Heiko Stübner

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