From: "Andy Yan" <andyshrk@163.com>
To: "Quentin Schulz" <quentin.schulz@cherry.de>
Cc: "Heiko Stuebner" <heiko@sntech.de>,
hjc@rock-chips.com, andy.yan@rock-chips.com,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org,
"Heiko Stuebner" <heiko.stuebner@cherry.de>
Subject: Re:Re: [PATCH 1/2] drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification
Date: Thu, 14 Nov 2024 08:50:20 +0800 (CST) [thread overview]
Message-ID: <72672888.8f9.1932826549b.Coremail.andyshrk@163.com> (raw)
In-Reply-To: <cb73853e-4201-4cc9-9e8a-f977e66241f6@cherry.de>
Hi,
At 2024-05-06 15:44:36, "Quentin Schulz" <quentin.schulz@cherry.de> wrote:
>Hi Heiko,
>
>On 4/25/24 9:55 PM, Heiko Stuebner wrote:
>> From: Heiko Stuebner <heiko.stuebner@cherry.de>
>>
>> The clock is in Hz while the value checked against is in kHz, so
>> actual frequencies will never be able to be below to max value.
>> Fix this by specifying the max-value in Hz too.
>>
>> Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
>> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
>> ---
>> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> index 9bee1fd88e6a2..523880a4e8e74 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>> @@ -1719,7 +1719,7 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
>> else
>> dclk_out_rate = v_pixclk >> 2;
>>
>> - dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
>> + dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
>> if (!dclk_rate) {
>> drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
>
>It seems the error message is incorrect as well and should be saying Hz
>instead of KHz. (note also the lowercase z).
I think kHz is fine, we can find many siminary usage in drm:
drivers/gpu/drm/drm_vblank.c
656: drm_dbg_core(dev, "crtc %u: clock %d kHz framedur %d linedur %d\n",
>
>> dclk_out_rate);
>> @@ -1736,7 +1736,7 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
>> * dclk_rate = N * dclk_core_rate N = (1,2,4 ),
>> * we get a little factor here
>> */
>> - dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
>> + dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
>> if (!dclk_rate) {
>> drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
>
>Ditto.
>
>Otherwise,
>
>Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Acked-by: Andy Yan<andyshrk@163.com>
>
>Thanks!
>Quentin
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next prev parent reply other threads:[~2024-11-14 0:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-25 19:55 [PATCH 0/2] drm/rockchip: vop2: two fixes from working on DSI enablement Heiko Stuebner
2024-04-25 19:55 ` [PATCH 1/2] drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification Heiko Stuebner
2024-05-03 12:13 ` Quentin Schulz
2024-11-14 0:50 ` Andy Yan [this message]
2024-11-14 9:38 ` Quentin Schulz
2024-11-14 10:16 ` Andy Yan
2024-11-13 1:16 ` Andy Yan
2024-04-25 19:55 ` [PATCH 2/2] drm/rockchip: vop2: configure layers for vp3 on rk3588 Heiko Stuebner
2024-05-03 12:57 ` Quentin Schulz
2024-05-03 13:02 ` Heiko Stübner
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