[PATCH v2 0/4] accel: rocket: Add RK3568 NPU support

[PATCH v2 0/4] accel: rocket: Add RK3568 NPU support

[MidG971]

From: Midgy BALON <midgy971@gmail.com>

This series adds Rockchip RK3568 support to the upstream Rocket accel
driver (drivers/accel/rocket/), tested on a Radxa ROCK 3B board running
Linux 6.19-rc5.

The RK3568 carries a single NVDLA-derived NPU core (0.8 TOPS), the same
IP family as the three-core RK3588 NPU already supported by the driver.
The hardware register layout (pc/cna/core regions, interrupt, IOMMU) is
identical; the differences are:

  - 32-bit DMA address limit (NPU AXI bus and IOMMU page walker are 32-bit)
  - Requires explicit PVTPLL initialisation via two TF-A SCMI calls before
    the NPU NOC bus can be de-idled
  - Requires explicit PMU writes to power on the NPU domain (because the
    RK3568 power domain RK3568_PD_NPU is always_on so the generic
    pm-domains callback is a no-op) and de-idle the NPU NOC bus

Patch 1 introduces a per-SoC rocket_soc_data abstraction (dma_bits and
optional noc_init callback) plumbed via of_device_get_match_data(), and
adds RK3568 SoC support on top of it.  The DMA mask for the parent
DRM facade device is chosen based on the narrowest core present
(32-bit if any RK3568 core is in the system).

Patch 2 documents the new rk3568-rknn-core compatible and the
rockchip,pmu phandle that RK3568 requires; the sram-supply property
becomes conditional (RK3588-only).

Patches 3-4 add the RK3568 NPU and IOMMU nodes to rk356x-base.dtsi and
enable them on the Radxa ROCK 3B.

Verified on Radxa ROCK 3B (RK3568, 8 GB RAM):
  - /dev/accel/accel0 created at boot
  - dmesg: "Rockchip NPU core 0 version: 0"
  - IOMMU domain attached per open()
  - Job submission path complete: regcmd reaches the NPU's program
    controller, PC processes all 135 regcmd entries, broadcasts to
    sub-units, and advances to BSP-equivalent completion state
    (PC_TASKST=0x11000)

Status of end-to-end inference: NOT YET WORKING.  After 12 days of
investigation comparing rocket's behaviour against the vendor BSP RKNPU
driver, the NPU's MMIO state at submission time matches BSP byte-for-byte
(CNA configs, sub-unit OP_ENABLE registers, CBUF_CON0, etc.) but no
sub-unit transitions to its EXECUTER state and the completion IRQ never
fires.  The kernel driver and DT infrastructure in this series stand on
their own — the driver loads, IOMMU domain is attached, regcmd reaches
the NPU, PC state machine matches BSP — but a mesa-side regcmd issue
(or another piece we have not yet found) blocks the final conv firing.

I am sending this series now because the kernel and DT pieces are
self-contained, verifiable, and ready for review.  A separate RFC on
mesa-dev will follow with the userspace findings.  Detailed investigation
notes are available on request; relevant highlights for the maintainer:

1. Mesa rocket userspace (src/gallium/drivers/rocket/) targets RK3588.
   For RK3568, several encoded values need adjustment.  Most notably,
   sub-unit OP_ENABLE register offset on RK3568 is 0x_00c, not 0x_008.
   Mesa emits writes at 0x1008/0x2008/0x3008/0x4008/0x5008 — BSP regcmd
   captures show no writes at these offsets across two distinct conv
   shapes (YOLOv5s 6x6/s2 and MobileNet 3x3/s2).  BSP writes OP_ENABLE
   at offset 0x_00c with multi-bit values (CMAC=0x1, ACCU=0x0, DPU=0x108,
   DPU_RDMA=0x13f), not bit-0 booleans.  This and a handful of other
   shape-independent value differences will be filed as a mesa RFC.

2. The vendor BSP RKNPU driver writes the userspace task_base_addr to
   PC_DMA_BASE_ADDR (PC offset 0x34); the rocket driver did not.  PC's
   TASK_DMA engine reads struct rknpu_task descriptors from there.  With
   task_pp_en=1 in TASK_CON and a kernel-allocated descriptor BO,
   PC's task counter state machine advances from "stuck at 0xf000" to
   the BSP completion state.  This is the most invasive piece of the
   investigation and is held back for a follow-on patch (not in this
   series); the current series gets the driver to a working /dev/accel/
   node and an attached IOMMU domain, which is the right shape for v2.

3. The NPU's master AXI port is 32-bit, but dma_alloc_coherent() through
   the dma-iommu framework silently ignores GFP_DMA32 even with a 32-bit
   dma_mask set on the device.  When BOs for the NPU are allocated kernel-
   side, __get_free_pages(GFP_DMA32 | __GFP_ZERO, order) + dma_map_single()
   is the working pattern.  Not in this series, but might be a useful
   documentation note for other 32-bit AXI accelerators using dma-iommu.

This series builds against current v6.19-rc5 with no checkpatch warnings,
the dtb builds, and dtbs_check passes.  The April v1 series included a
fifth patch ("Use of_find_matching_node() instead of for_each_of_allnodes")
which is no longer required — upstream rocket already uses
for_each_compatible_node() since v6.19-rc5.

Changes since v1 (April 2026, never sent on-list):
  - Rebased to v6.19-rc5
  - Patch 1 absorbed v1 patch 1 (obsolete) and now includes the
    rocket_soc_data abstraction needed to support both RK3568 and
    RK3588 cores in the same driver
  - Cover letter expanded with current investigation status

Assisted by Claude Sonnet/Opus 4.x throughout the investigation.  All
findings empirically verified via BSP register captures and side-by-side
rocket execution traces on the same board.

Midgy BALON (4):
  accel: rocket: Add support for Rockchip RK3568
  dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support
  arm64: dts: rockchip: rk356x: Add NPU and its IOMMU
  arm64: dts: rockchip: rk3568-rock-3b: Enable NPU

 Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml | 18 ++++++++++++++--
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi                        | 31 +++++++++++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts                      |  9 ++++++++
 drivers/accel/rocket/rocket_core.c                                   | 21 +++++++++++++++++-
 drivers/accel/rocket/rocket_core.h                                   | 18 ++++++++++++++--
 drivers/accel/rocket/rocket_device.c                                 | 23 +++++++++++++++++--
 drivers/accel/rocket/rocket_drv.c                                    | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 7 files changed, 192 insertions(+), 7 deletions(-)


Midgy BALON (4):
  accel: rocket: Add support for Rockchip RK3568
  dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support
  arm64: dts: rockchip: rk356x: Add NPU and its IOMMU
  arm64: dts: rockchip: rk3568-rock-3b: Enable NPU

 .../npu/rockchip,rk3588-rknn-core.yaml        | 18 ++++-
 .../boot/dts/rockchip/rk3568-rock-3b.dts      |  9 +++
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 ++++++++
 drivers/accel/rocket/rocket_core.c            | 18 ++++-
 drivers/accel/rocket/rocket_core.h            | 16 +++++
 drivers/accel/rocket/rocket_device.c          | 25 ++++++-
 drivers/accel/rocket/rocket_drv.c             | 71 ++++++++++++++++++-
 7 files changed, 182 insertions(+), 6 deletions(-)

-- 
2.39.5


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[PATCH v2 1/4] accel: rocket: Add support for Rockchip RK3568

[MidG971]

From: Midgy BALON <midgy971@gmail.com>

The RK3568 has a single NVDLA-derived NPU core (0.8 TOPS), the same IP
family as the three-core RK3588 NPU already supported by the Rocket
driver. To accommodate both SoCs:

  - Introduce a per-SoC rocket_soc_data structure carrying dma_bits and
an optional noc_init callback, plumbed through of_device_get_match_data().
  - rocket_device_init() now scans for both rk3568 and rk3588 RKNN cores
and picks the narrower DMA width (32-bit) when an RK3568 core is present.
  - Add rk3568_soc_data and rk3568_noc_init() handling the three RK3568-
specific initialisation steps that must run after the power domain is
on and clocks are enabled:

1. PVTPLL initialisation: The NPU uses a PVTPLL ring oscillator
   managed by TF-A via SCMI for rates above 400 MHz. A two-step
   clk_set_rate() sequence (600 MHz then 1 GHz) forces two SCMI calls
   to TF-A even if the kernel clock framework would skip an unchanged
   rate. The PVTPLL must be running before the NPU NOC bus will
   acknowledge a de-idle request.

2. Explicit NPU power-on (PWR_GATE_SFTCON): The RK3568_PD_NPU power
   domain is marked always_on in pm-domains.c, so the generic power
   domain framework power_on() callback is a no-op. The NPU hardware
   can remain power-gated at boot. Writing bit 1 = 0 to PWR_GATE_SFTCON
   (PMU offset 0xa0) explicitly powers on the NPU hardware before the
   de-idle request is issued.

3. NOC bus de-idle: Disable NPU NOC auto-idle (NOC_AUTO_CON0 bit 2),
   request de-idle (BUS_IDLE_SFTCON0 bit 2 = 0), then poll
   BUS_IDLE_ST (PMU offset 0x60) until bit 2 clears (bus active).

The RK3568 DMA address space is limited to 32 bits, as the NPU AXI bus
and IOMMU page walker cannot address memory above 4 GB.

All PMU accesses follow the RK3568 write-mask protocol: upper 16 bits are
the write-enable mask for the lower 16 bits.

Signed-off-by: Midgy BALON <midgy971@gmail.com>
---
 drivers/accel/rocket/rocket_core.c   | 18 ++++++-
 drivers/accel/rocket/rocket_core.h   | 16 +++++++
 drivers/accel/rocket/rocket_device.c | 25 ++++++++--
 drivers/accel/rocket/rocket_drv.c    | 71 +++++++++++++++++++++++++++-
 4 files changed, 125 insertions(+), 5 deletions(-)

diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c
index abe7719c1..7e2f3524a 100644
--- a/drivers/accel/rocket/rocket_core.c
+++ b/drivers/accel/rocket/rocket_core.c
@@ -21,6 +21,12 @@ int rocket_core_init(struct rocket_core *core)
 	u32 version;
 	int err = 0;
 
+	core->soc_data = of_device_get_match_data(dev);
+	if (!core->soc_data)
+		return dev_err_probe(dev, -EINVAL,
+				     "no per-SoC match data for core %d\n",
+				     core->index);
+
 	core->resets[0].id = "srst_a";
 	core->resets[1].id = "srst_h";
 	err = devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(core->resets),
@@ -52,7 +58,8 @@ int rocket_core_init(struct rocket_core *core)
 
 	dma_set_max_seg_size(dev, UINT_MAX);
 
-	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+	err = dma_set_mask_and_coherent(dev,
+					DMA_BIT_MASK(core->soc_data->dma_bits));
 	if (err)
 		return err;
 
@@ -80,6 +87,15 @@ int rocket_core_init(struct rocket_core *core)
 		return err;
 	}
 
+	if (core->soc_data->noc_init) {
+		err = core->soc_data->noc_init(core);
+		if (err) {
+			pm_runtime_put_sync(dev);
+			rocket_job_fini(core);
+			return err;
+		}
+	}
+
 	version = rocket_pc_readl(core, VERSION);
 	version += rocket_pc_readl(core, VERSION_NUM) & 0xffff;
 
diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h
index f6d738285..742e14a29 100644
--- a/drivers/accel/rocket/rocket_core.h
+++ b/drivers/accel/rocket/rocket_core.h
@@ -12,6 +12,21 @@
 
 #include "rocket_registers.h"
 
+struct rocket_core;
+
+/**
+ * struct rocket_soc_data - per-SoC configuration data
+ * @dma_bits: Physical address width reachable by the NPU's AXI bus.
+ *            RK3568: 32 (32-bit AXI), RK3588: 40.
+ * @noc_init: optional callback to de-idle the NPU NOC bus at core init.
+ *            Required on RK3568 where the NOC must be explicitly un-idled
+ *            before the NPU can be accessed.
+ */
+struct rocket_soc_data {
+	unsigned int dma_bits;
+	int (*noc_init)(struct rocket_core *core);
+};
+
 #define rocket_pc_readl(core, reg) \
 	readl((core)->pc_iomem + (REG_PC_##reg))
 #define rocket_pc_writel(core, reg, value) \
@@ -31,6 +46,7 @@ struct rocket_core {
 	struct device *dev;
 	struct rocket_device *rdev;
 	unsigned int index;
+	const struct rocket_soc_data *soc_data;
 
 	int irq;
 	void __iomem *pc_iomem;
diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
index 46e6ee1e7..0ed8251c8 100644
--- a/drivers/accel/rocket/rocket_device.c
+++ b/drivers/accel/rocket/rocket_device.c
@@ -27,6 +27,9 @@ struct rocket_device *rocket_device_init(struct platform_device *pdev,
 	ddev = &rdev->ddev;
 	dev_set_drvdata(dev, rdev);
 
+	for_each_compatible_node(core_node, NULL, "rockchip,rk3568-rknn-core")
+		if (of_device_is_available(core_node))
+			num_cores++;
 	for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core")
 		if (of_device_is_available(core_node))
 			num_cores++;
@@ -37,9 +40,25 @@ struct rocket_device *rocket_device_init(struct platform_device *pdev,
 
 	dma_set_max_seg_size(dev, UINT_MAX);
 
-	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
-	if (err)
-		return ERR_PTR(err);
+	/* Use the DMA width of the first available RKNN core.  RK3568 cores
+	 * are 32-bit; RK3588 are 40-bit.  If both are present we pick the
+	 * narrower mask.
+	 */
+	{
+		struct device_node *n;
+		unsigned int dma_bits = 40;
+
+		for_each_compatible_node(n, NULL, "rockchip,rk3568-rknn-core")
+			if (of_device_is_available(n)) {
+				dma_bits = 32;
+				of_node_put(n);
+				break;
+			}
+
+		err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_bits));
+		if (err)
+			return ERR_PTR(err);
+	}
 
 	err = devm_mutex_init(dev, &rdev->sched_lock);
 	if (err)
diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
index 5c0b63f0a..f8e153fc2 100644
--- a/drivers/accel/rocket/rocket_drv.c
+++ b/drivers/accel/rocket/rocket_drv.c
@@ -9,9 +9,11 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/iommu.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 
 #include "rocket_drv.h"
 #include "rocket_gem.h"
@@ -199,8 +201,75 @@ static void rocket_remove(struct platform_device *pdev)
 	}
 }
 
+/*
+ * RK3568 NOC de-idle: the NPU bus must be explicitly un-idled before the
+ * NPU hardware can be accessed.  The RK3568 PMU provides BUS_IDLE_SFTCON0
+ * (offset 0x50) and NOC_AUTO_CON0 (offset 0x70) for this purpose.  Refer
+ * to the RK3568 TRM section "PMU" for the write-mask protocol used by
+ * these registers (bits [31:16] are write-enable for bits [15:0]).
+ *
+ * rocket_clk_names[] in rocket_core.c defines: "aclk"[0], "hclk"[1],
+ * "npu"[2], "pclk"[3].  Index 2 is the SCMI-managed NPU clock.
+ */
+#define ROCKET_CLK_NPU_IDX	2
+
+static int rk3568_noc_init(struct rocket_core *core)
+{
+	struct regmap *pmu;
+	unsigned int val;
+	int ret;
+
+	/*
+	 * RK3568: PVTPLL (the NPU's high-speed clock, managed by TF-A via
+	 * SCMI) must be running before the NPU NOC bus will de-idle.  Force
+	 * two SCMI calls now that the NPU power domain is on and clocks are
+	 * enabled.  The intermediate 600 MHz step ensures a real SCMI call
+	 * even when the kernel clock framework would otherwise skip an
+	 * "unchanged rate" request.
+	 */
+	clk_set_rate(core->clks[ROCKET_CLK_NPU_IDX].clk, 600000000UL);
+	clk_set_rate(core->clks[ROCKET_CLK_NPU_IDX].clk, 1000000000UL);
+
+	pmu = syscon_regmap_lookup_by_phandle(core->dev->of_node, "rockchip,pmu");
+	if (IS_ERR(pmu))
+		return dev_err_probe(core->dev, PTR_ERR(pmu),
+				     "failed to get PMU regmap\n");
+
+	/* Disable NPU NOC auto-idle so the bus stays awake */
+	regmap_write(pmu, 0x70, BIT(2 + 16));
+
+	/*
+	 * Request NPU power domain power-on (PWR_GATE_SFTCON bit 1 = 0).
+	 * genpd for RK3568_PD_NPU is always_on so its power_on() is a no-op;
+	 * explicitly power on the hardware here so the bus de-idle ACK arrives.
+	 */
+	regmap_write(pmu, 0xa0, BIT(1 + 16));
+
+	/* Request NPU bus de-idle (bit 2 = 0 → active) */
+	regmap_write(pmu, 0x50, BIT(2 + 16));
+
+	/* Wait for NPU bus to become active (BUS_IDLE_ST bit 2 = 0) */
+	ret = regmap_read_poll_timeout(pmu, 0x60, val, !(val & BIT(2)), 10, 1000);
+	if (ret)
+		dev_err(core->dev,
+			"timeout waiting for NPU bus de-idle (BUS_IDLE_ST=0x%08x)\n",
+			val);
+
+	return ret;
+}
+
+static const struct rocket_soc_data rk3568_soc_data = {
+	.dma_bits = 32,
+	.noc_init = rk3568_noc_init,
+};
+
+static const struct rocket_soc_data rk3588_soc_data = {
+	.dma_bits = 40,
+};
+
 static const struct of_device_id dt_match[] = {
-	{ .compatible = "rockchip,rk3588-rknn-core" },
+	{ .compatible = "rockchip,rk3568-rknn-core", .data = &rk3568_soc_data },
+	{ .compatible = "rockchip,rk3588-rknn-core", .data = &rk3588_soc_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, dt_match);
-- 
2.39.5


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[PATCH v2 2/4] dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support

[MidG971]

From: Midgy BALON <midgy971@gmail.com>

Add rockchip,rk3568-rknn-core to the compatible enum, document the
new rockchip,pmu phandle that RK3568 needs for the NPU NOC bus de-idle
sequence, and make sram-supply only required on RK3588 (RK3568 has no
NPU SRAM rail).

The driver supports both RK3568 and RK3588 RKNN cores; the binding now
documents both. The rockchip,pmu phandle is consumed by the driver to
issue PMU register writes (BUS_IDLE_SFTCON0, NOC_AUTO_CON0,
PWR_GATE_SFTCON, BUS_IDLE_ST) on RK3568 only.

Signed-off-by: Midgy BALON <midgy971@gmail.com>
---
 .../npu/rockchip,rk3588-rknn-core.yaml         | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
index caca2a490..6582a0c5c 100644
--- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
+++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
@@ -21,6 +21,7 @@ properties:
 
   compatible:
     enum:
+      - rockchip,rk3568-rknn-core
       - rockchip,rk3588-rknn-core
 
   reg:
@@ -50,6 +51,13 @@ properties:
 
   npu-supply: true
 
+  rockchip,pmu:
+    : /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the Rockchip PMU syscon node.  Required on RK3568 to
+      perform the NPU NOC bus de-idle sequence via PMU registers before
+      the hardware can be accessed.
+
   power-domains:
     maxItems: 1
 
@@ -75,7 +83,15 @@ required:
   - resets
   - reset-names
   - npu-supply
-  - sram-supply
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: rockchip,rk3588-rknn-core
+then:
+  required:
+    - sram-supply
 
 additionalProperties: false
 
-- 
2.39.5


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[PATCH v2 3/4] arm64: dts: rockchip: rk356x: Add NPU and its IOMMU

[MidG971]

From: Midgy BALON <midgy971@gmail.com>

Add the RKNN core 0 and its IOMMU to the RK3568 SoC dtsi, mirroring
the RK3588 pattern in rk3588-base.dtsi but with rk3568-specific clocks,
resets, power domain, and a rockchip,pmu phandle required for the NPU
NOC bus de-idle sequence.

Both nodes remain disabled by default; boards enable them as needed.

Signed-off-by: Midgy BALON <midgy971@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 8893b7b6c..2c2a57ea3 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -929,6 +929,37 @@ qos_rga_wr: qos@fe158300 {
 		reg = <0x0 0xfe158300 0x0 0x20>;
 	};
 
+	rknn_core_0: npu@fde40000 {
+		compatible = "rockchip,rk3568-rknn-core";
+		reg = <0x0 0xfde40000 0x0 0x1000>,
+		      <0x0 0xfde41000 0x0 0x1000>,
+		      <0x0 0xfde43000 0x0 0x1000>;
+		reg-names = "pc", "cna", "core";
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>,
+			 <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_PRE>;
+		clock-names = "aclk", "hclk", "npu", "pclk";
+		assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+		assigned-clock-rates = <200000000>;
+		resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>;
+		reset-names = "srst_a", "srst_h";
+		power-domains = <&power RK3568_PD_NPU>;
+		rockchip,pmu = <&pmu>;
+		iommus = <&rknn_mmu_0>;
+		status = "disabled";
+	};
+
+	rknn_mmu_0: iommu@fde4b000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xfde4b000 0x0 0x40>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "aclk", "iface";
+		clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>;
+		power-domains = <&power RK3568_PD_NPU>;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	qos_npu: qos@fe180000 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe180000 0x0 0x20>;
-- 
2.39.5


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[PATCH v2 4/4] arm64: dts: rockchip: rk3568-rock-3b: Enable NPU

[MidG971]

From: Midgy BALON <midgy971@gmail.com>

Enable the RKNN core 0 and its IOMMU on the Radxa ROCK 3B by
overriding their status. The Rocket accel driver binds via the
rockchip,rk3568-rknn-core compatible.

The NPU is powered from vdd_npu (regulator already defined for OPP
table). The IOMMU node is also enabled so the rocket driver can manage
its own paging domain for user-mode submissions.

Signed-off-by: Midgy BALON <midgy971@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
index 3d0c1ccfa..d54229123 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
@@ -779,3 +779,12 @@ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
 		remote-endpoint = <&hdmi_in_vp0>;
 	};
 };
+
+&rknn_core_0 {
+	npu-supply = <&vdd_npu>;
+	status = "okay";
+};
+
+&rknn_mmu_0 {
+	status = "okay";
+};
-- 
2.39.5


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Re: [PATCH v2 0/4] accel: rocket: Add RK3568 NPU support

[Krzysztof Kozlowski]

On 29/05/2026 17:58, MidG971 wrote:
> 
> This series builds against current v6.19-rc5 with no checkpatch warnings,
> the dtb builds, and dtbs_check passes.  The April v1 series included a
> fifth patch ("Use of_find_matching_node() instead of for_each_of_allnodes")
> which is no longer required — upstream rocket already uses
> for_each_compatible_node() since v6.19-rc5.
> 
> Changes since v1 (April 2026, never sent on-list):

Then there was never a v1. v1 is the first version you send, regardless
of its status.

Best regards,
Krzysztof

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Re: [PATCH v2 2/4] dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support

[Krzysztof Kozlowski]

On 29/05/2026 17:58, MidG971 wrote:
> From: Midgy BALON <midgy971@gmail.com>
> 
> Add rockchip,rk3568-rknn-core to the compatible enum, document the
> new rockchip,pmu phandle that RK3568 needs for the NPU NOC bus de-idle
> sequence, and make sram-supply only required on RK3588 (RK3568 has no
> NPU SRAM rail).
> 
> The driver supports both RK3568 and RK3588 RKNN cores; the binding now
> documents both. The rockchip,pmu phandle is consumed by the driver to
> issue PMU register writes (BUS_IDLE_SFTCON0, NOC_AUTO_CON0,

You need to start explaining the hardware, not drivers.

> PWR_GATE_SFTCON, BUS_IDLE_ST) on RK3568 only.
> 
> Signed-off-by: Midgy BALON <midgy971@gmail.com>
> ---
>  .../npu/rockchip,rk3588-rknn-core.yaml         | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> index caca2a490..6582a0c5c 100644
> --- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> @@ -21,6 +21,7 @@ properties:
>  
>    compatible:
>      enum:
> +      - rockchip,rk3568-rknn-core
>        - rockchip,rk3588-rknn-core
>  
>    reg:
> @@ -50,6 +51,13 @@ properties:
>  
>    npu-supply: true
>  
> +  rockchip,pmu:
> +    : /schemas/types.yaml#/definitions/phandle

I don't think you tested this.

Best regards,
Krzysztof

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Re: [PATCH v2 0/4] accel: rocket: Add RK3568 NPU support

[Heiko Stuebner]

Hi,

Am Freitag, 29. Mai 2026, 17:58:20 Mitteleuropäische Sommerzeit schrieb MidG971:
> From: Midgy BALON <midgy971@gmail.com>
> 
> This series adds Rockchip RK3568 support to the upstream Rocket accel
> driver (drivers/accel/rocket/), tested on a Radxa ROCK 3B board running
> Linux 6.19-rc5.
> 
> The RK3568 carries a single NVDLA-derived NPU core (0.8 TOPS), the same
> IP family as the three-core RK3588 NPU already supported by the driver.
> The hardware register layout (pc/cna/core regions, interrupt, IOMMU) is
> identical; the differences are:
> 
>   - 32-bit DMA address limit (NPU AXI bus and IOMMU page walker are 32-bit)
>   - Requires explicit PVTPLL initialisation via two TF-A SCMI calls before
>     the NPU NOC bus can be de-idled
>   - Requires explicit PMU writes to power on the NPU domain (because the
>     RK3568 power domain RK3568_PD_NPU is always_on so the generic
>     pm-domains callback is a no-op) and de-idle the NPU NOC bus
> 
> Patch 1 introduces a per-SoC rocket_soc_data abstraction (dma_bits and
> optional noc_init callback) plumbed via of_device_get_match_data(), and
> adds RK3568 SoC support on top of it.  The DMA mask for the parent
> DRM facade device is chosen based on the narrowest core present
> (32-bit if any RK3568 core is in the system).
> 
> Patch 2 documents the new rk3568-rknn-core compatible and the
> rockchip,pmu phandle that RK3568 requires; the sram-supply property
> becomes conditional (RK3588-only).
> 
> Patches 3-4 add the RK3568 NPU and IOMMU nodes to rk356x-base.dtsi and
> enable them on the Radxa ROCK 3B.
> 
> Verified on Radxa ROCK 3B (RK3568, 8 GB RAM):
>   - /dev/accel/accel0 created at boot
>   - dmesg: "Rockchip NPU core 0 version: 0"
>   - IOMMU domain attached per open()
>   - Job submission path complete: regcmd reaches the NPU's program
>     controller, PC processes all 135 regcmd entries, broadcasts to
>     sub-units, and advances to BSP-equivalent completion state
>     (PC_TASKST=0x11000)
> 
> Status of end-to-end inference: NOT YET WORKING.  After 12 days of

what about the iommu side, aka the parts mentioned in
https://lore.kernel.org/linux-rockchip/5663593b-2c53-4632-ad2c-db9efa8e9ab2@rock-chips.com/

does that is in some way responsible for the not-yet-working state?


Also in general, we don't want to merge partially working code.
Either things work, or they don't, especially as right now you wouldn't
even know if it's your code that is wrong, or some other part that needs
changes.

Also please reduce those novel-sized (generated) texts.
For the cover-letter alone I'd need a fireplace, an armchair and a
hot cocoa to fully parse it.


Heiko

> investigation comparing rocket's behaviour against the vendor BSP RKNPU
> driver, the NPU's MMIO state at submission time matches BSP byte-for-byte
> (CNA configs, sub-unit OP_ENABLE registers, CBUF_CON0, etc.) but no
> sub-unit transitions to its EXECUTER state and the completion IRQ never
> fires.  The kernel driver and DT infrastructure in this series stand on
> their own — the driver loads, IOMMU domain is attached, regcmd reaches
> the NPU, PC state machine matches BSP — but a mesa-side regcmd issue
> (or another piece we have not yet found) blocks the final conv firing.
> 
> I am sending this series now because the kernel and DT pieces are
> self-contained, verifiable, and ready for review.  A separate RFC on
> mesa-dev will follow with the userspace findings.  Detailed investigation
> notes are available on request; relevant highlights for the maintainer:
> 
> 1. Mesa rocket userspace (src/gallium/drivers/rocket/) targets RK3588.
>    For RK3568, several encoded values need adjustment.  Most notably,
>    sub-unit OP_ENABLE register offset on RK3568 is 0x_00c, not 0x_008.
>    Mesa emits writes at 0x1008/0x2008/0x3008/0x4008/0x5008 — BSP regcmd
>    captures show no writes at these offsets across two distinct conv
>    shapes (YOLOv5s 6x6/s2 and MobileNet 3x3/s2).  BSP writes OP_ENABLE
>    at offset 0x_00c with multi-bit values (CMAC=0x1, ACCU=0x0, DPU=0x108,
>    DPU_RDMA=0x13f), not bit-0 booleans.  This and a handful of other
>    shape-independent value differences will be filed as a mesa RFC.
> 
> 2. The vendor BSP RKNPU driver writes the userspace task_base_addr to
>    PC_DMA_BASE_ADDR (PC offset 0x34); the rocket driver did not.  PC's
>    TASK_DMA engine reads struct rknpu_task descriptors from there.  With
>    task_pp_en=1 in TASK_CON and a kernel-allocated descriptor BO,
>    PC's task counter state machine advances from "stuck at 0xf000" to
>    the BSP completion state.  This is the most invasive piece of the
>    investigation and is held back for a follow-on patch (not in this
>    series); the current series gets the driver to a working /dev/accel/
>    node and an attached IOMMU domain, which is the right shape for v2.
> 
> 3. The NPU's master AXI port is 32-bit, but dma_alloc_coherent() through
>    the dma-iommu framework silently ignores GFP_DMA32 even with a 32-bit
>    dma_mask set on the device.  When BOs for the NPU are allocated kernel-
>    side, __get_free_pages(GFP_DMA32 | __GFP_ZERO, order) + dma_map_single()
>    is the working pattern.  Not in this series, but might be a useful
>    documentation note for other 32-bit AXI accelerators using dma-iommu.
>
> This series builds against current v6.19-rc5 with no checkpatch warnings,
> the dtb builds, and dtbs_check passes.  The April v1 series included a
> fifth patch ("Use of_find_matching_node() instead of for_each_of_allnodes")
> which is no longer required — upstream rocket already uses
> for_each_compatible_node() since v6.19-rc5.
> 
> Changes since v1 (April 2026, never sent on-list):
>   - Rebased to v6.19-rc5
>   - Patch 1 absorbed v1 patch 1 (obsolete) and now includes the
>     rocket_soc_data abstraction needed to support both RK3568 and
>     RK3588 cores in the same driver
>   - Cover letter expanded with current investigation status
> 
> Assisted by Claude Sonnet/Opus 4.x throughout the investigation.  All
> findings empirically verified via BSP register captures and side-by-side
> rocket execution traces on the same board.
> 
> Midgy BALON (4):
>   accel: rocket: Add support for Rockchip RK3568
>   dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support
>   arm64: dts: rockchip: rk356x: Add NPU and its IOMMU
>   arm64: dts: rockchip: rk3568-rock-3b: Enable NPU
> 
>  Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml | 18 ++++++++++++++--
>  arch/arm64/boot/dts/rockchip/rk356x-base.dtsi                        | 31 +++++++++++++++++++++++++++
>  arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts                      |  9 ++++++++
>  drivers/accel/rocket/rocket_core.c                                   | 21 +++++++++++++++++-
>  drivers/accel/rocket/rocket_core.h                                   | 18 ++++++++++++++--
>  drivers/accel/rocket/rocket_device.c                                 | 23 +++++++++++++++++--
>  drivers/accel/rocket/rocket_drv.c                                    | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
>  7 files changed, 192 insertions(+), 7 deletions(-)
> 
> 
> Midgy BALON (4):
>   accel: rocket: Add support for Rockchip RK3568
>   dt-bindings: npu: rockchip,rk3588-rknn-core: Add RK3568 support
>   arm64: dts: rockchip: rk356x: Add NPU and its IOMMU
>   arm64: dts: rockchip: rk3568-rock-3b: Enable NPU
> 
>  .../npu/rockchip,rk3588-rknn-core.yaml        | 18 ++++-
>  .../boot/dts/rockchip/rk3568-rock-3b.dts      |  9 +++
>  arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 31 ++++++++
>  drivers/accel/rocket/rocket_core.c            | 18 ++++-
>  drivers/accel/rocket/rocket_core.h            | 16 +++++
>  drivers/accel/rocket/rocket_device.c          | 25 ++++++-
>  drivers/accel/rocket/rocket_drv.c             | 71 ++++++++++++++++++-
>  7 files changed, 182 insertions(+), 6 deletions(-)
> 
> 





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Re: [PATCH v2 1/4] accel: rocket: Add support for Rockchip RK3568

[Heiko Stuebner]

Hi,

Am Freitag, 29. Mai 2026, 17:58:21 Mitteleuropäische Sommerzeit schrieb MidG971:
> From: Midgy BALON <midgy971@gmail.com>
> 
> The RK3568 has a single NVDLA-derived NPU core (0.8 TOPS), the same IP
> family as the three-core RK3588 NPU already supported by the Rocket
> driver. To accommodate both SoCs:
> 
>   - Introduce a per-SoC rocket_soc_data structure carrying dma_bits and
> an optional noc_init callback, plumbed through of_device_get_match_data().
>   - rocket_device_init() now scans for both rk3568 and rk3588 RKNN cores
> and picks the narrower DMA width (32-bit) when an RK3568 core is present.
>   - Add rk3568_soc_data and rk3568_noc_init() handling the three RK3568-
> specific initialisation steps that must run after the power domain is
> on and clocks are enabled:

if you need bullet points to describe your patch, that strongly indicates
these need to be multple patches.
I.e. the move of the relevant parts to a per-soc data is one patch
(and only having the rk3588 soc-data in that one).



> 
> 1. PVTPLL initialisation: The NPU uses a PVTPLL ring oscillator
>    managed by TF-A via SCMI for rates above 400 MHz. A two-step
>    clk_set_rate() sequence (600 MHz then 1 GHz) forces two SCMI calls
>    to TF-A even if the kernel clock framework would skip an unchanged
>    rate. The PVTPLL must be running before the NPU NOC bus will
>    acknowledge a de-idle request.
> 
> 2. Explicit NPU power-on (PWR_GATE_SFTCON): The RK3568_PD_NPU power
>    domain is marked always_on in pm-domains.c, so the generic power
>    domain framework power_on() callback is a no-op. The NPU hardware
>    can remain power-gated at boot. Writing bit 1 = 0 to PWR_GATE_SFTCON
>    (PMU offset 0xa0) explicitly powers on the NPU hardware before the
>    de-idle request is issued.
> 
> 3. NOC bus de-idle: Disable NPU NOC auto-idle (NOC_AUTO_CON0 bit 2),
>    request de-idle (BUS_IDLE_SFTCON0 bit 2 = 0), then poll
>    BUS_IDLE_ST (PMU offset 0x60) until bit 2 clears (bus active).
> 
> The RK3568 DMA address space is limited to 32 bits, as the NPU AXI bus
> and IOMMU page walker cannot address memory above 4 GB.
> 
> All PMU accesses follow the RK3568 write-mask protocol: upper 16 bits are
> the write-enable mask for the lower 16 bits.
> 
> Signed-off-by: Midgy BALON <midgy971@gmail.com>

[...]

> diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
> index 46e6ee1e7..0ed8251c8 100644
> --- a/drivers/accel/rocket/rocket_device.c
> +++ b/drivers/accel/rocket/rocket_device.c
> @@ -27,6 +27,9 @@ struct rocket_device *rocket_device_init(struct platform_device *pdev,
>  	ddev = &rdev->ddev;
>  	dev_set_drvdata(dev, rdev);
>  
> +	for_each_compatible_node(core_node, NULL, "rockchip,rk3568-rknn-core")
> +		if (of_device_is_available(core_node))
> +			num_cores++;
>  	for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core")
>  		if (of_device_is_available(core_node))
>  			num_cores++;
> @@ -37,9 +40,25 @@ struct rocket_device *rocket_device_init(struct platform_device *pdev,
>  
>  	dma_set_max_seg_size(dev, UINT_MAX);
>  
> -	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
> -	if (err)
> -		return ERR_PTR(err);

for both changes in rocket_device_init():

rocket_device_init() gets called from the main probe function, so before
calling rocket_device_init() you can already access the specific soc data
from the compatible and can derive both that for_each above, and the dma-
width, directly from that.

No need for that loop below.

> +	/* Use the DMA width of the first available RKNN core.  RK3568 cores
> +	 * are 32-bit; RK3588 are 40-bit.  If both are present we pick the
> +	 * narrower mask.
> +	 */
> +	{
> +		struct device_node *n;
> +		unsigned int dma_bits = 40;
> +
> +		for_each_compatible_node(n, NULL, "rockchip,rk3568-rknn-core")
> +			if (of_device_is_available(n)) {
> +				dma_bits = 32;
> +				of_node_put(n);
> +				break;
> +			}
> +
> +		err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_bits));
> +		if (err)
> +			return ERR_PTR(err);
> +	}


Heiko



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