[Vortex86] Preempt-rt on Vortex86DX SoC - HIGH_RESOLUTION_TIMER

[Vortex86] Preempt-rt on Vortex86DX SoC - HIGH_RESOLUTION_TIMER

[Lukasz Majewski]

Hi all,

I'd like to kindly ask for some help.
I'm using the Vortex86DX SoC (it's a x86 32 clone) on my PC104 board.

I've managed to apply and run the 2.6.33.7.2-rt30 RT linux.

It supports the full preemption (PREEMPT_RT enabled).

I've run the cyclictest and then I've realized, than the
HIGH_RESOLUTION_TIMER is not supported on this SoC (yet... I hope :-) ).

Moreove the low-res counter resolution is 1ms (as shown at
cat /proc/timer_list), which is unacceptable for the application. 

I've searched deeper in the spec and I've found, that the Vortex86DX
supports two i8254 timers. One is used for DMA, interrupt controller
and disk, but the second seems to be free :-).

root@lukma:~# cat /proc/ioports 
0000-001f : dma1
0020-0021 : pic1
0040-0043 : timer0
0050-0053 : timer1 -> for use?


On the i8254 spec it is written, that it is possible to feed the counter
with 10MHz, which would be sufficient. 

I've poked around in the 2.6.33.7.2-rt30 source code and I've found,
that mostly the COMEDI "staged driver" supports this chip. It looks
that this driver has some issues and should not be used (it looks
rather old).

I have got following questions:
1. It seems, that i8254/53 is in some kind standard timer chip (like
8237- DMA chip) and should already HAVE driver (for x86).

2. It should be possible to use it as a source for HIGH RESOLUTION
TIMER to provide 1/10 MHz = 100 ns resolution. (for me 1us is enough).
I suppose, that "only" proper callbacks should be provided for
HIGH_RESOLUTION_TIMER framework.

3. It should be a common problem for x86 arch clones to provide one or
another source for HIGH RESOLUTION TIMERS to achieve proper schedule.
How this problem is tackled on the other x86 variants? There MUST be
either Local Advanced Programmable Interrupt Controller (Local APIC) or
High Precision Event Timer. The vortex86DX SoC has 800MHz clock freq,
so 1us timer precision shall be achievable. Is there any Time Stamp
Counter (TSC)?

4. I'd be glad to have an opportunity to solve this problem (I mean to
write a driver for i8254) but I don't want to reinvent the wheel :-)

Any help/ideas/hints are very welcome. I've got some experience with
ARM/PXA cores, so x86 SoC is somewhat new for my real-time adventure.


Thanks in advance and regards,
Łukasz Majewski
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