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From: sashiko-bot@kernel.org
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: wsa+renesas@sang-engineering.com, linux-rtc@vger.kernel.org,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v6 06/17] rtc: rzn1: Disable alarm interrupt before reprogramming alarm registers
Date: Fri, 21 Aug 2026 21:26:11 +0000	[thread overview]
Message-ID: <20260821212612.10E0C1F00A3E@smtp.kernel.org> (raw)
In-Reply-To: <20260821211032.13554-7-prabhakar.mahadev-lad.rj@bp.renesas.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

Pre-existing issues:
- [High] Data race and TOCTOU in IRQ handler leading to spurious interrupts and incomplete synchronization
- [High] Hardware state lockup on timeout in rzn1_rtc_set_time()
- [High] Alarm logic erroneously uses 1-second interrupt for past alarms with the same minute
- [Medium] Race window in rzn1_rtc_read_time() fallback logic can produce inconsistent timestamps
--

--- Patch [6]: [PATCH v6 06/17] rtc: rzn1: Disable alarm interrupt before reprogramming alarm registers ---
commit 0be1a07839b0e52a936e0315319b64b90371633b
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: rtc: rzn1: Disable alarm interrupt before reprogramming alarm registers

This commit updates rzn1_rtc_set_alarm() to disable alarm interrupts before
reprogramming the alarm registers (ALM, ALH, ALW). This prevents a scenario
where an existing alarm interrupt fires while the registers contain a mixture
of old and new values.

> diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
> index f3268655fd373..42e57bf0b4aaa 100644
> --- a/drivers/rtc/rtc-rzn1.c
> +++ b/drivers/rtc/rtc-rzn1.c
> @@ -281,6 +281,11 @@ static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
>  	if (alarm > farest)
>  		return -ERANGE;
>  
> +	/* Disable alarm interrupts before reprogramming the alarm. */
> +	ret = rzn1_rtc_alarm_irq_enable(dev, 0);

[Severity: High]
This is a pre-existing issue, but does disabling the IRQ here fully prevent
the race without a call to synchronize_irq()?

If a previous alarm interrupt fires right as rzn1_rtc_set_alarm() is called,
CPU0 could enter rzn1_rtc_alarm_irq(), read tm_sec locklessly, and wait for
the spinlock.

CPU1 could then call rzn1_rtc_alarm_irq_enable(dev, 0), holding and releasing
the lock.

CPU0 could then acquire the lock and unconditionally write its locklessly
computed set_irq_bits to CTL1, re-enabling the interrupt:

drivers/rtc/rtc-rzn1.c:rzn1_rtc_alarm_irq() {
	if (rtc->tm_alarm.tm_sec == 0)
		rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF);
	else
		/* Switch to 1s interrupts */
		set_irq_bits = RZN1_RTC_CTL1_1SE;

	guard(spinlock)(&rtc->ctl1_access_lock);
	...
	ctl1 &= ~RZN1_RTC_CTL1_ALME;
	ctl1 |= set_irq_bits;
	writel(ctl1, rtc->base + RZN1_RTC_CTL1);
}

Could this allow the handler to override the synchronization intended by
this patch?

> +	if (ret)
> +		return ret;
> +
>  	writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM);

[ ... ]


[Severity: High]
This isn't a bug introduced by this patch, but does the error path in
rzn1_rtc_set_time() leave the hardware in a locked-up state?

drivers/rtc/rtc-rzn1.c:rzn1_rtc_set_time() {
	...
		ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val,
					 val & RZN1_RTC_CTL2_WST, 0, 100);
		if (ret)
			return ret;
	...
}

If the system is under heavy load causing a preemption delay longer than
the 100us timeout, the function returns -ETIMEDOUT immediately without
clearing RZN1_RTC_CTL2_WAIT.

Could this stop the RTC hardware from ticking entirely across the system?


[Severity: Medium]
This is a pre-existing issue, but does the fallback logic in
rzn1_rtc_read_time() leave a race window for preemption to corrupt the
timestamp?

drivers/rtc/rtc-rzn1.c:rzn1_rtc_read_time() {
	...
	rzn1_rtc_get_time_snapshot(rtc, tm);
	secs = readl(rtc->base + RZN1_RTC_SECC);
	if (tm->tm_sec != bcd2bin(secs))
		rzn1_rtc_get_time_snapshot(rtc, tm);

	return 0;
}

If the thread is preempted precisely between the TIMEC and CALC reads in the
second snapshot, could this return an inconsistent timestamp to userspace
since there is no loop to verify the second snapshot?


[Severity: High]
This is a pre-existing issue, but does the alarm logic erroneously fall back
to the 1-second interrupt for past alarms?

drivers/rtc/rtc-rzn1.c:rzn1_rtc_alarm_irq_enable() {
	...
			if (rtc_tm_sub(tm, &tm_now) > 59 || tm->tm_min != tm_now.tm_min)
				ctl1 |= RZN1_RTC_CTL1_ALME;
			else
				ctl1 |= RZN1_RTC_CTL1_1SE;
	...
}

If an alarm is set for a time in the past where tm_min matches but
rtc_tm_sub() is negative, does this logic incorrectly apply the 1-second
interrupt and cause late or spurious wakeups?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260821211032.13554-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=6

  reply	other threads:[~2026-08-21 21:26 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-21 21:10 [PATCH v6 00/17] Add RTC support for Renesas RZ/T2H and RZ/N2H SoCs Prabhakar
2026-08-21 21:10 ` [PATCH v6 01/17] dt-bindings: rtc: renesas,rzn1-rtc: Add RZ/T2H and RZ/N2H support Prabhakar
2026-08-21 21:19   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 02/17] rtc: rzn1: Handle EPROBE_DEFER for optional pps interrupt Prabhakar
2026-08-21 21:20   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 03/17] rtc: rzn1: Fix weekday underflow when alarm crosses month boundary Prabhakar
2026-08-21 21:26   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 04/17] rtc: rzn1: Handle unset alarm weekday in rzn1_rtc_read_alarm Prabhakar
2026-08-21 21:18   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 05/17] rtc: rzn1: Fix alarm range check truncation on 32-bit systems Prabhakar
2026-08-21 21:22   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 06/17] rtc: rzn1: Disable alarm interrupt before reprogramming alarm registers Prabhakar
2026-08-21 21:26   ` sashiko-bot [this message]
2026-08-22 19:22     ` Wolfram Sang
2026-08-21 21:10 ` [PATCH v6 07/17] rtc: rzn1: Fix malformed MODULE_AUTHOR string Prabhakar
2026-08-21 21:13   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 08/17] rtc: Kconfig: Broaden RTC_DRV_RZN1 dependency to ARCH_RENESAS Prabhakar
2026-08-21 21:15   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 09/17] rtc: rzn1: Use pm_runtime_put_sync() Prabhakar
2026-08-21 21:19   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 10/17] rtc: rzn1: Replace remove callback with devm_add_action_or_reset() Prabhakar
2026-08-21 21:17   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 11/17] rtc: rzn1: Dynamically calculate synchronization delay based on clock rate Prabhakar
2026-08-21 21:16   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 12/17] rtc: rzn1: Use temporary variable for struct device Prabhakar
2026-08-21 21:18   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 13/17] rtc: rzn1: Consistently use dev_err_probe() Prabhakar
2026-08-21 21:17   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 14/17] rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access Prabhakar
2026-08-21 21:20   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 15/17] rtc: rzn1: Add OF match data to gate SUBU " Prabhakar
2026-08-21 21:20   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 16/17] rtc: rzn1: Drop trailing comma from OF match table sentinel Prabhakar
2026-08-21 21:18   ` sashiko-bot
2026-08-21 21:10 ` [PATCH v6 17/17] rtc: rzn1: Add support for Renesas RZ/T2H and RZ/N2H SoCs Prabhakar
2026-08-21 21:25   ` sashiko-bot
2026-08-22 19:27 ` [PATCH v6 00/17] Add RTC " Wolfram Sang
2026-08-23 19:27 ` Alexandre Belloni

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