* [PATCH v4 9/9] clk: sunxi-ng: sun6i-rtc: add a733 support
From: Jerome Brunet @ 2026-07-06 9:32 UTC (permalink / raw)
To: Junhui Liu, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Michael Turquette, Stephen Boyd, Maxime Ripard
Cc: linux-rtc, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-clk, Jerome Brunet
In-Reply-To: <20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com>
Add support for the sun60i a733 CCU RTC.
Compared to the a523, this SoC has a different input oscillator divider
which auto-detects the oscillator rate and select a divider to provide
a fixed 32768Hz clock. It also provides several phy reference clocks
with dedicated clock gates.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 73 ++++++++++++++++++++++++++++++++++--
drivers/clk/sunxi-ng/ccu-sun6i-rtc.h | 2 +-
2 files changed, 71 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index 25dd87e78eb7..6b71bbd80255 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -44,9 +44,13 @@
#define DCXO_CTRL_REG 0x160
#define DCXO_CTRL_CLK16M_RC_EN BIT(0)
+#define DCXO_GATING_REG 0x16c
+
struct sun6i_rtc_match_data {
bool have_ext_osc32k : 1;
bool have_iosc_calibration : 1;
+ bool have_dcxo_status : 1;
+ bool have_phy_ref_gates : 1;
bool rtc_32k_single_parent : 1;
const struct clk_parent_data *osc32k_fanout_parents;
u8 osc32k_fanout_nparents;
@@ -213,7 +217,12 @@ static struct ccu_mux osc32k_clk = {
},
};
-/* This falls back to the global name for fwnodes without a named reference. */
+/*
+ * This falls back to the global name for fwnodes without a named reference.
+ * NOTE: osc24M name might be misleading the oscillator could also be a 26MHz
+ * or a 19.2MHz one starting with the a733. The original name is kept anyway
+ * in case anything is relying on it.
+ */
static const struct clk_parent_data osc24M[] = {
{ .fw_name = "hosc", .name = "osc24M" }
};
@@ -227,8 +236,28 @@ static struct clk_fixed_factor osc24M_32k_div_clk = {
0),
};
-static SUNXI_CCU_GATE_HW(osc24M_32k_clk, "osc24M-32k", &osc24M_32k_div_clk.hw,
- LOSC_OUT_GATING_REG, BIT(16), 0);
+static struct clk_div_table osc24M_32k_div_a733_table[] = {
+ { .val = 0, .div = 732 },
+ { .val = 1, .div = 586 },
+ { .val = 2, .div = 793 },
+ { .val = 3, .div = 732 },
+ { /* Sentinel */ },
+};
+
+static struct ccu_div osc24M_32k_div_a733_clk = {
+ .enable = BIT(1),
+ .div = _SUNXI_CCU_DIV_TABLE(14, 2, osc24M_32k_div_a733_table),
+ .common = {
+ .reg = DCXO_CTRL_REG,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k-div",
+ osc24M,
+ &ccu_rodiv_ops,
+ 0),
+ },
+};
+
+static SUNXI_CCU_GATE(osc24M_32k_clk, "osc24M-32k", "osc24M-32k-div",
+ LOSC_OUT_GATING_REG, BIT(16), 0);
static const struct clk_hw *rtc_32k_parents[] = {
&osc32k_clk.common.hw,
@@ -267,6 +296,15 @@ static struct ccu_mux osc32k_fanout_clk = {
},
};
+static SUNXI_CCU_GATE_FW(hosc_serdes1_clk, "hosc-serdes1", "hosc",
+ DCXO_GATING_REG, BIT(5), 0);
+static SUNXI_CCU_GATE_FW(hosc_serdes0_clk, "hosc-serdes0", "hosc",
+ DCXO_GATING_REG, BIT(4), 0);
+static SUNXI_CCU_GATE_FW(hosc_hdmi_clk, "hosc-hdmi", "hosc",
+ DCXO_GATING_REG, BIT(1), 0);
+static SUNXI_CCU_GATE_FW(hosc_ufs_clk, "hosc-ufs", "hosc",
+ DCXO_GATING_REG, BIT(0), 0);
+
static struct ccu_common *sun6i_rtc_ccu_clks[] = {
&iosc_clk,
&iosc_32k_clk,
@@ -275,6 +313,11 @@ static struct ccu_common *sun6i_rtc_ccu_clks[] = {
&osc24M_32k_clk.common,
&rtc_32k_clk.common,
&osc32k_fanout_clk.common,
+ &osc24M_32k_div_a733_clk.common,
+ &hosc_serdes1_clk.common,
+ &hosc_serdes0_clk.common,
+ &hosc_hdmi_clk.common,
+ &hosc_ufs_clk.common,
};
static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
@@ -288,6 +331,10 @@ static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
[CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw,
[CLK_RTC_32K] = &rtc_32k_clk.common.hw,
[CLK_OSC24M_32K_DIV] = &osc24M_32k_div_clk.hw,
+ [CLK_HOSC_UFS] = &hosc_ufs_clk.common.hw,
+ [CLK_HOSC_HDMI] = &hosc_hdmi_clk.common.hw,
+ [CLK_HOSC_SERDES0] = &hosc_serdes0_clk.common.hw,
+ [CLK_HOSC_SERDES1] = &hosc_serdes1_clk.common.hw,
},
};
@@ -330,6 +377,15 @@ static const struct sun6i_rtc_match_data sun55i_a523_rtc_ccu_data = {
.osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
};
+static const struct sun6i_rtc_match_data sun60i_a733_rtc_ccu_data = {
+ .have_ext_osc32k = true,
+ .have_iosc_calibration = true,
+ .have_dcxo_status = true,
+ .have_phy_ref_gates = true,
+ .osc32k_fanout_parents = sun50i_r329_osc32k_fanout_parents,
+ .osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
+};
+
static const struct of_device_id sun6i_rtc_ccu_match[] = {
{
.compatible = "allwinner,sun50i-h616-rtc",
@@ -343,6 +399,10 @@ static const struct of_device_id sun6i_rtc_ccu_match[] = {
.compatible = "allwinner,sun55i-a523-rtc",
.data = &sun55i_a523_rtc_ccu_data,
},
+ {
+ .compatible = "allwinner,sun60i-a733-rtc",
+ .data = &sun60i_a733_rtc_ccu_data,
+ },
{},
};
MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match);
@@ -375,6 +435,13 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
osc32k_fanout_init_data.parent_data = data->osc32k_fanout_parents;
osc32k_fanout_init_data.num_parents = data->osc32k_fanout_nparents;
+ if (data->have_dcxo_status)
+ sun6i_rtc_ccu_hw_clks.hws[CLK_OSC24M_32K_DIV] =
+ &osc24M_32k_div_a733_clk.common.hw;
+
+ if (!data->have_phy_ref_gates)
+ sun6i_rtc_ccu_hw_clks.num = CLK_OSC24M_32K_DIV + 1;
+
return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc);
}
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
index ab7b92b47f59..4f4f4cb00f1d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
@@ -11,6 +11,6 @@
#define CLK_RTC_32K 6
#define CLK_OSC24M_32K_DIV 7
-#define CLK_NUMBER (CLK_OSC24M_32K_DIV + 1)
+#define CLK_NUMBER (CLK_HOSC_SERDES1 + 1)
#endif /* _CCU_SUN6I_RTC_H */
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v4 1/9] dt-bindings: rtc: sun6i: no clock-output-names on h616/r329
From: sashiko-bot @ 2026-07-06 9:39 UTC (permalink / raw)
To: Jerome Brunet
Cc: linux-sunxi, devicetree, Alexandre Belloni, linux-rtc, robh,
conor+dt
In-Reply-To: <20260706-a733-rtc-v4-1-f330728db3d3@baylibre.com>
> On h616 and r329 chips, clock output names are never defined through DT and
> are not meant to be. Just disallow the property for those chips.
>
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Closes: http://lore.kernel.org/r/20260629125305.0DF981F000E9@smtp.kernel.org
> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=1
^ permalink raw reply
* Re: [PATCH v4 2/9] dt-bindings: rtc: sun6i: add sun60i-a733 support
From: sashiko-bot @ 2026-07-06 9:41 UTC (permalink / raw)
To: Jerome Brunet
Cc: conor+dt, Alexandre Belloni, robh, linux-sunxi, devicetree,
linux-rtc
In-Reply-To: <20260706-a733-rtc-v4-2-f330728db3d3@baylibre.com>
> Add a new rtc compatible for the sun60i-a733 SoC and new IDs for the
> peripheral oscillator clock gates of this SoC.
>
> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=2
^ permalink raw reply
* Re: [PATCH] rtc: s32g: add missing MODULE_DEVICE_TABLE()
From: Matthias Brugger @ 2026-07-06 9:43 UTC (permalink / raw)
To: Pengpeng Hou, Chester Lin, Ghennadi Procopciuc,
NXP S32 Linux Team, Alexandre Belloni
Cc: linux-arm-kernel, linux-rtc, linux-kernel
In-Reply-To: <20260704122003.70108-1-pengpeng@iscas.ac.cn>
On 04/07/2026 14:20, Pengpeng Hou wrote:
> The driver has an OF match table wired to .of_match_table, but does
> not export the table with MODULE_DEVICE_TABLE().
>
> Add the missing MODULE_DEVICE_TABLE(of, ...) entry so module alias
> information is generated for OF based module autoloading.
>
> This is a source-level fix. It does not claim dynamic hardware
> reproduction; the evidence is the driver-owned match table, its use by
> the platform driver, and the missing module alias publication.
>
> Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> drivers/rtc/rtc-s32g.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/rtc/rtc-s32g.c b/drivers/rtc/rtc-s32g.c
> index 3a0818e972eb..86716192d10f 100644
> --- a/drivers/rtc/rtc-s32g.c
> +++ b/drivers/rtc/rtc-s32g.c
> @@ -366,6 +366,7 @@ static const struct of_device_id rtc_dt_ids[] = {
> { .compatible = "nxp,s32g2-rtc", .data = &rtc_s32g2_data },
> { /* sentinel */ },
> };
> +MODULE_DEVICE_TABLE(of, rtc_dt_ids);
>
> static DEFINE_SIMPLE_DEV_PM_OPS(s32g_rtc_pm_ops,
> s32g_rtc_suspend, s32g_rtc_resume);
>
^ permalink raw reply
* Re: [PATCH v4 3/9] clk: sunxi-ng: fix ccu probe clock unregister on error
From: sashiko-bot @ 2026-07-06 9:43 UTC (permalink / raw)
To: Jerome Brunet
Cc: conor+dt, robh, devicetree, Alexandre Belloni, linux-sunxi,
linux-rtc
In-Reply-To: <20260706-a733-rtc-v4-3-f330728db3d3@baylibre.com>
> When registering clocks with sunxi_ccu_probe(), the number of ccu_clocks
> and the number of hw clocks might be different, eventhough they usually are
> the same.
>
> If they are different, it could lead to out-of-bound access or registered
> clock left behind on error.
>
> Use a different variable when iterating on hw clocks so every registered
> clock, and only those, gets unregistered on error.
>
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Closes: https://lore.kernel.org/r/20260629131254.7E34C1F00A3A@smtp.kernel.org
> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=3
^ permalink raw reply
* Re: [PATCH v4 4/9] clk: sunxi-ng: sun6i-rtc: clean up DT usage
From: sashiko-bot @ 2026-07-06 9:49 UTC (permalink / raw)
To: Jerome Brunet
Cc: conor+dt, Alexandre Belloni, linux-rtc, robh, linux-sunxi,
devicetree
In-Reply-To: <20260706-a733-rtc-v4-4-f330728db3d3@baylibre.com>
> With sun6i-rtc compatible devices, the "ext-osc32k" clock input
> is optional for the devices that support this input (r329 and onward).
>
> Probably preparing for older SoC support, the driver does something funny
> when parsing DT. It check if "ext-osc32k" is present in the clock-names and
> if it is not, it uses the first clock as "ext-osc32k". This clock will
> actually be the rtc bus clock so what the driver does is wrong.
>
> At the moment, the driver does not support the older SoCs that would have
> an external 32k clock provided on index #0 so just remove this quirk.
>
> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=4
^ permalink raw reply
* Re: [PATCH v4 5/9] clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration
From: sashiko-bot @ 2026-07-06 9:56 UTC (permalink / raw)
To: Jerome Brunet
Cc: robh, linux-sunxi, linux-rtc, conor+dt, devicetree,
Alexandre Belloni
In-Reply-To: <20260706-a733-rtc-v4-5-f330728db3d3@baylibre.com>
> From: Junhui Liu <junhui.liu@pigmoral.tech>
>
> The sun6i-rtc CCU driver currently uses a global static variable to
> denote whether calibration is supported, which makes IOSC operations
> tightly coupled to this file.
>
> Convert this into a feature bit to decouple the logic. This allows the
> IOSC clock code to be moved into a shared module for reuse by other SoCs.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=5
^ permalink raw reply
* Re: [PATCH v4 6/9] clk: sunxi-ng: div: add read-only operation support
From: sashiko-bot @ 2026-07-06 10:06 UTC (permalink / raw)
To: Jerome Brunet
Cc: conor+dt, robh, linux-rtc, Alexandre Belloni, devicetree,
linux-sunxi
In-Reply-To: <20260706-a733-rtc-v4-6-f330728db3d3@baylibre.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Inconsistent rate calculation between `determine_rate` and `recalc_rate` due to division order.
--
commit 39f872462c04ad724c3624b152234160de56a47e
Author: Jerome Brunet <jbrunet@baylibre.com>
clk: sunxi-ng: div: add read-only operation support
Add support for sunxi-ng read-only dividers. This will be
useful to the a733 oscillator detection logic.
> diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
> index 62d680ccb524b..d1c8c7baa12dc 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.c
> +++ b/drivers/clk/sunxi-ng/ccu_div.c
[ ... ]
> @@ -84,6 +84,36 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
> req, ccu_div_determine_rate_helper, cd);
> }
>
> +static int ccu_rodiv_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct ccu_div *cd = hw_to_ccu_div(hw);
> + unsigned long val;
> + u32 reg;
> + int ret;
> +
> + reg = readl(cd->common.base + cd->common.reg);
> + val = reg >> cd->div.shift;
> + val &= (1 << cd->div.width) - 1;
> +
> + req->rate = ccu_mux_helper_unapply_prediv(&cd->common, &cd->mux, -1,
> + req->rate);
> +
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + req->rate *= cd->fixed_post_div;
> +
> + ret = divider_ro_determine_rate(hw, req, cd->div.table,
> + cd->div.width, cd->div.flags, val);
> +
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + req->rate /= cd->fixed_post_div;
> +
> + req->rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
> + req->rate);
[Severity: Medium]
Will this division order cause inconsistent rate calculations compared to
ccu_div_recalc_rate()?
The divider_ro_determine_rate() helper applies DIV_ROUND_UP() to the unadjusted
parent rate, and then this function divides that result by fixed_post_div and
prediv.
However, ccu_div_recalc_rate() applies prediv to the parent rate first, then
calculates the divider rate, and finally divides by fixed_post_div.
Since the Common Clock Framework requires determine_rate and recalc_rate to be
mathematically consistent, could this discrepancy cause rate mismatches or
warnings for clocks using a pre-divider or fixed post-divider?
> +
> + return ret;
> +}
> +
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=6
^ permalink raw reply
* Re: [PATCH v4 7/9] clk: sunxi-ng: mux: remove unneeded export
From: sashiko-bot @ 2026-07-06 10:10 UTC (permalink / raw)
To: Jerome Brunet
Cc: conor+dt, linux-rtc, linux-sunxi, Alexandre Belloni, robh,
devicetree
In-Reply-To: <20260706-a733-rtc-v4-7-f330728db3d3@baylibre.com>
> The export ccu_mux_helper_apply_prediv() symbol is actually not
> necessary. No module other than sunxi-ccu would use it at the moment
> so just remove the export.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=7
^ permalink raw reply
* Re: [PATCH v4 8/9] clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate.
From: sashiko-bot @ 2026-07-06 10:18 UTC (permalink / raw)
To: Jerome Brunet
Cc: conor+dt, robh, Alexandre Belloni, devicetree, linux-sunxi,
linux-rtc
In-Reply-To: <20260706-a733-rtc-v4-8-f330728db3d3@baylibre.com>
> On the a733 the "osc24M-32k" clock has the same gate bits as the previously
> supported SoC but a different divider implementation.
>
> Instead of a fixed 750 divider, the divider is selected based on the
> rate of the oscillator. It can be seen as a simple read-only divider.
>
> To easily replace the divider part depending the SoC, split the divider
> and gate into two separate clock entities.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=8
^ permalink raw reply
* Re: [PATCH v4 9/9] clk: sunxi-ng: sun6i-rtc: add a733 support
From: sashiko-bot @ 2026-07-06 10:26 UTC (permalink / raw)
To: Jerome Brunet
Cc: robh, conor+dt, devicetree, linux-rtc, Alexandre Belloni,
linux-sunxi
In-Reply-To: <20260706-a733-rtc-v4-9-f330728db3d3@baylibre.com>
> Add support for the sun60i a733 CCU RTC.
>
> Compared to the a523, this SoC has a different input oscillator divider
> which auto-detects the oscillator rate and select a divider to provide
> a fixed 32768Hz clock. It also provides several phy reference clocks
> with dedicated clock gates.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-a733-rtc-v4-0-f330728db3d3@baylibre.com?part=9
^ permalink raw reply
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