* [PATCH] rtc: ac100: Program clock divider encodings without subtracting one
@ 2026-11-12 7:16 Zhu Jun
2026-11-12 7:20 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Zhu Jun @ 2026-11-12 7:16 UTC (permalink / raw)
To: alexandre.belloni; +Cc: linux-rtc, linux-kernel, Zhu Jun
divider_get_val() already returns the hardware encoding for the
power-of-two divider, and ac100_clkout_prediv[].val is also a register
encoding. Subtracting one from either value programs the previous
divider setting and turns encoding zero into all ones.
For example, selecting a 32768 Hz output from the 32768 Hz parent
programs divider seven and produces 256 Hz. Write both encodings
directly so the programmed rate agrees with the requested rate.
Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
Signed-off-by: Zhu Jun <zhujun2@cmss.chinamobile.com>
---
drivers/rtc/rtc-ac100.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index be57a33ecf53..a94248346bf3 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -243,8 +243,8 @@ static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
regmap_update_bits(clk->regmap, clk->offset,
((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |
((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,
- (div - 1) << AC100_CLKOUT_DIV_SHIFT |
- (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);
+ div << AC100_CLKOUT_DIV_SHIFT |
+ pre_div << AC100_CLKOUT_PRE_DIV_SHIFT);
return 0;
}
--
2.51.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] rtc: ac100: Program clock divider encodings without subtracting one
2026-11-12 7:16 [PATCH] rtc: ac100: Program clock divider encodings without subtracting one Zhu Jun
@ 2026-11-12 7:20 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-11-12 7:20 UTC (permalink / raw)
To: Zhu Jun; +Cc: linux-rtc, Alexandre Belloni
> divider_get_val() already returns the hardware encoding for the
> power-of-two divider, and ac100_clkout_prediv[].val is also a register
> encoding. Subtracting one from either value programs the previous
> divider setting and turns encoding zero into all ones.
>
> For example, selecting a 32768 Hz output from the 32768 Hz parent
> programs divider seven and produces 256 Hz. Write both encodings
> directly so the programmed rate agrees with the requested rate.
>
> Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
> Signed-off-by: Zhu Jun <zhujun2@cmss.chinamobile.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112071620.154398-1-zhujun2@cmss.chinamobile.com?part=1
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