Re: [PATCH v2 4/4] s390: Add support for DCACHE_WORD_ACCESS (again)

[Heiko Carstens <hca@linux.ibm.com>]

On Fri, Jul 17, 2026 at 09:36:32AM +0000, sashiko-bot@kernel.org wrote:
> > +static inline unsigned long load_unaligned_zeropad(const void *addr)
> > +{
> > +	unsigned long data;
> > +
> > +	asm_inline volatile(
> > +		"0:	lg	%[data],0(%[addr])\n"
> > +		"1:	nopr	%%r7\n"
> > +		EX_TABLE_ZEROPAD(0b, 1b, %[data], %[addr])
> > +		EX_TABLE_ZEROPAD(1b, 1b, %[data], %[addr])
> > +		: [data] "=d" (data)
> 
> [Severity: High]
> Could GCC allocate the same register for both the [addr] input and the
> [data] output since there is no earlyclobber modifier here?
> 
> If a page-crosser triggers a terminating secure storage access exception,
> the hardware leaves the result register in an unpredictable state.
> 
> The exception handler ex_handler_zeropad() relies on reading the original
> address from the register specified by [addr] to compute the valid bytes.
> If GCC uses the exact same register for both input and output, the handler
> will read a corrupted address from the clobbered register, dereference it,
> and cause a kernel panic.
> 
> Should this use the earlyclobber constraint "=&d" for the data output to
> ensure the address register is preserved during a terminating exception?

This doesn't make sense to me. Secure storage access exceptions are
nullifying per architecture, not terminating.