[PATCH v2 0/2] i2c: exynos5: add support for ExynosAutov9 SoC

[PATCH v2 0/2] i2c: exynos5: add support for ExynosAutov9 SoC

[Jaewon Kim]

Serial IPs(UART, I2C, SPI) are integrated into New IP-Core
called USI(Universal Serial Interface).

As it is integrated into USI, there are additinal HW changes.
Registers to control USI and sysreg to set serial IPs have been added.
Also, some timing registres have been changed.

Changes in v2:
 - Changes compatible name to "samsung,exynosautov9-hsi2c"
 - Changes I2C type name to "I2C_TYPE_EXYNOSAUTOV9" from "I2C_TYPE_USI"
 - Changes to clear after reset instread of clearing reset
 - Add description about system register for USI

Jaewon Kim (2):
  dt-bindings: i2c: exynos5: add exynosautov9-hsi2c compatible
  i2c: exynos5: add support for ExynosAutov9 SoC

 .../devicetree/bindings/i2c/i2c-exynos5.txt   |   7 +
 drivers/i2c/busses/i2c-exynos5.c              | 133 ++++++++++++++++--
 2 files changed, 130 insertions(+), 10 deletions(-)

-- 
2.33.1

[PATCH 1/2] dt-bindings: i2c: exynos5: add exynosautov9-hsi2c compatible

[Jaewon Kim]

This patch adds new "samsung,exynosautov9-hsi2c" compatible.
It is for i2c compatible with HSI2C available on Exynos SoC with USI.

Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
---
 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index 2dbc0b62daa6..39f4067d9d1f 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -14,6 +14,8 @@ Required properties:
 				on Exynos5260 SoCs.
 	-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
 				on Exynos7 SoCs.
+	-> "samsung,exynosautov9-hsi2c", for i2c compatible with HSI2C available
+				on ExynosAutov9 SoCs.
 
   - reg: physical base address of the controller and length of memory mapped
     region.
@@ -31,6 +33,11 @@ Optional properties:
        at 100khz.
     -> If specified, the bus operates in high-speed mode only if the
        clock-frequency is >= 1Mhz.
+  - samsung,sysreg : system registers controller phandle to control USI.
+    -> If I2C integrated to USI(Universal Serial Interface), this property
+       is required. When using Exynos USI block, it needs to select which type
+       of Serial IPs(UART, SPI, I2C) to use with system register. So, it
+       requires samsung,sysreg phandle and offset value of system register.
 
 Example:
 
-- 
2.33.1

Re: [PATCH 1/2] dt-bindings: i2c: exynos5: add exynosautov9-hsi2c compatible

[Krzysztof Kozlowski]

On 11/11/2021 09:43, Jaewon Kim wrote:
> This patch adds new "samsung,exynosautov9-hsi2c" compatible.
> It is for i2c compatible with HSI2C available on Exynos SoC with USI.
> 
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> ---
>  Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

You did not Cc the necessary lists (devicetree). Please use
scripts/get_maintainers.pl to get list of addresses to CC.

Patch itself looks good, so you can resend with:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>


Best regards,
Krzysztof

RE: [PATCH 1/2] dt-bindings: i2c: exynos5: add exynosautov9-hsi2c compatible

[Jaewon Kim]

Hello Krzysztof

> On 11/11/2021 09:43, Jaewon Kim wrote:
> > This patch adds new "samsung,exynosautov9-hsi2c" compatible.
> > It is for i2c compatible with HSI2C available on Exynos SoC with USI.
> >
> > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> > ---
> >  Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> 
> You did not Cc the necessary lists (devicetree). Please use scripts/get_maintainers.pl to get list of
> addresses to CC.
> 
> Patch itself looks good, so you can resend with:
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> 
> 
> Best regards,
> Krzysztof

Thanks.
I will add more CC lists in next.

[PATCH 2/2] i2c: exynos5: add support for ExynosAutov9 SoC

[Jaewon Kim]

Serial IPs(UART, I2C, SPI) are integrated into New IP-Core
called USI(Universal Serial Interface).

As it is integrated into USI, there are additinal HW changes.
Registers to control USI and sysreg to set serial IPs have been added.
Also, some timing registres have been changed.

Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
---
 drivers/i2c/busses/i2c-exynos5.c | 133 ++++++++++++++++++++++++++++---
 1 file changed, 123 insertions(+), 10 deletions(-)

diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 97d4f3ac0abd..6a05af550aa5 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -22,6 +22,8 @@
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
 #include <linux/spinlock.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 /*
  * HSI2C controller from Samsung supports 2 modes of operation
@@ -166,9 +168,21 @@
 
 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
 
+/* USI(Universal Serial Interface) Register map */
+#define USI_CON					0xc4
+#define USI_OPTION				0xc8
+
+/* USI(Universal Serial Interface) Register bits */
+#define USI_CON_RESET				BIT(0)
+
+/* SYSREG Register bit */
+#define SYSREG_USI_SW_CONF_MASK			(0x7 << 0)
+#define SYSREG_I2C_SW_CONF			BIT(2)
+
 enum i2c_type_exynos {
 	I2C_TYPE_EXYNOS5,
 	I2C_TYPE_EXYNOS7,
+	I2C_TYPE_EXYNOSAUTOV9,
 };
 
 struct exynos5_i2c {
@@ -199,6 +213,10 @@ struct exynos5_i2c {
 
 	/* Version of HS-I2C Hardware */
 	const struct exynos_hsi2c_variant *variant;
+
+	/* USI sysreg info */
+	struct regmap		*usi_sysreg;
+	unsigned int		usi_offset;
 };
 
 /**
@@ -212,24 +230,34 @@ struct exynos5_i2c {
  */
 struct exynos_hsi2c_variant {
 	unsigned int		fifo_depth;
+	unsigned int		has_usi;
 	enum i2c_type_exynos	hw;
 };
 
 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
 	.fifo_depth	= 64,
+	.has_usi	= 0,
 	.hw		= I2C_TYPE_EXYNOS5,
 };
 
 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
 	.fifo_depth	= 16,
+	.has_usi	= 0,
 	.hw		= I2C_TYPE_EXYNOS5,
 };
 
 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
 	.fifo_depth	= 16,
+	.has_usi	= 0,
 	.hw		= I2C_TYPE_EXYNOS7,
 };
 
+static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {
+	.fifo_depth	= 64,
+	.has_usi	= 1,
+	.hw		= I2C_TYPE_EXYNOSAUTOV9,
+};
+
 static const struct of_device_id exynos5_i2c_match[] = {
 	{
 		.compatible = "samsung,exynos5-hsi2c",
@@ -243,6 +271,9 @@ static const struct of_device_id exynos5_i2c_match[] = {
 	}, {
 		.compatible = "samsung,exynos7-hsi2c",
 		.data = &exynos7_hsi2c_data
+	}, {
+		.compatible = "samsung,exynosautov9-hsi2c",
+		.data = &exynosautov9_hsi2c_data
 	}, {},
 };
 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
@@ -281,6 +312,31 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
 		i2c->op_clock;
 	int div, clk_cycle, temp;
 
+	/* In case of HSI2C controllers in EXYNOSAUTOV9
+	 * timing control formula changed.
+	 *
+	 * FSCL = IPCLK / ((CLK_DIV + 1) * 16)
+	 * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M)
+	 *  [N : number of 0's in the TSCL_H_HS]
+	 *  [M : number of 0's in the TSCL_L_HS]
+	 * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M)
+	 *  [N : number of 1's in the TSCL_H_HS]
+	 *  [M : number of 1's in the TSCL_L_HS]
+	 *
+	 *  result of (N + M) is always 8.
+	 *  In general use case, we don't need to control timing_s1, timing_s2.
+	 */
+	if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
+		div = ((clkin / (16 * i2c->op_clock)) - 1);
+		i2c_timing_s3 = div << 16;
+		if (hs_timings)
+			writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
+		else
+			writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
+
+		return 0;
+	}
+
 	/*
 	 * In case of HSI2C controller in Exynos5 series
 	 * FPCLK / FI2C =
@@ -355,6 +411,20 @@ static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
 	return exynos5_i2c_set_timing(i2c, true);
 }
 
+static void exynos_usi_reset(struct exynos5_i2c *i2c)
+{
+	u32 val;
+
+	val = readl(i2c->regs + USI_CON);
+	val |= USI_CON_RESET;
+	writel(val, i2c->regs + USI_CON);
+	udelay(1);
+
+	val = readl(i2c->regs + USI_CON);
+	val &= ~USI_CON_RESET;
+	writel(val, i2c->regs + USI_CON);
+}
+
 /*
  * exynos5_i2c_init: configures the controller for I2C functionality
  * Programs I2C controller for Master mode operation
@@ -385,6 +455,9 @@ static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
 {
 	u32 i2c_ctl;
 
+	if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9)
+		exynos_usi_reset(i2c);
+
 	/* Set and clear the bit for reset */
 	i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 	i2c_ctl |= HSI2C_SW_RST;
@@ -422,7 +495,8 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
 	writel(int_status, i2c->regs + HSI2C_INT_STATUS);
 
 	/* handle interrupt related to the transfer status */
-	if (i2c->variant->hw == I2C_TYPE_EXYNOS7) {
+	if (i2c->variant->hw == I2C_TYPE_EXYNOS7 ||
+			i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
 		if (int_status & HSI2C_INT_TRANS_DONE) {
 			i2c->trans_done = 1;
 			i2c->state = 0;
@@ -569,13 +643,13 @@ static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
 {
 	unsigned long timeout;
 
-	if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
+	if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
 		return;
 
 	/*
-	 * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction
-	 * indicates that bus is stuck (SDA is low). In such case bus recovery
-	 * can be performed.
+	 * HSI2C_MASTER_ST_LOSE state in EXYNOS7 or EXYNOSAUTOV9 variant before
+	 * transaction indicates that bus is stuck (SDA is low).
+	 * In such case bus recovery can be performed.
 	 */
 	timeout = jiffies + msecs_to_jiffies(100);
 	for (;;) {
@@ -611,10 +685,10 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
 	unsigned long flags;
 	unsigned short trig_lvl;
 
-	if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
-		int_en |= HSI2C_INT_I2C_TRANS;
-	else
+	if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
 		int_en |= HSI2C_INT_I2C;
+	else
+		int_en |= HSI2C_INT_I2C_TRANS;
 
 	i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 	i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
@@ -738,6 +812,41 @@ static const struct i2c_algorithm exynos5_i2c_algorithm = {
 	.functionality		= exynos5_i2c_func,
 };
 
+static int exynos_usi_init(struct exynos5_i2c *i2c)
+{
+	struct device *dev = i2c->dev;
+	int ret;
+
+	if (!i2c->variant->has_usi)
+		return 0;
+
+	/* System Register has a field that can select the serial IP
+	 * provided by USI. We need to set it to I2C to use I2C.
+	 */
+	i2c->usi_sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
+							  "samsung,sysreg");
+	if (IS_ERR(i2c->usi_sysreg)) {
+		dev_err(dev, "Cannot find sysreg\n");
+		return PTR_ERR(i2c->usi_sysreg);
+	}
+
+	ret = of_property_read_u32_index(dev->of_node, "samsung,sysreg",
+					 1, &i2c->usi_offset);
+	if (ret) {
+		dev_err(dev, "sysreg offset is not specified\n");
+		return ret;
+	}
+
+	ret = regmap_update_bits(i2c->usi_sysreg, i2c->usi_offset,
+			SYSREG_USI_SW_CONF_MASK, SYSREG_I2C_SW_CONF);
+	if (ret < 0)
+		return ret;
+
+	exynos_usi_reset(i2c);
+
+	return 0;
+}
+
 static int exynos5_i2c_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -777,6 +886,12 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
 	i2c->adap.algo_data = i2c;
 	i2c->adap.dev.parent = &pdev->dev;
 
+	i2c->variant = of_device_get_match_data(&pdev->dev);
+
+	ret = exynos_usi_init(i2c);
+	if (ret)
+		return ret;
+
 	/* Clear pending interrupts from u-boot or misc causes */
 	exynos5_i2c_clr_pend_irq(i2c);
 
@@ -794,8 +909,6 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
 		goto err_clk;
 	}
 
-	i2c->variant = of_device_get_match_data(&pdev->dev);
-
 	ret = exynos5_hsi2c_clock_setup(i2c);
 	if (ret)
 		goto err_clk;
-- 
2.33.1

Re: [PATCH 2/2] i2c: exynos5: add support for ExynosAutov9 SoC

[Krzysztof Kozlowski]

On 11/11/2021 09:43, Jaewon Kim wrote:
> Serial IPs(UART, I2C, SPI) are integrated into New IP-Core
> called USI(Universal Serial Interface).
> 
> As it is integrated into USI, there are additinal HW changes.
> Registers to control USI and sysreg to set serial IPs have been added.
> Also, some timing registres have been changed.
> 
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> ---
>  drivers/i2c/busses/i2c-exynos5.c | 133 ++++++++++++++++++++++++++++---
>  1 file changed, 123 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
> index 97d4f3ac0abd..6a05af550aa5 100644
> --- a/drivers/i2c/busses/i2c-exynos5.c
> +++ b/drivers/i2c/busses/i2c-exynos5.c
> @@ -22,6 +22,8 @@
>  #include <linux/of_device.h>
>  #include <linux/of_irq.h>
>  #include <linux/spinlock.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
>  
>  /*
>   * HSI2C controller from Samsung supports 2 modes of operation
> @@ -166,9 +168,21 @@
>  
>  #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
>  
> +/* USI(Universal Serial Interface) Register map */
> +#define USI_CON					0xc4
> +#define USI_OPTION				0xc8
> +
> +/* USI(Universal Serial Interface) Register bits */
> +#define USI_CON_RESET				BIT(0)
> +
> +/* SYSREG Register bit */
> +#define SYSREG_USI_SW_CONF_MASK			(0x7 << 0)
> +#define SYSREG_I2C_SW_CONF			BIT(2)
> +
>  enum i2c_type_exynos {
>  	I2C_TYPE_EXYNOS5,
>  	I2C_TYPE_EXYNOS7,
> +	I2C_TYPE_EXYNOSAUTOV9,

The type in driver could stay USI, I only wanted the compatible to be
using SoC product ID/number. But current AUTOV9 is fine as well.

>  };
>  
>  struct exynos5_i2c {
> @@ -199,6 +213,10 @@ struct exynos5_i2c {
>  
>  	/* Version of HS-I2C Hardware */
>  	const struct exynos_hsi2c_variant *variant;
> +
> +	/* USI sysreg info */
> +	struct regmap		*usi_sysreg;
> +	unsigned int		usi_offset;
>  };
>  
>  /**
> @@ -212,24 +230,34 @@ struct exynos5_i2c {
>   */
>  struct exynos_hsi2c_variant {
>  	unsigned int		fifo_depth;
> +	unsigned int		has_usi;

Sorry for not noticing it earlier, but this should be bool.

>  	enum i2c_type_exynos	hw;
>  };
>  
>  static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
>  	.fifo_depth	= 64,
> +	.has_usi	= 0,

And this should be "false".

>  	.hw		= I2C_TYPE_EXYNOS5,
>  };
>  
>  static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
>  	.fifo_depth	= 16,
> +	.has_usi	= 0,
>  	.hw		= I2C_TYPE_EXYNOS5,
>  };
>  
>  static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
>  	.fifo_depth	= 16,
> +	.has_usi	= 0,
>  	.hw		= I2C_TYPE_EXYNOS7,
>  };
>  
> +static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {
> +	.fifo_depth	= 64,
> +	.has_usi	= 1,
> +	.hw		= I2C_TYPE_EXYNOSAUTOV9,
> +};
> +
>  static const struct of_device_id exynos5_i2c_match[] = {
>  	{
>  		.compatible = "samsung,exynos5-hsi2c",
> @@ -243,6 +271,9 @@ static const struct of_device_id exynos5_i2c_match[] = {
>  	}, {
>  		.compatible = "samsung,exynos7-hsi2c",
>  		.data = &exynos7_hsi2c_data
> +	}, {
> +		.compatible = "samsung,exynosautov9-hsi2c",
> +		.data = &exynosautov9_hsi2c_data
>  	}, {},
>  };
>  MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
> @@ -281,6 +312,31 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
>  		i2c->op_clock;
>  	int div, clk_cycle, temp;
>  
> +	/* In case of HSI2C controllers in EXYNOSAUTOV9

Linux coding comment please, so with a separate /* :

/*
 * In case of....

Rest looks good, thanks for the changes!

Best regards,
Krzysztof

RE: [PATCH 2/2] i2c: exynos5: add support for ExynosAutov9 SoC

[Jaewon Kim]

Hello Krzysztof


> On 11/11/2021 09:43, Jaewon Kim wrote:
> > Serial IPs(UART, I2C, SPI) are integrated into New IP-Core called
> > USI(Universal Serial Interface).
> >
> > As it is integrated into USI, there are additinal HW changes.
> > Registers to control USI and sysreg to set serial IPs have been added.
> > Also, some timing registres have been changed.
> >
> > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> > ---
> >  drivers/i2c/busses/i2c-exynos5.c | 133
> > ++++++++++++++++++++++++++++---
> >  1 file changed, 123 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-exynos5.c
> > b/drivers/i2c/busses/i2c-exynos5.c
> > index 97d4f3ac0abd..6a05af550aa5 100644
> > --- a/drivers/i2c/busses/i2c-exynos5.c
> > +++ b/drivers/i2c/busses/i2c-exynos5.c
> > @@ -22,6 +22,8 @@
> >  #include <linux/of_device.h>
> >  #include <linux/of_irq.h>
> >  #include <linux/spinlock.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/regmap.h>
> >
> >  /*
> >   * HSI2C controller from Samsung supports 2 modes of operation @@
> > -166,9 +168,21 @@
> >
> >  #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
> >
> > +/* USI(Universal Serial Interface) Register map */
> > +#define USI_CON					0xc4
> > +#define USI_OPTION				0xc8
> > +
> > +/* USI(Universal Serial Interface) Register bits */
> > +#define USI_CON_RESET				BIT(0)
> > +
> > +/* SYSREG Register bit */
> > +#define SYSREG_USI_SW_CONF_MASK			(0x7 << 0)
> > +#define SYSREG_I2C_SW_CONF			BIT(2)
> > +
> >  enum i2c_type_exynos {
> >  	I2C_TYPE_EXYNOS5,
> >  	I2C_TYPE_EXYNOS7,
> > +	I2C_TYPE_EXYNOSAUTOV9,
> 
> The type in driver could stay USI, I only wanted the compatible to be using SoC product ID/number. But
> current AUTOV9 is fine as well.
> 
> >  };
> >
> >  struct exynos5_i2c {
> > @@ -199,6 +213,10 @@ struct exynos5_i2c {
> >
> >  	/* Version of HS-I2C Hardware */
> >  	const struct exynos_hsi2c_variant *variant;
> > +
> > +	/* USI sysreg info */
> > +	struct regmap		*usi_sysreg;
> > +	unsigned int		usi_offset;
> >  };
> >
> >  /**
> > @@ -212,24 +230,34 @@ struct exynos5_i2c {
> >   */
> >  struct exynos_hsi2c_variant {
> >  	unsigned int		fifo_depth;
> > +	unsigned int		has_usi;
> 
> Sorry for not noticing it earlier, but this should be bool.


Sorry, I miss latest change in 
"tty: serial: samsung: Improve naming for common macro "

I will change it to bool.

> 
> >  	enum i2c_type_exynos	hw;
> >  };
> >
> >  static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
> >  	.fifo_depth	= 64,
> > +	.has_usi	= 0,
> 
> And this should be "false".
> 
> >  	.hw		= I2C_TYPE_EXYNOS5,
> >  };
> >
> >  static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
> >  	.fifo_depth	= 16,
> > +	.has_usi	= 0,
> >  	.hw		= I2C_TYPE_EXYNOS5,
> >  };
> >
> >  static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
> >  	.fifo_depth	= 16,
> > +	.has_usi	= 0,
> >  	.hw		= I2C_TYPE_EXYNOS7,
> >  };
> >
> > +static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {
> > +	.fifo_depth	= 64,
> > +	.has_usi	= 1,
> > +	.hw		= I2C_TYPE_EXYNOSAUTOV9,
> > +};
> > +
> >  static const struct of_device_id exynos5_i2c_match[] = {
> >  	{
> >  		.compatible = "samsung,exynos5-hsi2c", @@ -243,6 +271,9 @@ static
> > const struct of_device_id exynos5_i2c_match[] = {
> >  	}, {
> >  		.compatible = "samsung,exynos7-hsi2c",
> >  		.data = &exynos7_hsi2c_data
> > +	}, {
> > +		.compatible = "samsung,exynosautov9-hsi2c",
> > +		.data = &exynosautov9_hsi2c_data
> >  	}, {},
> >  };
> >  MODULE_DEVICE_TABLE(of, exynos5_i2c_match); @@ -281,6 +312,31 @@
> > static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
> >  		i2c->op_clock;
> >  	int div, clk_cycle, temp;
> >
> > +	/* In case of HSI2C controllers in EXYNOSAUTOV9
> 
> Linux coding comment please, so with a separate /* :
> 
> /*
>  * In case of....

I miss this.
I will change it next version.

> 
> Rest looks good, thanks for the changes!
> 
> Best regards,
> Krzysztof

Thanks
Jaewon Kim