* [PATCH 01/14] ARM: S5PV310: Adds clock addresses for S5PV310
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 02/14] ARM: S5PV310: Removed unused clock Kukjin Kim
` (13 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Kukjin Kim
This patch adds definition of clock address.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/include/mach/regs-clock.h | 29 +++++++++++++++++++++-
1 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 7727b45..eda07fd 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -26,11 +26,23 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
-
+#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
+#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
+#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
+#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
-
+#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
+#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
+#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
+#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
+#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
+#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
+#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
+#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
@@ -38,6 +50,19 @@
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
+#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
+#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
+#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
+
+#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
+#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
+#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
+#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 02/14] ARM: S5PV310: Removed unused clock
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
2010-08-18 14:01 ` [PATCH 01/14] ARM: S5PV310: Adds clock addresses for S5PV310 Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-19 2:57 ` MyungJoo Ham
2010-08-18 14:01 ` [PATCH 03/14] ARM: S5PV310: Adds clkset_aclk for removing clkset_aclk_xxx Kukjin Kim
` (12 subsequent siblings)
14 siblings, 1 reply; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Kukjin Kim
This pach removed unused clock on S5PV310/S5PC210.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 126 +----------------------------------------
1 files changed, 2 insertions(+), 124 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 77f2b4d..e3098d5 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -96,60 +96,6 @@ static struct clksrc_clk clk_armclk = {
},
};
-static struct clksrc_clk clk_aclk_corem0 = {
- .clk = {
- .name = "aclk_corem0",
- .id = -1,
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cores = {
- .clk = {
- .name = "aclk_cores",
- .id = -1,
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corem1 = {
- .clk = {
- .name = "aclk_corem1",
- .id = -1,
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_periphclk = {
- .clk = {
- .name = "periphclk",
- .id = -1,
- .parent = &clk_coreclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_atclk = {
- .clk = {
- .name = "atclk",
- .id = -1,
- .parent = &clk_moutcore.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_dbg = {
- .clk = {
- .name = "pclk_dbg",
- .id = -1,
- .parent = &clk_atclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
-};
-
/* Core list of CMU_CORE side */
static struct clk *clkset_corebus_list[] = {
@@ -180,42 +126,6 @@ static struct clksrc_clk clk_sclk_dmc = {
.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
};
-static struct clksrc_clk clk_aclk_cored = {
- .clk = {
- .name = "aclk_cored",
- .id = -1,
- .parent = &clk_sclk_dmc.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corep = {
- .clk = {
- .name = "aclk_corep",
- .id = -1,
- .parent = &clk_aclk_cored.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_acp = {
- .clk = {
- .name = "aclk_acp",
- .id = -1,
- .parent = &clk_mout_corebus.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_acp = {
- .clk = {
- .name = "pclk_acp",
- .id = -1,
- .parent = &clk_aclk_acp.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
-};
-
/* Core list of CMU_TOP side */
static struct clk *clkset_aclk_top_list[] = {
@@ -416,18 +326,8 @@ static struct clksrc_clk *sysclks[] = {
&clk_moutcore,
&clk_coreclk,
&clk_armclk,
- &clk_aclk_corem0,
- &clk_aclk_cores,
- &clk_aclk_corem1,
- &clk_periphclk,
- &clk_atclk,
- &clk_pclk_dbg,
&clk_mout_corebus,
&clk_sclk_dmc,
- &clk_aclk_cored,
- &clk_aclk_corep,
- &clk_aclk_acp,
- &clk_pclk_acp,
&clk_vpllsrc,
&clk_sclk_vpll,
&clk_aclk_200,
@@ -446,15 +346,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
unsigned long vpllsrc;
unsigned long xtal;
unsigned long armclk;
- unsigned long aclk_corem0;
- unsigned long aclk_cores;
- unsigned long aclk_corem1;
- unsigned long periphclk;
unsigned long sclk_dmc;
- unsigned long aclk_cored;
- unsigned long aclk_corep;
- unsigned long aclk_acp;
- unsigned long pclk_acp;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
@@ -485,26 +377,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
apll, mpll, epll, vpll);
armclk = clk_get_rate(&clk_armclk.clk);
- aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
- aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
- aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
- periphclk = clk_get_rate(&clk_periphclk.clk);
sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
- aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
- aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
- aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
- pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
-
- printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
- "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
- "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
- armclk, aclk_corem0, aclk_cores, aclk_corem1,
- periphclk, sclk_dmc, aclk_cored, aclk_corep,
- aclk_acp, pclk_acp);
+
+ printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc);
clk_f.rate = armclk;
clk_h.rate = sclk_dmc;
- clk_p.rate = periphclk;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 02/14] ARM: S5PV310: Removed unused clock
2010-08-18 14:01 ` [PATCH 02/14] ARM: S5PV310: Removed unused clock Kukjin Kim
@ 2010-08-19 2:57 ` MyungJoo Ham
2010-08-20 7:10 ` Kukjin Kim
0 siblings, 1 reply; 26+ messages in thread
From: MyungJoo Ham @ 2010-08-19 2:57 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc, ben-linux, linux-arm-kernel
Hello,
On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> This pach removed unused clock on S5PV310/S5PC210.
>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In this patch, you've removed corem0, corem1, cores, periph, atclk,
and pclk_dbg, which are directly affected by cpu-freq drivers. As long
as CPUFREQ uses clocks under 800MHz, corem0, corem1, cores, and
periph's dividers should be updated and as long as CPUFREQ uses clocks
over 800MHz, atclk and pclk_dbg's dividers should also be updated.
Although in the cpu-freq patches of S5PV210, the cpu-freq driver did
not use the clock framework and accessed clock registers directly, I
thought cpu-freq should consider using the clock framework later as,
sometimes, other drivers and modules are interested in the values
related with this domain (e.g., for the stability issues,
suspend-to-mem/disk may want to read and save the clock rates of CPU).
Do you think CPUFREQ should keep accessing the clock registers
directly? or should start using clock frameworks later?
ps. If we are going to change the bus speed as well (as in S5PV210's
100MHz mode), we may need to access aclk_cored, aclk_corep, and
aclk_acp as well.
> ---
> arch/arm/mach-s5pv310/clock.c | 126 +----------------------------------------
> 1 files changed, 2 insertions(+), 124 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
> index 77f2b4d..e3098d5 100644
> --- a/arch/arm/mach-s5pv310/clock.c
> +++ b/arch/arm/mach-s5pv310/clock.c
> @@ -96,60 +96,6 @@ static struct clksrc_clk clk_armclk = {
> },
> };
>
> -static struct clksrc_clk clk_aclk_corem0 = {
> - .clk = {
> - .name = "aclk_corem0",
> - .id = -1,
> - .parent = &clk_coreclk.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_aclk_cores = {
> - .clk = {
> - .name = "aclk_cores",
> - .id = -1,
> - .parent = &clk_coreclk.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_aclk_corem1 = {
> - .clk = {
> - .name = "aclk_corem1",
> - .id = -1,
> - .parent = &clk_coreclk.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_periphclk = {
> - .clk = {
> - .name = "periphclk",
> - .id = -1,
> - .parent = &clk_coreclk.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_atclk = {
> - .clk = {
> - .name = "atclk",
> - .id = -1,
> - .parent = &clk_moutcore.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_pclk_dbg = {
> - .clk = {
> - .name = "pclk_dbg",
> - .id = -1,
> - .parent = &clk_atclk.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
> -};
> -
> /* Core list of CMU_CORE side */
>
> static struct clk *clkset_corebus_list[] = {
> @@ -180,42 +126,6 @@ static struct clksrc_clk clk_sclk_dmc = {
> .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
> };
>
> -static struct clksrc_clk clk_aclk_cored = {
> - .clk = {
> - .name = "aclk_cored",
> - .id = -1,
> - .parent = &clk_sclk_dmc.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_aclk_corep = {
> - .clk = {
> - .name = "aclk_corep",
> - .id = -1,
> - .parent = &clk_aclk_cored.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_aclk_acp = {
> - .clk = {
> - .name = "aclk_acp",
> - .id = -1,
> - .parent = &clk_mout_corebus.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
> -};
> -
> -static struct clksrc_clk clk_pclk_acp = {
> - .clk = {
> - .name = "pclk_acp",
> - .id = -1,
> - .parent = &clk_aclk_acp.clk,
> - },
> - .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
> -};
> -
> /* Core list of CMU_TOP side */
>
> static struct clk *clkset_aclk_top_list[] = {
> @@ -416,18 +326,8 @@ static struct clksrc_clk *sysclks[] = {
> &clk_moutcore,
> &clk_coreclk,
> &clk_armclk,
> - &clk_aclk_corem0,
> - &clk_aclk_cores,
> - &clk_aclk_corem1,
> - &clk_periphclk,
> - &clk_atclk,
> - &clk_pclk_dbg,
> &clk_mout_corebus,
> &clk_sclk_dmc,
> - &clk_aclk_cored,
> - &clk_aclk_corep,
> - &clk_aclk_acp,
> - &clk_pclk_acp,
> &clk_vpllsrc,
> &clk_sclk_vpll,
> &clk_aclk_200,
> @@ -446,15 +346,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
> unsigned long vpllsrc;
> unsigned long xtal;
> unsigned long armclk;
> - unsigned long aclk_corem0;
> - unsigned long aclk_cores;
> - unsigned long aclk_corem1;
> - unsigned long periphclk;
> unsigned long sclk_dmc;
> - unsigned long aclk_cored;
> - unsigned long aclk_corep;
> - unsigned long aclk_acp;
> - unsigned long pclk_acp;
> unsigned int ptr;
>
> printk(KERN_DEBUG "%s: registering clocks\n", __func__);
> @@ -485,26 +377,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
> apll, mpll, epll, vpll);
>
> armclk = clk_get_rate(&clk_armclk.clk);
> - aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
> - aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
> - aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
> - periphclk = clk_get_rate(&clk_periphclk.clk);
> sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
> - aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
> - aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
> - aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
> - pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
> -
> - printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
> - "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
> - "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
> - armclk, aclk_corem0, aclk_cores, aclk_corem1,
> - periphclk, sclk_dmc, aclk_cored, aclk_corep,
> - aclk_acp, pclk_acp);
> +
> + printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc);
>
> clk_f.rate = armclk;
> clk_h.rate = sclk_dmc;
> - clk_p.rate = periphclk;
>
> for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
> s3c_set_clksrc(&clksrcs[ptr], true);
> --
> 1.6.2.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 02/14] ARM: S5PV310: Removed unused clock
2010-08-19 2:57 ` MyungJoo Ham
@ 2010-08-20 7:10 ` Kukjin Kim
0 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-20 7:10 UTC (permalink / raw)
To: 'MyungJoo Ham'; +Cc: linux-arm-kernel, linux-samsung-soc, ben-linux
MyungJoo Ham wrote:
>
> Hello,
>
Hi :-)
> On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> > This pach removed unused clock on S5PV310/S5PC210.
> >
> > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
>
> In this patch, you've removed corem0, corem1, cores, periph, atclk,
> and pclk_dbg, which are directly affected by cpu-freq drivers. As long
> as CPUFREQ uses clocks under 800MHz, corem0, corem1, cores, and
> periph's dividers should be updated and as long as CPUFREQ uses clocks
> over 800MHz, atclk and pclk_dbg's dividers should also be updated.
> Although in the cpu-freq patches of S5PV210, the cpu-freq driver did
> not use the clock framework and accessed clock registers directly, I
> thought cpu-freq should consider using the clock framework later as,
> sometimes, other drivers and modules are interested in the values
> related with this domain (e.g., for the stability issues,
> suspend-to-mem/disk may want to read and save the clock rates of CPU).
>
> Do you think CPUFREQ should keep accessing the clock registers
> directly? or should start using clock frameworks later?
>
> ps. If we are going to change the bus speed as well (as in S5PV210's
> 100MHz mode), we may need to access aclk_cored, aclk_corep, and
> aclk_acp as well.
>
Basically, no need to control them when changed frequency because can be restored original value.
But I think need to check it again.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/14] ARM: S5PV310: Adds clkset_aclk for removing clkset_aclk_xxx
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
2010-08-18 14:01 ` [PATCH 01/14] ARM: S5PV310: Adds clock addresses for S5PV310 Kukjin Kim
2010-08-18 14:01 ` [PATCH 02/14] ARM: S5PV310: Removed unused clock Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 04/14] ARM: S5PV310: Fix on PLL setting for S5PV310 Kukjin Kim
` (11 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Kukjin Kim
This patch adds 'clkset_aclk' to use commonly. And removed struct
clksrc_sources clkset_aclk_200, clkset_aclk_100, clkset_aclk_160,
and clkset_aclk_133.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 25 +++++--------------------
1 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index e3098d5..d909515 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -133,7 +133,7 @@ static struct clk *clkset_aclk_top_list[] = {
[1] = &clk_mout_apll.clk,
};
-static struct clksrc_sources clkset_aclk_200 = {
+static struct clksrc_sources clkset_aclk = {
.sources = clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
};
@@ -143,52 +143,37 @@ static struct clksrc_clk clk_aclk_200 = {
.name = "aclk_200",
.id = -1,
},
- .sources = &clkset_aclk_200,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
};
-static struct clksrc_sources clkset_aclk_100 = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
static struct clksrc_clk clk_aclk_100 = {
.clk = {
.name = "aclk_100",
.id = -1,
},
- .sources = &clkset_aclk_100,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
};
-static struct clksrc_sources clkset_aclk_160 = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
static struct clksrc_clk clk_aclk_160 = {
.clk = {
.name = "aclk_160",
.id = -1,
},
- .sources = &clkset_aclk_160,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
};
-static struct clksrc_sources clkset_aclk_133 = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
static struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
.id = -1,
},
- .sources = &clkset_aclk_133,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
};
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 04/14] ARM: S5PV310: Fix on PLL setting for S5PV310
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (2 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 03/14] ARM: S5PV310: Adds clkset_aclk for removing clkset_aclk_xxx Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 05/14] ARM: S5PV310: Adds clk_sclk_usbphy0, _usbphy1, and _hdmiphy Kukjin Kim
` (10 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch fixes on PLL setting for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index d909515..c60d3b0 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -347,11 +347,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
- __raw_readl(S5P_EPLL_CON1), pll_4500);
+ __raw_readl(S5P_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
- __raw_readl(S5P_VPLL_CON1), pll_4502);
+ __raw_readl(S5P_VPLL_CON1), pll_4650);
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 05/14] ARM: S5PV310: Adds clk_sclk_usbphy0, _usbphy1, and _hdmiphy
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (3 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 04/14] ARM: S5PV310: Fix on PLL setting for S5PV310 Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 06/14] ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll Kukjin Kim
` (9 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds struct clk clk_sclk_usbphy0, _usbphy1, and _hdmiphy
for adding member of clkset_group_list.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index c60d3b0..892259b 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,6 +30,22 @@ static struct clk clk_sclk_hdmi27m = {
.rate = 27000000,
};
+static struct clk clk_sclk_hdmiphy = {
+ .name = "sclk_hdmiphy",
+ .id = -1,
+};
+
+static struct clk clk_sclk_usbphy0 = {
+ .name = "sclk_usbphy0",
+ .id = -1,
+ .rate = 27000000,
+};
+
+static struct clk clk_sclk_usbphy1 = {
+ .name = "sclk_usbphy1",
+ .id = -1,
+};
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -239,6 +255,9 @@ static struct clk *clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
[2] = &clk_sclk_hdmi27m,
+ [3] = &clk_sclk_usbphy0,
+ [4] = &clk_sclk_usbphy1,
+ [5] = &clk_sclk_hdmiphy,
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
[8] = &clk_sclk_vpll.clk,
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 06/14] ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (4 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 05/14] ARM: S5PV310: Adds clk_sclk_usbphy0, _usbphy1, and _hdmiphy Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 07/14] ARM: S5PV310: Adds printing ACLK200, ACLK100, ACLK160 and ACLK133 Kukjin Kim
` (8 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds clk_sclk_apll so that fixes on clk_mout_apll.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 15 ++++++++++++---
1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 892259b..8ffda6e 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -55,6 +55,14 @@ static struct clksrc_clk clk_mout_apll = {
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_apll = {
+ .clk = {
+ .name = "sclk_apll",
+ .id = -1,
+ .parent = &clk_mout_apll.clk,
+ },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};
@@ -77,7 +85,7 @@ static struct clksrc_clk clk_mout_mpll = {
};
static struct clk *clkset_moutcore_list[] = {
- [0] = &clk_mout_apll.clk,
+ [0] = &clk_sclk_apll.clk,
[1] = &clk_mout_mpll.clk,
};
@@ -116,7 +124,7 @@ static struct clksrc_clk clk_armclk = {
static struct clk *clkset_corebus_list[] = {
[0] = &clk_mout_mpll.clk,
- [1] = &clk_mout_apll.clk,
+ [1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_mout_corebus = {
@@ -146,7 +154,7 @@ static struct clksrc_clk clk_sclk_dmc = {
static struct clk *clkset_aclk_top_list[] = {
[0] = &clk_mout_mpll.clk,
- [1] = &clk_mout_apll.clk,
+ [1] = &clk_sclk_apll.clk,
};
static struct clksrc_sources clkset_aclk = {
@@ -325,6 +333,7 @@ static struct clksrc_clk clksrcs[] = {
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
+ &clk_sclk_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_moutcore,
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 07/14] ARM: S5PV310: Adds printing ACLK200, ACLK100, ACLK160 and ACLK133
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (5 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 06/14] ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 08/14] ARM: S5PV310: Adds enable and ctrlbit for clk_vpllsrc Kukjin Kim
` (7 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds log messages of aclk_200, aclk_100, aclk_160, and
aclk_133. And adds clk_p.rate from calculated aclk_100.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 8ffda6e..cc583c1 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -360,6 +360,10 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
unsigned long xtal;
unsigned long armclk;
unsigned long sclk_dmc;
+ unsigned long aclk_200;
+ unsigned long aclk_100;
+ unsigned long aclk_160;
+ unsigned long aclk_133;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
@@ -392,10 +396,19 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
armclk = clk_get_rate(&clk_armclk.clk);
sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
- printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld\n", armclk, sclk_dmc);
+ aclk_200 = clk_get_rate(&clk_aclk_200.clk);
+ aclk_100 = clk_get_rate(&clk_aclk_100.clk);
+ aclk_160 = clk_get_rate(&clk_aclk_160.clk);
+ aclk_133 = clk_get_rate(&clk_aclk_133.clk);
+
+ printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+ "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+ armclk, sclk_dmc, aclk_200,
+ aclk_100, aclk_160, aclk_133);
clk_f.rate = armclk;
clk_h.rate = sclk_dmc;
+ clk_p.rate = aclk_100;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 08/14] ARM: S5PV310: Adds enable and ctrlbit for clk_vpllsrc
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (6 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 07/14] ARM: S5PV310: Adds printing ACLK200, ACLK100, ACLK160 and ACLK133 Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 09/14] ARM: S5PV310: Adds SDMMC clock for S5PV310 Kukjin Kim
` (6 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds enable and ctrlbit for struct clksrc_clk clk_vpllsrc
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index cc583c1..c3ee742 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -46,6 +46,11 @@ static struct clk clk_sclk_usbphy1 = {
.id = -1,
};
+static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -216,6 +221,8 @@ static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.id = -1,
+ .enable = s5pv310_clksrc_mask_top_ctrl,
+ .ctrlbit = (1 << 0),
},
.sources = &clkset_vpllsrc,
.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 09/14] ARM: S5PV310: Adds SDMMC clock for S5PV310
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (7 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 08/14] ARM: S5PV310: Adds enable and ctrlbit for clk_vpllsrc Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 10/14] ARM: S5PV310: Adds uart clocks Kukjin Kim
` (5 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds SDMMC clocks for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 142 ++++++++++++++++++++++++++++++++++++++++-
1 files changed, 141 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index c3ee742..8728504 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -51,6 +51,16 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
}
+static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -259,6 +269,36 @@ static struct clk init_clocks_disable[] = {
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
+ }, {
+ .name = "hsmmc",
+ .id = 0,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "hsmmc",
+ .id = 1,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "hsmmc",
+ .id = 2,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "hsmmc",
+ .id = 3,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "hsmmc",
+ .id = 4,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 9),
}
};
@@ -283,6 +323,56 @@ static struct clksrc_sources clkset_group = {
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
+static struct clksrc_clk clk_dout_mmc0 = {
+ .clk = {
+ .name = "dout_mmc0",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc1 = {
+ .clk = {
+ .name = "dout_mmc1",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc2 = {
+ .clk = {
+ .name = "dout_mmc2",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc3 = {
+ .clk = {
+ .name = "dout_mmc3",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc4 = {
+ .clk = {
+ .name = "dout_mmc4",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
static struct clksrc_clk clksrcs[] = {
{
.clk = {
@@ -334,7 +424,52 @@ static struct clksrc_clk clksrcs[] = {
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
- },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 0,
+ .parent = &clk_dout_mmc0.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 1,
+ .parent = &clk_dout_mmc1.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 2,
+ .parent = &clk_dout_mmc2.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 3,
+ .parent = &clk_dout_mmc3.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 4,
+ .parent = &clk_dout_mmc4.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+ }
};
/* Clock initialization code */
@@ -354,6 +489,11 @@ static struct clksrc_clk *sysclks[] = {
&clk_aclk_100,
&clk_aclk_160,
&clk_aclk_133,
+ &clk_dout_mmc0,
+ &clk_dout_mmc1,
+ &clk_dout_mmc2,
+ &clk_dout_mmc3,
+ &clk_dout_mmc4,
};
void __init_or_cpufreq s5pv310_setup_clocks(void)
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 10/14] ARM: S5PV310: Adds uart clocks
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (8 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 09/14] ARM: S5PV310: Adds SDMMC clock for S5PV310 Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-19 8:40 ` MyungJoo Ham
2010-08-18 14:01 ` [PATCH 11/14] ARM: S5PV310: Bug fix on uclk1 and sclk_pwm Kukjin Kim
` (4 subsequent siblings)
14 siblings, 1 reply; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds uart clocks for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 37 +++++++++++++++++++++++++++++++------
1 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 8728504..843f4d0 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -61,6 +61,11 @@ static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
}
+static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
@@ -257,11 +262,6 @@ static struct clksrc_clk clk_sclk_vpll = {
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
};
-static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
static struct clk init_clocks_disable[] = {
{
.name = "timers",
@@ -303,7 +303,32 @@ static struct clk init_clocks_disable[] = {
};
static struct clk init_clocks[] = {
- /* Nothing here yet */
+ {
+ .name = "uart",
+ .id = 1,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "uart",
+ .id = 2,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "uart",
+ .id = 3,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "uart",
+ .id = 4,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "uart",
+ .id = 5,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 5),
+ }
};
static struct clk *clkset_group_list[] = {
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 10/14] ARM: S5PV310: Adds uart clocks
2010-08-18 14:01 ` [PATCH 10/14] ARM: S5PV310: Adds uart clocks Kukjin Kim
@ 2010-08-19 8:40 ` MyungJoo Ham
2010-08-20 6:58 ` Kukjin Kim
0 siblings, 1 reply; 26+ messages in thread
From: MyungJoo Ham @ 2010-08-19 8:40 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc, Jongpill Lee, ben-linux
Hello,
Did you intentionally omit uart:0? Then, why uart:0 clock is not being
registered while other uart clocks are?
On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> From: Jongpill Lee <boyko.lee@samsung.com>
>
> This patch adds uart clocks for S5PV310/S5PC210.
>
> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> arch/arm/mach-s5pv310/clock.c | 37 +++++++++++++++++++++++++++++++------
> 1 files changed, 31 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
> index 8728504..843f4d0 100644
> --- a/arch/arm/mach-s5pv310/clock.c
> +++ b/arch/arm/mach-s5pv310/clock.c
> @@ -61,6 +61,11 @@ static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
> return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
> }
>
> +static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
> +}
> +
> /* Core list of CMU_CPU side */
>
> static struct clksrc_clk clk_mout_apll = {
> @@ -257,11 +262,6 @@ static struct clksrc_clk clk_sclk_vpll = {
> .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
> };
>
> -static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
> -{
> - return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
> -}
> -
> static struct clk init_clocks_disable[] = {
> {
> .name = "timers",
> @@ -303,7 +303,32 @@ static struct clk init_clocks_disable[] = {
> };
>
> static struct clk init_clocks[] = {
> - /* Nothing here yet */
> + {
> + .name = "uart",
> + .id = 1,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 1),
> + }, {
> + .name = "uart",
> + .id = 2,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 2),
> + }, {
> + .name = "uart",
> + .id = 3,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 3),
> + }, {
> + .name = "uart",
> + .id = 4,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 4),
> + }, {
> + .name = "uart",
> + .id = 5,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 5),
> + }
> };
>
> static struct clk *clkset_group_list[] = {
> --
> 1.6.2.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 10/14] ARM: S5PV310: Adds uart clocks
2010-08-19 8:40 ` MyungJoo Ham
@ 2010-08-20 6:58 ` Kukjin Kim
0 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-20 6:58 UTC (permalink / raw)
To: 'MyungJoo Ham'
Cc: linux-arm-kernel, linux-samsung-soc, 'Jongpill Lee',
ben-linux
MyungJoo Ham wrote:
>
> Hello,
>
Hi,
> Did you intentionally omit uart:0? Then, why uart:0 clock is not being
> registered while other uart clocks are?
>
Just missed...thanks for finding it.
Will fix it.
> On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com>
wrote:
> > From: Jongpill Lee <boyko.lee@samsung.com>
> >
> > This patch adds uart clocks for S5PV310/S5PC210.
> >
> > Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > ---
> > arch/arm/mach-s5pv310/clock.c | 37
> +++++++++++++++++++++++++++++++------
> > 1 files changed, 31 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/mach-s5pv310/clock.c
b/arch/arm/mach-s5pv310/clock.c
> > index 8728504..843f4d0 100644
> > --- a/arch/arm/mach-s5pv310/clock.c
> > +++ b/arch/arm/mach-s5pv310/clock.c
> > @@ -61,6 +61,11 @@ static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk,
int
> enable)
> > return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
> > }
> >
> > +static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
> > +{
> > + return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
> > +}
> > +
> > /* Core list of CMU_CPU side */
> >
> > static struct clksrc_clk clk_mout_apll = {
> > @@ -257,11 +262,6 @@ static struct clksrc_clk clk_sclk_vpll = {
> > .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1
},
> > };
> >
> > -static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
> > -{
> > - return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
> > -}
> > -
> > static struct clk init_clocks_disable[] = {
> > {
> > .name = "timers",
> > @@ -303,7 +303,32 @@ static struct clk init_clocks_disable[] = {
> > };
> >
> > static struct clk init_clocks[] = {
> > - /* Nothing here yet */
> > + {
> > + .name = "uart",
> > + .id = 1,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
> > + .ctrlbit = (1 << 1),
> > + }, {
> > + .name = "uart",
> > + .id = 2,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
> > + .ctrlbit = (1 << 2),
> > + }, {
> > + .name = "uart",
> > + .id = 3,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
> > + .ctrlbit = (1 << 3),
> > + }, {
> > + .name = "uart",
> > + .id = 4,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
> > + .ctrlbit = (1 << 4),
> > + }, {
> > + .name = "uart",
> > + .id = 5,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
> > + .ctrlbit = (1 << 5),
> > + }
> > };
> >
> > static struct clk *clkset_group_list[] = {
> > --
> > 1.6.2.5
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 11/14] ARM: S5PV310: Bug fix on uclk1 and sclk_pwm
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (9 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 10/14] ARM: S5PV310: Adds uart clocks Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-18 14:01 ` [PATCH 12/14] ARM: S5PV310: Add various clocks Kukjin Kim
` (3 subsequent siblings)
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch fixes on enable and ctrlbit of uclk1 and sclk_pwm.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 21 +++++++++++++--------
1 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 843f4d0..ec69edc 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -56,6 +56,11 @@ static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
}
+static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
@@ -403,8 +408,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 0,
+ .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
- .enable = s5pv310_clk_ip_peril_ctrl,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@@ -413,8 +418,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 1,
- .enable = s5pv310_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 1),
+ .enable = s5pv310_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 4),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -423,8 +428,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 2,
- .enable = s5pv310_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 2),
+ .enable = s5pv310_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 8),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -433,8 +438,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 3,
- .enable = s5pv310_clk_ip_peril_ctrl,
- .ctrlbit = (1 << 3),
+ .enable = s5pv310_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 12),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -443,7 +448,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_pwm",
.id = -1,
- .enable = s5pv310_clk_ip_peril_ctrl,
+ .enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 12/14] ARM: S5PV310: Add various clocks
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (10 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 11/14] ARM: S5PV310: Bug fix on uclk1 and sclk_pwm Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-19 8:52 ` MyungJoo Ham
2010-08-18 14:01 ` [PATCH 13/14] ARM: S5PV310: Add video clocks Kukjin Kim
` (2 subsequent siblings)
14 siblings, 1 reply; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds clocks for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 155 ++++++++++++++++++++++++++++++++++++++++-
1 files changed, 154 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index ec69edc..14c9707 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -61,6 +61,26 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
+static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
+}
+
+static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
+}
+
static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
@@ -275,6 +295,46 @@ static struct clk init_clocks_disable[] = {
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
}, {
+ .name = "csis",
+ .id = 0,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "csis",
+ .id = 1,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "fimc",
+ .id = 0,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "fimc",
+ .id = 1,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "fimc",
+ .id = 2,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "fimc",
+ .id = 3,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "fimd",
+ .id = 0,
+ .enable = s5pv310_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "fimd",
+ .id = 1,
+ .enable = s5pv310_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
.name = "hsmmc",
.id = 0,
.parent = &clk_aclk_133.clk,
@@ -304,7 +364,100 @@ static struct clk init_clocks_disable[] = {
.parent = &clk_aclk_133.clk,
.enable = s5pv310_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
- }
+ }, {
+ .name = "sata",
+ .id = -1,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "adc",
+ .id = -1,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "watchdog",
+ .id = -1,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "usbhost",
+ .id = -1,
+ .enable = s5pv310_clk_ip_fsys_ctrl ,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "otg",
+ .id = -1,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "spi",
+ .id = 0,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .id = 1,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .id = 2,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "fimg2d",
+ .id = -1,
+ .enable = s5pv310_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "i2c",
+ .id = 0,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "i2c",
+ .id = 1,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "i2c",
+ .id = 2,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "i2c",
+ .id = 3,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "i2c",
+ .id = 4,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "i2c",
+ .id = 5,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "i2c",
+ .id = 6,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "i2c",
+ .id = 7,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 13),
+ },
};
static struct clk init_clocks[] = {
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 12/14] ARM: S5PV310: Add various clocks
2010-08-18 14:01 ` [PATCH 12/14] ARM: S5PV310: Add various clocks Kukjin Kim
@ 2010-08-19 8:52 ` MyungJoo Ham
2010-08-20 7:00 ` Kukjin Kim
0 siblings, 1 reply; 26+ messages in thread
From: MyungJoo Ham @ 2010-08-19 8:52 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc, Jongpill Lee, ben-linux, linux-arm-kernel
On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> From: Jongpill Lee <boyko.lee@samsung.com>
>
> This patch adds clocks for S5PV310/S5PC210.
>
> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> arch/arm/mach-s5pv310/clock.c | 155 ++++++++++++++++++++++++++++++++++++++++-
> 1 files changed, 154 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
> index ec69edc..14c9707 100644
> --- a/arch/arm/mach-s5pv310/clock.c
> +++ b/arch/arm/mach-s5pv310/clock.c
> @@ -61,6 +61,26 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
> return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
> }
>
> +static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
> +}
> +
> +static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
> +}
> +
> +static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
> +}
> +
> +static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
> +{
> + return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
> +}
> +
> static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
> {
> return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
> @@ -275,6 +295,46 @@ static struct clk init_clocks_disable[] = {
> .enable = s5pv310_clk_ip_peril_ctrl,
> .ctrlbit = (1<<24),
> }, {
> + .name = "csis",
> + .id = 0,
> + .enable = s5pv310_clk_ip_cam_ctrl,
> + .ctrlbit = (1 << 4),
> + }, {
> + .name = "csis",
> + .id = 1,
> + .enable = s5pv310_clk_ip_cam_ctrl,
> + .ctrlbit = (1 << 5),
> + }, {
> + .name = "fimc",
> + .id = 0,
> + .enable = s5pv310_clk_ip_cam_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> + .name = "fimc",
> + .id = 1,
> + .enable = s5pv310_clk_ip_cam_ctrl,
> + .ctrlbit = (1 << 1),
> + }, {
> + .name = "fimc",
> + .id = 2,
> + .enable = s5pv310_clk_ip_cam_ctrl,
> + .ctrlbit = (1 << 2),
> + }, {
> + .name = "fimc",
> + .id = 3,
> + .enable = s5pv310_clk_ip_cam_ctrl,
> + .ctrlbit = (1 << 3),
> + }, {
> + .name = "fimd",
> + .id = 0,
> + .enable = s5pv310_clk_ip_lcd0_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> + .name = "fimd",
> + .id = 1,
> + .enable = s5pv310_clk_ip_lcd1_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> .name = "hsmmc",
> .id = 0,
> .parent = &clk_aclk_133.clk,
> @@ -304,7 +364,100 @@ static struct clk init_clocks_disable[] = {
> .parent = &clk_aclk_133.clk,
> .enable = s5pv310_clk_ip_fsys_ctrl,
> .ctrlbit = (1 << 9),
> - }
> + }, {
> + .name = "sata",
> + .id = -1,
> + .enable = s5pv310_clk_ip_fsys_ctrl,
> + .ctrlbit = (1 << 10),
> + }, {
> + .name = "adc",
> + .id = -1,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 15),
> + }, {
> + .name = "watchdog",
> + .id = -1,
> + .enable = s5pv310_clk_ip_peril_ctrl,
s5pv310_clk_ip_perir_ctrl (R, not L) appears to be correct for this entry.
Probably, we may need to sort these according to .enable entry (and
then .ctrlbit entry) later.
> + .ctrlbit = (1 << 14),
> + }, {
> + .name = "usbhost",
> + .id = -1,
> + .enable = s5pv310_clk_ip_fsys_ctrl ,
> + .ctrlbit = (1 << 12),
> + }, {
> + .name = "otg",
> + .id = -1,
> + .enable = s5pv310_clk_ip_fsys_ctrl,
> + .ctrlbit = (1 << 13),
> + }, {
> + .name = "spi",
> + .id = 0,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 16),
> + }, {
> + .name = "spi",
> + .id = 1,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 17),
> + }, {
> + .name = "spi",
> + .id = 2,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 18),
> + }, {
> + .name = "fimg2d",
> + .id = -1,
> + .enable = s5pv310_clk_ip_image_ctrl,
> + .ctrlbit = (1 << 0),
> + }, {
> + .name = "i2c",
> + .id = 0,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 6),
> + }, {
> + .name = "i2c",
> + .id = 1,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 7),
> + }, {
> + .name = "i2c",
> + .id = 2,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 8),
> + }, {
> + .name = "i2c",
> + .id = 3,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 9),
> + }, {
> + .name = "i2c",
> + .id = 4,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 10),
> + }, {
> + .name = "i2c",
> + .id = 5,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 11),
> + }, {
> + .name = "i2c",
> + .id = 6,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 12),
> + }, {
> + .name = "i2c",
> + .id = 7,
> + .parent = &clk_aclk_100.clk,
> + .enable = s5pv310_clk_ip_peril_ctrl,
> + .ctrlbit = (1 << 13),
> + },
> };
>
> static struct clk init_clocks[] = {
> --
> 1.6.2.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 12/14] ARM: S5PV310: Add various clocks
2010-08-19 8:52 ` MyungJoo Ham
@ 2010-08-20 7:00 ` Kukjin Kim
0 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-20 7:00 UTC (permalink / raw)
To: 'MyungJoo Ham'
Cc: linux-arm-kernel, linux-samsung-soc, 'Jongpill Lee',
ben-linux
MyungJoo Ham wrote:
>
> On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com>
wrote:
> > From: Jongpill Lee <boyko.lee@samsung.com>
> >
> > This patch adds clocks for S5PV310/S5PC210.
> >
> > Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> > ---
> > arch/arm/mach-s5pv310/clock.c | 155
> ++++++++++++++++++++++++++++++++++++++++-
> > 1 files changed, 154 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/mach-s5pv310/clock.c
b/arch/arm/mach-s5pv310/clock.c
> > index ec69edc..14c9707 100644
> > --- a/arch/arm/mach-s5pv310/clock.c
> > +++ b/arch/arm/mach-s5pv310/clock.c
> > @@ -61,6 +61,26 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk
*clk,
> int enable)
> > return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
> > }
> >
> > +static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
> > +{
> > + return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
> > +}
> > +
> > +static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
> > +{
> > + return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
> > +}
> > +
> > +static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
> > +{
> > + return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
> > +}
> > +
> > +static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
> > +{
> > + return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
> > +}
> > +
> > static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
> > {
> > return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
> > @@ -275,6 +295,46 @@ static struct clk init_clocks_disable[] = {
> > .enable = s5pv310_clk_ip_peril_ctrl,
> > .ctrlbit = (1<<24),
> > }, {
> > + .name = "csis",
> > + .id = 0,
> > + .enable = s5pv310_clk_ip_cam_ctrl,
> > + .ctrlbit = (1 << 4),
> > + }, {
> > + .name = "csis",
> > + .id = 1,
> > + .enable = s5pv310_clk_ip_cam_ctrl,
> > + .ctrlbit = (1 << 5),
> > + }, {
> > + .name = "fimc",
> > + .id = 0,
> > + .enable = s5pv310_clk_ip_cam_ctrl,
> > + .ctrlbit = (1 << 0),
> > + }, {
> > + .name = "fimc",
> > + .id = 1,
> > + .enable = s5pv310_clk_ip_cam_ctrl,
> > + .ctrlbit = (1 << 1),
> > + }, {
> > + .name = "fimc",
> > + .id = 2,
> > + .enable = s5pv310_clk_ip_cam_ctrl,
> > + .ctrlbit = (1 << 2),
> > + }, {
> > + .name = "fimc",
> > + .id = 3,
> > + .enable = s5pv310_clk_ip_cam_ctrl,
> > + .ctrlbit = (1 << 3),
> > + }, {
> > + .name = "fimd",
> > + .id = 0,
> > + .enable = s5pv310_clk_ip_lcd0_ctrl,
> > + .ctrlbit = (1 << 0),
> > + }, {
> > + .name = "fimd",
> > + .id = 1,
> > + .enable = s5pv310_clk_ip_lcd1_ctrl,
> > + .ctrlbit = (1 << 0),
> > + }, {
> > .name = "hsmmc",
> > .id = 0,
> > .parent = &clk_aclk_133.clk,
> > @@ -304,7 +364,100 @@ static struct clk init_clocks_disable[] = {
> > .parent = &clk_aclk_133.clk,
> > .enable = s5pv310_clk_ip_fsys_ctrl,
> > .ctrlbit = (1 << 9),
> > - }
> > + }, {
> > + .name = "sata",
> > + .id = -1,
> > + .enable = s5pv310_clk_ip_fsys_ctrl,
> > + .ctrlbit = (1 << 10),
> > + }, {
> > + .name = "adc",
> > + .id = -1,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
> > + .ctrlbit = (1 << 15),
> > + }, {
> > + .name = "watchdog",
> > + .id = -1,
> > + .enable = s5pv310_clk_ip_peril_ctrl,
>
> s5pv310_clk_ip_perir_ctrl (R, not L) appears to be correct for this entry.
>
> Probably, we may need to sort these according to .enable entry (and
> then .ctrlbit entry) later.
>
You're right. will fix it.
(snip)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 13/14] ARM: S5PV310: Add video clocks
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (11 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 12/14] ARM: S5PV310: Add various clocks Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-19 10:04 ` MyungJoo Ham
2010-08-18 14:01 ` [PATCH 14/14] ARM: S5PV310: Adds various special clocks Kukjin Kim
2010-08-23 2:05 ` [PATCH 00/14] ARM: S5PV310: Updates clock Kyungmin Park
14 siblings, 1 reply; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds video clocks for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 74 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 14c9707..04bde94 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -506,6 +506,78 @@ static struct clksrc_sources clkset_group = {
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
+static struct clksrc_clk clk_sclk_mipidphy4l = {
+ .clk = {
+ .name = "sclk_mipidphy4l",
+ .id = -1,
+ .enable = s5pv310_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mipidphy2l = {
+ .clk = {
+ .name = "sclk_mipidphy2l",
+ .id = -1,
+ .enable = s5pv310_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 16, .size = 4 },
+};
+
+static struct clk *clkset_mout_g2d0_list[] = {
+ [0] = &clk_mout_mpll.clk,
+ [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d0 = {
+ .sources = clkset_mout_g2d0_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk clk_mout_g2d0 = {
+ .clk = {
+ .name = "mout_g2d0",
+ .id = -1,
+ },
+ .sources = &clkset_mout_g2d0,
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d1_list[] = {
+ [0] = &clk_mout_epll.clk,
+ [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d1 = {
+ .sources = clkset_mout_g2d1_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk clk_mout_g2d1 = {
+ .clk = {
+ .name = "mout_g2d1",
+ .id = -1,
+ },
+ .sources = &clkset_mout_g2d1,
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d_list[] = {
+ [0] = &clk_mout_g2d0.clk,
+ [1] = &clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d = {
+ .sources = clkset_mout_g2d_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
+};
+
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
@@ -672,6 +744,8 @@ static struct clksrc_clk *sysclks[] = {
&clk_aclk_100,
&clk_aclk_160,
&clk_aclk_133,
+ &clk_sclk_mipidphy4l,
+ &clk_sclk_mipidphy2l,
&clk_dout_mmc0,
&clk_dout_mmc1,
&clk_dout_mmc2,
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 13/14] ARM: S5PV310: Add video clocks
2010-08-18 14:01 ` [PATCH 13/14] ARM: S5PV310: Add video clocks Kukjin Kim
@ 2010-08-19 10:04 ` MyungJoo Ham
2010-08-19 10:28 ` MyungJoo Ham
0 siblings, 1 reply; 26+ messages in thread
From: MyungJoo Ham @ 2010-08-19 10:04 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-samsung-soc, Jongpill Lee, ben-linux, linux-arm-kernel
On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> From: Jongpill Lee <boyko.lee@samsung.com>
>
> This patch adds video clocks for S5PV310/S5PC210.
>
> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> ---
> arch/arm/mach-s5pv310/clock.c | 74 +++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 74 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
> index 14c9707..04bde94 100644
> --- a/arch/arm/mach-s5pv310/clock.c
> +++ b/arch/arm/mach-s5pv310/clock.c
> @@ -506,6 +506,78 @@ static struct clksrc_sources clkset_group = {
> .nr_sources = ARRAY_SIZE(clkset_group_list),
> };
>
> +static struct clksrc_clk clk_sclk_mipidphy4l = {
> + .clk = {
> + .name = "sclk_mipidphy4l",
> + .id = -1,
> + .enable = s5pv310_clk_ip_lcd0_ctrl,
> + .ctrlbit = (1 << 4),
> + },
> + .sources = &clkset_group,
> + .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 12, .size = 4 },
> + .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 16, .size = 4 },
> +};
It appears that clk_ip_lcd0[4](CLK_SMMUFIMD0) is not for this clock
source. This SCLK_MIPIDPHY4L seems to be masked by
CLK_SRC_MASK_LCD0[12] (MIPI0_MASK)
> +
> +static struct clksrc_clk clk_sclk_mipidphy2l = {
> + .clk = {
> + .name = "sclk_mipidphy2l",
> + .id = -1,
> + .enable = s5pv310_clk_ip_lcd1_ctrl,
> + .ctrlbit = (1 << 4),
> + },
> + .sources = &clkset_group,
> + .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 12, .size = 4 },
> + .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 16, .size = 4 },
> +};
Appears to have the similar issue with the previous clock source
> +
> +static struct clk *clkset_mout_g2d0_list[] = {
> + [0] = &clk_mout_mpll.clk,
> + [1] = &clk_sclk_apll.clk,
> +};
> +
> +static struct clksrc_sources clkset_mout_g2d0 = {
> + .sources = clkset_mout_g2d0_list,
> + .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
> +};
> +
> +static struct clksrc_clk clk_mout_g2d0 = {
> + .clk = {
> + .name = "mout_g2d0",
> + .id = -1,
> + },
> + .sources = &clkset_mout_g2d0,
> + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
> +};
> +
> +static struct clk *clkset_mout_g2d1_list[] = {
> + [0] = &clk_mout_epll.clk,
> + [1] = &clk_sclk_vpll.clk,
> +};
> +
> +static struct clksrc_sources clkset_mout_g2d1 = {
> + .sources = clkset_mout_g2d1_list,
> + .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
> +};
> +
> +static struct clksrc_clk clk_mout_g2d1 = {
> + .clk = {
> + .name = "mout_g2d1",
> + .id = -1,
> + },
> + .sources = &clkset_mout_g2d1,
> + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
> +};
> +
> +static struct clk *clkset_mout_g2d_list[] = {
> + [0] = &clk_mout_g2d0.clk,
> + [1] = &clk_mout_g2d1.clk,
> +};
> +
> +static struct clksrc_sources clkset_mout_g2d = {
> + .sources = clkset_mout_g2d_list,
> + .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
> +};
> +
> static struct clksrc_clk clk_dout_mmc0 = {
> .clk = {
> .name = "dout_mmc0",
> @@ -672,6 +744,8 @@ static struct clksrc_clk *sysclks[] = {
> &clk_aclk_100,
> &clk_aclk_160,
> &clk_aclk_133,
> + &clk_sclk_mipidphy4l,
> + &clk_sclk_mipidphy2l,
> &clk_dout_mmc0,
> &clk_dout_mmc1,
> &clk_dout_mmc2,
> --
> 1.6.2.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH 13/14] ARM: S5PV310: Add video clocks
2010-08-19 10:04 ` MyungJoo Ham
@ 2010-08-19 10:28 ` MyungJoo Ham
2010-08-20 7:35 ` Kukjin Kim
0 siblings, 1 reply; 26+ messages in thread
From: MyungJoo Ham @ 2010-08-19 10:28 UTC (permalink / raw)
To: Kukjin Kim; +Cc: linux-arm-kernel, linux-samsung-soc, Jongpill Lee, ben-linux
On Thu, Aug 19, 2010 at 7:04 PM, MyungJoo Ham <myungjoo.ham@samsung.com> wrote:
> On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
>> From: Jongpill Lee <boyko.lee@samsung.com>
>>
>> This patch adds video clocks for S5PV310/S5PC210.
>>
>> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
>> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
>> ---
>> arch/arm/mach-s5pv310/clock.c | 74 +++++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 74 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
>> index 14c9707..04bde94 100644
>> --- a/arch/arm/mach-s5pv310/clock.c
>> +++ b/arch/arm/mach-s5pv310/clock.c
>> @@ -506,6 +506,78 @@ static struct clksrc_sources clkset_group = {
>> .nr_sources = ARRAY_SIZE(clkset_group_list),
>> };
>>
>> +static struct clksrc_clk clk_sclk_mipidphy4l = {
>> + .clk = {
>> + .name = "sclk_mipidphy4l",
>> + .id = -1,
>> + .enable = s5pv310_clk_ip_lcd0_ctrl,
>> + .ctrlbit = (1 << 4),
>> + },
>> + .sources = &clkset_group,
>> + .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 12, .size = 4 },
>> + .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 16, .size = 4 },
>> +};
>
> It appears that clk_ip_lcd0[4](CLK_SMMUFIMD0) is not for this clock
> source. This SCLK_MIPIDPHY4L seems to be masked by
> CLK_SRC_MASK_LCD0[12] (MIPI0_MASK)
Um... As CLK_SRC_MASK_LCD0[12] (MIPI0_MASK) controls MUX_MIPI0, it
masks both SCLK_MIPIDPHY4L and SCLK_MIPI0. Then, it seems that we
cannot mask SCLK_MIPIDPHY4L and SCLK_MIPI0 independently.
Then, what about not adding .enable entry for both "sclk_mipidphy4l"
and "sclk_mipi" (which is added in the PATCH 14/14)? Affecting another
clock source with one does not look good.
>
>> +
>> +static struct clksrc_clk clk_sclk_mipidphy2l = {
>> + .clk = {
>> + .name = "sclk_mipidphy2l",
>> + .id = -1,
>> + .enable = s5pv310_clk_ip_lcd1_ctrl,
>> + .ctrlbit = (1 << 4),
>> + },
>> + .sources = &clkset_group,
>> + .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 12, .size = 4 },
>> + .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 16, .size = 4 },
>> +};
>
> Appears to have the similar issue with the previous clock source
Same with above.
>
>> +
>> +static struct clk *clkset_mout_g2d0_list[] = {
>> + [0] = &clk_mout_mpll.clk,
>> + [1] = &clk_sclk_apll.clk,
>> +};
>> +
>> +static struct clksrc_sources clkset_mout_g2d0 = {
>> + .sources = clkset_mout_g2d0_list,
>> + .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
>> +};
>> +
>> +static struct clksrc_clk clk_mout_g2d0 = {
>> + .clk = {
>> + .name = "mout_g2d0",
>> + .id = -1,
>> + },
>> + .sources = &clkset_mout_g2d0,
>> + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
>> +};
>> +
>> +static struct clk *clkset_mout_g2d1_list[] = {
>> + [0] = &clk_mout_epll.clk,
>> + [1] = &clk_sclk_vpll.clk,
>> +};
>> +
>> +static struct clksrc_sources clkset_mout_g2d1 = {
>> + .sources = clkset_mout_g2d1_list,
>> + .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
>> +};
>> +
>> +static struct clksrc_clk clk_mout_g2d1 = {
>> + .clk = {
>> + .name = "mout_g2d1",
>> + .id = -1,
>> + },
>> + .sources = &clkset_mout_g2d1,
>> + .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
>> +};
>> +
>> +static struct clk *clkset_mout_g2d_list[] = {
>> + [0] = &clk_mout_g2d0.clk,
>> + [1] = &clk_mout_g2d1.clk,
>> +};
>> +
>> +static struct clksrc_sources clkset_mout_g2d = {
>> + .sources = clkset_mout_g2d_list,
>> + .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
>> +};
>> +
>> static struct clksrc_clk clk_dout_mmc0 = {
>> .clk = {
>> .name = "dout_mmc0",
>> @@ -672,6 +744,8 @@ static struct clksrc_clk *sysclks[] = {
>> &clk_aclk_100,
>> &clk_aclk_160,
>> &clk_aclk_133,
>> + &clk_sclk_mipidphy4l,
>> + &clk_sclk_mipidphy2l,
>> &clk_dout_mmc0,
>> &clk_dout_mmc1,
>> &clk_dout_mmc2,
>> --
>> 1.6.2.5
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
>
>
> --
> MyungJoo Ham, Ph.D.
> Mobile Software Platform Lab,
> Digital Media and Communications (DMC) Business
> Samsung Electronics
> cell: 82-10-6714-2858
>
--
MyungJoo Ham (함명주), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 13/14] ARM: S5PV310: Add video clocks
2010-08-19 10:28 ` MyungJoo Ham
@ 2010-08-20 7:35 ` Kukjin Kim
0 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-20 7:35 UTC (permalink / raw)
To: 'MyungJoo Ham'
Cc: linux-arm-kernel, linux-samsung-soc, 'Jongpill Lee',
ben-linux
MyungJoo Ham wrote:
>
> On Thu, Aug 19, 2010 at 7:04 PM, MyungJoo Ham
> <myungjoo.ham@samsung.com> wrote:
> > On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com>
> wrote:
> >> From: Jongpill Lee <boyko.lee@samsung.com>
> >>
> >> This patch adds video clocks for S5PV310/S5PC210.
> >>
> >> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
> >> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
> >> ---
> >> arch/arm/mach-s5pv310/clock.c | 74
> +++++++++++++++++++++++++++++++++++++++++
> >> 1 files changed, 74 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
> >> index 14c9707..04bde94 100644
> >> --- a/arch/arm/mach-s5pv310/clock.c
> >> +++ b/arch/arm/mach-s5pv310/clock.c
> >> @@ -506,6 +506,78 @@ static struct clksrc_sources clkset_group = {
> >> .nr_sources = ARRAY_SIZE(clkset_group_list),
> >> };
> >>
> >> +static struct clksrc_clk clk_sclk_mipidphy4l = {
> >> + .clk = {
> >> + .name = "sclk_mipidphy4l",
> >> + .id = -1,
> >> + .enable = s5pv310_clk_ip_lcd0_ctrl,
> >> + .ctrlbit = (1 << 4),
> >> + },
> >> + .sources = &clkset_group,
> >> + .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 12, .size = 4 },
> >> + .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 16, .size = 4 },
> >> +};
> >
> > It appears that clk_ip_lcd0[4](CLK_SMMUFIMD0) is not for this clock
> > source. This SCLK_MIPIDPHY4L seems to be masked by
> > CLK_SRC_MASK_LCD0[12] (MIPI0_MASK)
>
Ok...you're right.
> Um... As CLK_SRC_MASK_LCD0[12] (MIPI0_MASK) controls MUX_MIPI0, it
> masks both SCLK_MIPIDPHY4L and SCLK_MIPI0. Then, it seems that we
> cannot mask SCLK_MIPIDPHY4L and SCLK_MIPI0 independently.
>
> Then, what about not adding .enable entry for both "sclk_mipidphy4l"
> and "sclk_mipi" (which is added in the PATCH 14/14)? Affecting another
> clock source with one does not look good.
>
Hmm...yeah, I agree with you. I will think about that again.
Thank you for your pointing out.
> >
> >> +
> >> +static struct clksrc_clk clk_sclk_mipidphy2l = {
> >> + .clk = {
> >> + .name = "sclk_mipidphy2l",
> >> + .id = -1,
> >> + .enable = s5pv310_clk_ip_lcd1_ctrl,
> >> + .ctrlbit = (1 << 4),
> >> + },
> >> + .sources = &clkset_group,
> >> + .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 12, .size = 4 },
> >> + .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 16, .size = 4 },
> >> +};
> >
> > Appears to have the similar issue with the previous clock source
>
> Same with above.
>
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 14/14] ARM: S5PV310: Adds various special clocks
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (12 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 13/14] ARM: S5PV310: Add video clocks Kukjin Kim
@ 2010-08-18 14:01 ` Kukjin Kim
2010-08-23 2:05 ` [PATCH 00/14] ARM: S5PV310: Updates clock Kyungmin Park
14 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-18 14:01 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc; +Cc: ben-linux, Jongpill Lee, Kukjin Kim
From: Jongpill Lee <boyko.lee@samsung.com>
This patch adds various special clocks for S5PV310/S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
arch/arm/mach-s5pv310/clock.c | 186 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 186 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 04bde94..d8a7697 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -51,6 +51,21 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
}
+static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
@@ -61,6 +76,11 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
+static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -681,6 +701,172 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
}, {
.clk = {
+ .name = "sclk_csis",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 2,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 3,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_mipi",
+ .id = 0,
+ .parent = &clk_sclk_mipidphy4l.clk,
+ .enable = s5pv310_clksrc_mask_lcd0_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_mipi",
+ .id = 1,
+ .parent = &clk_sclk_mipidphy2l.clk,
+ .enable = s5pv310_clksrc_mask_lcd1_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_sata",
+ .id = -1,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_mout_corebus,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_spi",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_spi",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_spi",
+ .id = 2,
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimg2d",
+ .id = -1,
+ },
+ .sources = &clkset_mout_g2d,
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
.name = "sclk_mmc",
.id = 0,
.parent = &clk_dout_mmc0.clk,
--
1.6.2.5
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 00/14] ARM: S5PV310: Updates clock
2010-08-18 14:01 [PATCH 00/14] ARM: S5PV310: Updates clock Kukjin Kim
` (13 preceding siblings ...)
2010-08-18 14:01 ` [PATCH 14/14] ARM: S5PV310: Adds various special clocks Kukjin Kim
@ 2010-08-23 2:05 ` Kyungmin Park
2010-08-23 2:21 ` Kukjin Kim
14 siblings, 1 reply; 26+ messages in thread
From: Kyungmin Park @ 2010-08-23 2:05 UTC (permalink / raw)
To: Kukjin Kim
Cc: linux-arm-kernel, linux-samsung-soc, ben-linux,
Russell King - ARM Linux
Well,
The current V310 clock codes don't work. I wonder these codes are
should be tested by your team. but it's just hang at clock init.
With this patch, it's also don't boot. We also fixed the wrong uart
clock bit. but same. don't works.
Question? Do you can boot with this codes at your board?
Thank you,
Kyungmin Park
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Linux version 2.6.36-rc1-ga400ca7-dirty
(dofmind@dofmind-linux) (gcc version 4.4.1 (GCC) ) #334 PREEMPT Mon
Aug 23 10:45:59 KST 2010
[ 0.000000] CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c53c7f
[ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing
instruction cache
[ 0.000000] Machine: UNIVERSAL_C210
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] CPU S5PV310 (id 0x43200200)
[ 0.000000] S3C24XX Clocks, Copyright 2004 Simtec Electronics
[ 0.000000] s3c_register_clksrc: clock armclk has no registers set
[ 0.000000] S5PV310: PLL settings, A=800000000, M=660000000,
E=96000000 V=108000000
[ 0.000000] S5PV310: ARMCLK=800000000, DMC=330000000, ACLK200=165000000
[ 0.000000] ACLK100=82500000, ACLK160=132000000, ACLK133=110000000
[ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
[ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
[ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
[ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
[ 0.000000] sclk_pwm: source is mout_mpll (6), rate is 73333333
[ 0.000000] sclk_csis: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_csis: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_cam: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_cam: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimd: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimd: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_sata: source is mout_mpll (0), rate is 110000000
[ 0.000000] sclk_spi: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_spi: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_spi: source is ext_xtal (0), rate is 24000000
[ 0.000000] sclk_fimg2d: source is mout_g2d0 (0), rate is 0
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 130048
[ 0.000000] Kernel command line: root=ubi0!rootfs rootfstype=ubifs
rootflags=bulk_read,no_chk_data_crc ubi.mtd=8 ubi.mtd=3 ubi.mtd=6
earlyprintk console=ttySAC2,115200n8 mem=512M mtdparts=samsung-onenan)
[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 512MB = 512MB total
[ 0.000000] Memory: 517040k/517040k available, 7248k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
[ 0.000000] vmalloc : 0xe0800000 - 0xf0000000 ( 248 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
[ 0.000000] .init : 0xc0008000 - 0xc001f000 ( 92 kB)
[ 0.000000] .text : 0xc001f000 - 0xc023b000 (2160 kB)
[ 0.000000] .data : 0xc0250000 - 0xc0271340 ( 133 kB)
[ 0.000000] SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0,
CPUs=1, Nodes=1
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU-based detection of stalled CPUs is disabled.
[ 0.000000] Verbose stalled-CPUs detection is disabled.
[ 0.000000] NR_IRQS:440
[ 0.000000] Console: colour dummy device 80x30
s3c24xx_serial_initconsole
s3c24xx_serial_init_ports: initialising ports...
s3c24xx_serial_init_port: port=c026caa0, platdev=c0271b20
s3c24xx_serial_init_port: c026caa0 (hw 0)...
resource c02564b8 (13800000..13800100)
port: map=13800000, mem=f5000000, irq=16 (16,18), clock=1
s3c24xx_serial_init_port: port=c026cb68, platdev=c0256f08
s3c24xx_serial_init_port: c026cb68 (hw 1)...
resource c0256528 (13810000..13810100)
port: map=13810000, mem=f5010000, irq=20 (20,22), clock=1
s3c24xx_serial_init_port: port=c026cc30, platdev=c0256fe8
s3c24xx_serial_init_port: c026cc30 (hw 2)...
resource c0256598 (13820000..13820100)
port: map=13820000, mem=f5020000, irq=24 (24,26), clock=1
s3c24xx_serial_init_port: port=c026ccf8, platdev=c02570c8
s3c24xx_serial_init_port: c026ccf8 (hw 3)...
resource c0256608 (13830000..13830100)
port: map=13830000, mem=f5030000, irq=28 (28,30), clock=1
s3c24xx_serial_console_setup: co=c026cd9c (2), 115200n8
s3c24xx_serial_console_setup: port=c026cc30 (2)
s3c24xx_serial_console_setup: baud 115200
selecting clock fffffffe
fracval = 0000
config: 8bits/char
On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> This patch updates clock for S5PV310/S5PC210.
>
> [PATCH 01/14] ARM: S5PV310: Adds clock addresses for S5PV310
> [PATCH 02/14] ARM: S5PV310: Removed unused clock
> [PATCH 03/14] ARM: S5PV310: Adds clkset_aclk for removing clkset_aclk_xxx
> [PATCH 04/14] ARM: S5PV310: Fix on PLL setting for S5PV310
> [PATCH 05/14] ARM: S5PV310: Adds clk_sclk_usbphy0, _usbphy1, and _hdmiphy
> [PATCH 06/14] ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll
> [PATCH 07/14] ARM: S5PV310: Adds printing ACLK200, ACLK100, ACLK160 and ACLK133
> [PATCH 08/14] ARM: S5PV310: Adds enable and ctrlbit for clk_vpllsrc
> [PATCH 09/14] ARM: S5PV310: Adds SDMMC clock for S5PV310
> [PATCH 10/14] ARM: S5PV310: Adds uart clocks
> [PATCH 11/14] ARM: S5PV310: Bug fix on uclk1 and sclk_pwm
> [PATCH 12/14] ARM: S5PV310: Add various clocks
> [PATCH 13/14] ARM: S5PV310: Add video clocks
> [PATCH 14/14] ARM: S5PV310: Adds various special clocks
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 00/14] ARM: S5PV310: Updates clock
2010-08-23 2:05 ` [PATCH 00/14] ARM: S5PV310: Updates clock Kyungmin Park
@ 2010-08-23 2:21 ` Kukjin Kim
0 siblings, 0 replies; 26+ messages in thread
From: Kukjin Kim @ 2010-08-23 2:21 UTC (permalink / raw)
To: 'Kyungmin Park'
Cc: linux-arm-kernel, linux-samsung-soc, ben-linux,
'Russell King - ARM Linux'
Kyungmin Park wrote:
>
> Well,
>
> The current V310 clock codes don't work. I wonder these codes are
> should be tested by your team. but it's just hang at clock init.
>
> With this patch, it's also don't boot. We also fixed the wrong uart
> clock bit. but same. don't works.
>
> Question? Do you can boot with this codes at your board?
>
Actually, tested on the board but some codes which don't match common kernel framework such as serial and so on had not been submitted at that time.
...will be submitted soon.
> Thank you,
> Kyungmin Park
>
> Uncompressing Linux... done, booting the kernel.
> [ 0.000000] Linux version 2.6.36-rc1-ga400ca7-dirty
> (dofmind@dofmind-linux) (gcc version 4.4.1 (GCC) ) #334 PREEMPT Mon
> Aug 23 10:45:59 KST 2010
> [ 0.000000] CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7),
> cr=10c53c7f
> [ 0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing
> instruction cache
> [ 0.000000] Machine: UNIVERSAL_C210
> [ 0.000000] bootconsole [earlycon0] enabled
> [ 0.000000] Memory policy: ECC disabled, Data cache writeback
> [ 0.000000] CPU S5PV310 (id 0x43200200)
> [ 0.000000] S3C24XX Clocks, Copyright 2004 Simtec Electronics
> [ 0.000000] s3c_register_clksrc: clock armclk has no registers set
> [ 0.000000] S5PV310: PLL settings, A=800000000, M=660000000,
> E=96000000 V=108000000
> [ 0.000000] S5PV310: ARMCLK=800000000, DMC=330000000,
> ACLK200=165000000
> [ 0.000000] ACLK100=82500000, ACLK160=132000000, ACLK133=110000000
> [ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
> [ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
> [ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
> [ 0.000000] uclk1: source is mout_mpll (6), rate is 82500000
> [ 0.000000] sclk_pwm: source is mout_mpll (6), rate is 73333333
> [ 0.000000] sclk_csis: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_csis: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_cam: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_cam: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimc: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimd: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimd: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_sata: source is mout_mpll (0), rate is 110000000
> [ 0.000000] sclk_spi: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_spi: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_spi: source is ext_xtal (0), rate is 24000000
> [ 0.000000] sclk_fimg2d: source is mout_g2d0 (0), rate is 0
> [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
> Total pages: 130048
> [ 0.000000] Kernel command line: root=ubi0!rootfs rootfstype=ubifs
> rootflags=bulk_read,no_chk_data_crc ubi.mtd=8 ubi.mtd=3 ubi.mtd=6
> earlyprintk console=ttySAC2,115200n8 mem=512M mtdparts=samsung-onenan)
> [ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
> [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [ 0.000000] Memory: 512MB = 512MB total
> [ 0.000000] Memory: 517040k/517040k available, 7248k reserved, 0K highmem
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
> [ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
> [ 0.000000] vmalloc : 0xe0800000 - 0xf0000000 ( 248 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
> [ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
> [ 0.000000] .init : 0xc0008000 - 0xc001f000 ( 92 kB)
> [ 0.000000] .text : 0xc001f000 - 0xc023b000 (2160 kB)
> [ 0.000000] .data : 0xc0250000 - 0xc0271340 ( 133 kB)
> [ 0.000000] SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0,
> CPUs=1, Nodes=1
> [ 0.000000] Hierarchical RCU implementation.
> [ 0.000000] RCU-based detection of stalled CPUs is disabled.
> [ 0.000000] Verbose stalled-CPUs detection is disabled.
> [ 0.000000] NR_IRQS:440
> [ 0.000000] Console: colour dummy device 80x30
> s3c24xx_serial_initconsole
> s3c24xx_serial_init_ports: initialising ports...
> s3c24xx_serial_init_port: port=c026caa0, platdev=c0271b20
> s3c24xx_serial_init_port: c026caa0 (hw 0)...
> resource c02564b8 (13800000..13800100)
> port: map=13800000, mem=f5000000, irq=16 (16,18), clock=1
> s3c24xx_serial_init_port: port=c026cb68, platdev=c0256f08
> s3c24xx_serial_init_port: c026cb68 (hw 1)...
> resource c0256528 (13810000..13810100)
> port: map=13810000, mem=f5010000, irq=20 (20,22), clock=1
> s3c24xx_serial_init_port: port=c026cc30, platdev=c0256fe8
> s3c24xx_serial_init_port: c026cc30 (hw 2)...
> resource c0256598 (13820000..13820100)
> port: map=13820000, mem=f5020000, irq=24 (24,26), clock=1
> s3c24xx_serial_init_port: port=c026ccf8, platdev=c02570c8
> s3c24xx_serial_init_port: c026ccf8 (hw 3)...
> resource c0256608 (13830000..13830100)
> port: map=13830000, mem=f5030000, irq=28 (28,30), clock=1
> s3c24xx_serial_console_setup: co=c026cd9c (2), 115200n8
> s3c24xx_serial_console_setup: port=c026cc30 (2)
> s3c24xx_serial_console_setup: baud 115200
> selecting clock fffffffe
> fracval = 0000
> config: 8bits/char
>
>
> On Wed, Aug 18, 2010 at 11:01 PM, Kukjin Kim <kgene.kim@samsung.com> wrote:
> > This patch updates clock for S5PV310/S5PC210.
> >
> > [PATCH 01/14] ARM: S5PV310: Adds clock addresses for S5PV310
> > [PATCH 02/14] ARM: S5PV310: Removed unused clock
> > [PATCH 03/14] ARM: S5PV310: Adds clkset_aclk for removing clkset_aclk_xxx
> > [PATCH 04/14] ARM: S5PV310: Fix on PLL setting for S5PV310
> > [PATCH 05/14] ARM: S5PV310: Adds clk_sclk_usbphy0, _usbphy1, and
> _hdmiphy
> > [PATCH 06/14] ARM: S5PV310: Should be clk_sclk_apll not clk_mout_apll
> > [PATCH 07/14] ARM: S5PV310: Adds printing ACLK200, ACLK100, ACLK160 and
> ACLK133
> > [PATCH 08/14] ARM: S5PV310: Adds enable and ctrlbit for clk_vpllsrc
> > [PATCH 09/14] ARM: S5PV310: Adds SDMMC clock for S5PV310
> > [PATCH 10/14] ARM: S5PV310: Adds uart clocks
> > [PATCH 11/14] ARM: S5PV310: Bug fix on uclk1 and sclk_pwm
> > [PATCH 12/14] ARM: S5PV310: Add various clocks
> > [PATCH 13/14] ARM: S5PV310: Add video clocks
> > [PATCH 14/14] ARM: S5PV310: Adds various special clocks
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 26+ messages in thread