[PATCH 00/16] Another 16 L2C patches

[PATCH 00/16] Another 16 L2C patches

[Russell King - ARM Linux]

So, in response to Matt Porter's complaint about breaking prima2, here's
another 16 patches which changes the way the L2 cache is initialised on
many platforms.  This series moves towards a situation where the generic
code initialises the L2 cache itself, with as little help as possible
from board specific code.

A number of platforms are left alone because they're more complex -
these should still eventually be converted.

At some point in the near future, I will see about sorting out their
ordering wrt the previous patch set.  For the time being, they apply
on top of the existing l2c changes.

 arch/arm/include/asm/mach/arch.h  |  3 +++
 arch/arm/kernel/irq.c             | 12 ++++++++++++
 arch/arm/mach-bcm/bcm_5301x.c     |  9 ++-------
 arch/arm/mach-berlin/berlin.c     | 17 ++++++-----------
 arch/arm/mach-exynos/exynos.c     |  8 ++------
 arch/arm/mach-highbank/highbank.c |  9 +++------
 arch/arm/mach-imx/mach-vf610.c    |  9 ++-------
 arch/arm/mach-mvebu/board-v7.c    |  9 ++++++---
 arch/arm/mach-nomadik/cpu-8815.c  | 13 +++----------
 arch/arm/mach-prima2/Makefile     |  1 -
 arch/arm/mach-prima2/common.c     |  6 ++++++
 arch/arm/mach-prima2/l2x0.c       | 17 -----------------
 arch/arm/mach-rockchip/rockchip.c |  9 ++-------
 arch/arm/mach-socfpga/socfpga.c   |  9 ++-------
 arch/arm/mach-sti/board-dt.c      | 20 +++++---------------
 arch/arm/mach-tegra/tegra.c       | 12 +++---------
 arch/arm/mach-vexpress/v2m.c      |  3 ++-
 arch/arm/mach-zynq/common.c       |  8 +++-----
 18 files changed, 62 insertions(+), 112 deletions(-)


-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

[PATCH 14/16] ARM: l2c: convert exynos to generic l2c initialisation (and thereby fix it)

[Russell King]

exynos was unconditionally calling the L2 cache initialisation from an
early_initcall.  This breaks multiplatform kernels.  Thankfully,
converting to generic l2c initialisation fixes this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-exynos/exynos.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fbfc29df3299..a763c0862da9 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -316,12 +316,6 @@ static int __init exynos_core_init(void)
 }
 core_initcall(exynos_core_init);
 
-static int __init exynos4_l2x0_cache_init(void)
-{
-	return l2x0_of_init(0x3c400001, 0xc20fffff);
-}
-early_initcall(exynos4_l2x0_cache_init);
-
 static void __init exynos_dt_machine_init(void)
 {
 	struct device_node *i2c_np;
@@ -387,6 +381,8 @@ static void __init exynos_reserve(void)
 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 	/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
 	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+	.l2c_aux_val	= 0x3c400001,
+	.l2c_aux_mask	= 0xc20fffff,
 	.smp		= smp_ops(exynos_smp_ops),
 	.map_io		= exynos_init_io,
 	.init_early	= exynos_firmware_init,
-- 
1.8.3.1

Re: [PATCH 00/16] Another 16 L2C patches

[Stephen Warren]

On 04/28/2014 10:56 AM, Russell King - ARM Linux wrote:
> So, in response to Matt Porter's complaint about breaking prima2, here's
> another 16 patches which changes the way the L2 cache is initialised on
> many platforms.  This series moves towards a situation where the generic
> code initialises the L2 cache itself, with as little help as possible
> from board specific code.
> 
> A number of platforms are left alone because they're more complex -
> these should still eventually be converted.
> 
> At some point in the near future, I will see about sorting out their
> ordering wrt the previous patch set.  For the time being, they apply
> on top of the existing l2c changes.

Are "the existing l2c changes" in next-20140428? If not, is there a git
branch I can pull to test the whole thing, rather than tracking down and
applying "the existing l2c changes" first?

Re: [PATCH 00/16] Another 16 L2C patches

[Stephen Warren]

On 04/28/2014 11:12 AM, Stephen Warren wrote:
> On 04/28/2014 10:56 AM, Russell King - ARM Linux wrote:
>> So, in response to Matt Porter's complaint about breaking prima2, here's
>> another 16 patches which changes the way the L2 cache is initialised on
>> many platforms.  This series moves towards a situation where the generic
>> code initialises the L2 cache itself, with as little help as possible
>> from board specific code.
>>
>> A number of platforms are left alone because they're more complex -
>> these should still eventually be converted.
>>
>> At some point in the near future, I will see about sorting out their
>> ordering wrt the previous patch set.  For the time being, they apply
>> on top of the existing l2c changes.
> 
> Are "the existing l2c changes" in next-20140428? If not, is there a git
> branch I can pull to test the whole thing, rather than tracking down and
> applying "the existing l2c changes" first?

I guess they must be in linux-next, since this series applies cleanly on
top of it.

So, patches 2/16 ("ARM: l2c: add platform independent core L2 cache
initialisation") and 7/16 ("ARM: l2c: convert tegra to generic l2c
initialisation"),

Tested-by: Stephen Warren <swarren@nvidia.com>

(On an NVIDIA Tegra20 Seaboard/Springbank board, on top of next-20140428)

I do see one error in dmesg during boot, but it doesn't appear to
negatively affect operation in brief testing, and is present in
linux-next without this series anyway. Is this message a problem?

> [    0.000000] L2C: platform modifies aux control register: 0x02080000 -> 0x3e480001
> [    0.000000] L2C: DT/platform modifies aux control register: 0x02080000 -> 0x3e480001
> [    0.000000] L2C-310 errata 727915 769419 enabled
> [    0.000000] L2C-310 enabling early BRESP for Cortex-A9
> [    0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
                          ^^^^^^ this is logged at error level
> [    0.000000] L2C-310 ID prefetch enabled, offset 1 lines
> [    0.000000] L2C-310 dynamic clock gating disabled, standby mode disabled
> [    0.000000] L2C-310 cache controller enabled, 8 ways, 1024 kB
> [    0.000000] L2C-310: CACHE_ID 0x410000c4, AUX_CTRL 0x7e480001

Re: [PATCH 00/16] Another 16 L2C patches

[Russell King - ARM Linux]

On Mon, Apr 28, 2014 at 11:27:09AM -0600, Stephen Warren wrote:
> On 04/28/2014 11:12 AM, Stephen Warren wrote:
> > On 04/28/2014 10:56 AM, Russell King - ARM Linux wrote:
> >> So, in response to Matt Porter's complaint about breaking prima2, here's
> >> another 16 patches which changes the way the L2 cache is initialised on
> >> many platforms.  This series moves towards a situation where the generic
> >> code initialises the L2 cache itself, with as little help as possible
> >> from board specific code.
> >>
> >> A number of platforms are left alone because they're more complex -
> >> these should still eventually be converted.
> >>
> >> At some point in the near future, I will see about sorting out their
> >> ordering wrt the previous patch set.  For the time being, they apply
> >> on top of the existing l2c changes.
> > 
> > Are "the existing l2c changes" in next-20140428? If not, is there a git
> > branch I can pull to test the whole thing, rather than tracking down and
> > applying "the existing l2c changes" first?
> 
> I guess they must be in linux-next, since this series applies cleanly on
> top of it.
> 
> So, patches 2/16 ("ARM: l2c: add platform independent core L2 cache
> initialisation") and 7/16 ("ARM: l2c: convert tegra to generic l2c
> initialisation"),
> 
> Tested-by: Stephen Warren <swarren@nvidia.com>
> 
> (On an NVIDIA Tegra20 Seaboard/Springbank board, on top of next-20140428)
> 
> I do see one error in dmesg during boot, but it doesn't appear to
> negatively affect operation in brief testing, and is present in
> linux-next without this series anyway. Is this message a problem?
> 
> > [    0.000000] L2C: platform modifies aux control register: 0x02080000 -> 0x3e480001
> > [    0.000000] L2C: DT/platform modifies aux control register: 0x02080000 -> 0x3e480001
> > [    0.000000] L2C-310 errata 727915 769419 enabled
> > [    0.000000] L2C-310 enabling early BRESP for Cortex-A9
> > [    0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
>                           ^^^^^^ this is logged at error level

Correct, it's an error because on Tegra you explicitly set bit 0 in the
auxiliary control register, which is pointless unless the feature is
also enabled in the Cortex-A9 control register as well.

Rather than trying to track down everyone who does this, and then end
up in a long discussion about it, I'm just going to make the kernel
print an error message as a result, it's just wrong to set random bits
in device control registers without first properly understanding what
they're doing.

-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

Re: [PATCH 00/16] Another 16 L2C patches

[Heiko Stübner]

Am Montag, 28. April 2014, 17:56:31 schrieb Russell King - ARM Linux:
> So, in response to Matt Porter's complaint about breaking prima2, here's
> another 16 patches which changes the way the L2 cache is initialised on
> many platforms.  This series moves towards a situation where the generic
> code initialises the L2 cache itself, with as little help as possible
> from board specific code.

Patches 2/16 ("ARM: l2c: add platform independent core L2 cache
initialisation") and 3/16 ("ARM: l2c:  convert rockchip to generic l2c 
initialisation") applied on a linux-next from 20140428,

Tested-by: Heiko Stuebner <heiko@sntech.de>