[PATCH 1/3] drm/exynos: don't commit if plane scaling is required

[PATCH 1/3] drm/exynos: don't commit if plane scaling is required

[Gustavo Padovan]

From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>

exynos doesn't show scaled planes properly on the screen so
disable the feature and show a message to the user.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
---
 drivers/gpu/drm/exynos/exynos_mixer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 2e3bc57..a95fe84 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -550,6 +550,12 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
 		fmt = ARGB8888;
 	}
 
+	if (win_data->crtc_width != win_data->src_width ||
+	    win_data->crtc_height != win_data->src_height) {
+		DRM_DEBUG_KMS("plane scaling not supported\n");
+		return;
+	}
+
 	/* 2x scaling feature */
 	x_ratio = 0;
 	y_ratio = 0;
-- 
2.1.0

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[PATCH 2/3] drm/exynos: reset temporary value after write to register

[Gustavo Padovan]

From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>

'val' wasn't clean after its last usage, so we could get garbage value and
send the wrong command to the hw.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
---
 drivers/gpu/drm/exynos/exynos_mixer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index a95fe84..7aff88f 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -687,7 +687,7 @@ static void mixer_win_reset(struct mixer_context *ctx)
 	mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
 
 	/* Blend layer 1 into layer 0 */
-	val |= MXR_GRP_CFG_BLEND_PRE_MUL;
+	val = MXR_GRP_CFG_BLEND_PRE_MUL;
 	val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
 	mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
 
-- 
2.1.0

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Re: [PATCH 2/3] drm/exynos: reset temporary value after write to register

[Joonyoung Shim]

Hi Gustavo,

On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> 
> 'val' wasn't clean after its last usage, so we could get garbage value and
> send the wrong command to the hw.
> 
> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> ---
>  drivers/gpu/drm/exynos/exynos_mixer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index a95fe84..7aff88f 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -687,7 +687,7 @@ static void mixer_win_reset(struct mixer_context *ctx)
>  	mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
>  
>  	/* Blend layer 1 into layer 0 */
> -	val |= MXR_GRP_CFG_BLEND_PRE_MUL;

I know this is not wrong, current code means layer 1 needs above
register setting value of layer 0 as default.

Thanks.

> +	val = MXR_GRP_CFG_BLEND_PRE_MUL;
>  	val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
>  	mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
>  
> 

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[PATCH 3/3] drm/exynos: enable/disable blend based on pixel format

[Gustavo Padovan]

From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>

Change the switch to use the pixel_format instead of bpp to figure out
if we need to enable or disable the layer blending.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
---
 drivers/gpu/drm/exynos/exynos_mixer.c | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 7aff88f..0c54098 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -529,7 +529,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
 	unsigned int x_ratio, y_ratio;
 	unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
 	dma_addr_t dma_addr;
-	unsigned int fmt;
+	unsigned int fmt, blend;
 	u32 val;
 
 	win_data = &ctx->win_data[win];
@@ -539,15 +539,26 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
 	#define ARGB4444 6
 	#define ARGB8888 7
 
-	switch (win_data->bpp) {
-	case 16:
+	switch (win_data->pixel_format) {
+	case DRM_FORMAT_ARGB4444:
 		fmt = ARGB4444;
+		blend = 1;
 		break;
-	case 32:
+
+	case DRM_FORMAT_ARGB8888:
+		fmt = ARGB8888;
+		blend = 1;
+		break;
+
+	case DRM_FORMAT_XRGB8888:
 		fmt = ARGB8888;
+		blend = 0;
 		break;
+
 	default:
 		fmt = ARGB8888;
+		blend = 0;
+		break;
 	}
 
 	if (win_data->crtc_width != win_data->src_width ||
@@ -586,6 +597,16 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
 	mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
 			win_data->fb_pitch / (win_data->bpp >> 3));
 
+	if (blend) {
+		val = MXR_GRP_CFG_BLEND_PRE_MUL;
+		val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
+	} else {
+		val = 0;
+	}
+	mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), val,
+			    MXR_GRP_CFG_BLEND_PRE_MUL
+			    | MXR_GRP_CFG_PIXEL_BLEND_EN);
+
 	/* setup display size */
 	if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
 		win == MIXER_DEFAULT_WIN) {
-- 
2.1.0

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Re: [PATCH 3/3] drm/exynos: enable/disable blend based on pixel format

[Joonyoung Shim]

Hi Gustavo,

On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> 
> Change the switch to use the pixel_format instead of bpp to figure out
> if we need to enable or disable the layer blending.
> 

The default concept is ok about enable or disable of pixel blending
feature by pixel_format, but it will make to possible blending with
background layer. I'm not sure whether it's proper or not.

Thanks.

> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> ---
>  drivers/gpu/drm/exynos/exynos_mixer.c | 29 +++++++++++++++++++++++++----
>  1 file changed, 25 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 7aff88f..0c54098 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -529,7 +529,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
>  	unsigned int x_ratio, y_ratio;
>  	unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
>  	dma_addr_t dma_addr;
> -	unsigned int fmt;
> +	unsigned int fmt, blend;
>  	u32 val;
>  
>  	win_data = &ctx->win_data[win];
> @@ -539,15 +539,26 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
>  	#define ARGB4444 6
>  	#define ARGB8888 7
>  
> -	switch (win_data->bpp) {
> -	case 16:
> +	switch (win_data->pixel_format) {
> +	case DRM_FORMAT_ARGB4444:
>  		fmt = ARGB4444;
> +		blend = 1;
>  		break;
> -	case 32:
> +
> +	case DRM_FORMAT_ARGB8888:
> +		fmt = ARGB8888;
> +		blend = 1;
> +		break;
> +
> +	case DRM_FORMAT_XRGB8888:
>  		fmt = ARGB8888;
> +		blend = 0;
>  		break;
> +
>  	default:
>  		fmt = ARGB8888;
> +		blend = 0;
> +		break;
>  	}
>  
>  	if (win_data->crtc_width != win_data->src_width ||
> @@ -586,6 +597,16 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
>  	mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
>  			win_data->fb_pitch / (win_data->bpp >> 3));
>  
> +	if (blend) {
> +		val = MXR_GRP_CFG_BLEND_PRE_MUL;
> +		val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
> +	} else {
> +		val = 0;
> +	}
> +	mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), val,
> +			    MXR_GRP_CFG_BLEND_PRE_MUL
> +			    | MXR_GRP_CFG_PIXEL_BLEND_EN);
> +
>  	/* setup display size */
>  	if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
>  		win == MIXER_DEFAULT_WIN) {
> 

Re: Fw: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on pixel format

[Tobias Jakobi]

Hello Joonyoung,

> Gesendet: Freitag, 17. April 2015 um 08:16 Uhr
> Von: "Joonyoung Shim" <jy0922.shim@samsung.com>
> An: "Gustavo Padovan" <gustavo@padovan.org>, 
> linux-samsung-soc@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, "Gustavo
> Padovan" <gustavo.padovan@collabora.co.uk>
> Betreff: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on 
> pixel format
> Hi Gustavo,
> 
> On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
>> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
>> 
>> Change the switch to use the pixel_format instead of bpp to figure out
>> if we need to enable or disable the layer blending.
>> 
> 
> The default concept is ok about enable or disable of pixel blending
> feature by pixel_format, but it will make to possible blending with
> background layer. I'm not sure whether it's proper or not.
Wouldn't this be solved by only allowing non-alpha formats for the 
primary plane, or am I confusing the plane ordering?


With best wishes,
Tobias



> 
> Thanks.
> 
>> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
>> ---
>> drivers/gpu/drm/exynos/exynos_mixer.c | 29 
>> +++++++++++++++++++++++++----
>> 1 file changed, 25 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c 
>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>> index 7aff88f..0c54098 100644
>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>> @@ -529,7 +529,7 @@ static void mixer_graph_buffer(struct 
>> mixer_context *ctx, int win)
>> unsigned int x_ratio, y_ratio;
>> unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
>> dma_addr_t dma_addr;
>> - unsigned int fmt;
>> + unsigned int fmt, blend;
>> u32 val;
>> 
>> win_data = &ctx->win_data[win];
>> @@ -539,15 +539,26 @@ static void mixer_graph_buffer(struct 
>> mixer_context *ctx, int win)
>> #define ARGB4444 6
>> #define ARGB8888 7
>> 
>> - switch (win_data->bpp) {
>> - case 16:
>> + switch (win_data->pixel_format) {
>> + case DRM_FORMAT_ARGB4444:
>> fmt = ARGB4444;
>> + blend = 1;
>> break;
>> - case 32:
>> +
>> + case DRM_FORMAT_ARGB8888:
>> + fmt = ARGB8888;
>> + blend = 1;
>> + break;
>> +
>> + case DRM_FORMAT_XRGB8888:
>> fmt = ARGB8888;
>> + blend = 0;
>> break;
>> +
>> default:
>> fmt = ARGB8888;
>> + blend = 0;
>> + break;
>> }
>> 
>> if (win_data->crtc_width != win_data->src_width ||
>> @@ -586,6 +597,16 @@ static void mixer_graph_buffer(struct 
>> mixer_context *ctx, int win)
>> mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
>> win_data->fb_pitch / (win_data->bpp >> 3));
>> 
>> + if (blend) {
>> + val = MXR_GRP_CFG_BLEND_PRE_MUL;
>> + val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
>> + } else {
>> + val = 0;
>> + }
>> + mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), val,
>> + MXR_GRP_CFG_BLEND_PRE_MUL
>> + | MXR_GRP_CFG_PIXEL_BLEND_EN);
>> +
>> /* setup display size */
>> if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
>> win == MIXER_DEFAULT_WIN) {
>> 
> 
> --
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> linux-samsung-soc" in
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Re: Fw: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on pixel format

[Tobias Jakobi]

Hello Joonyoung,

I thought about this some more.


> Gesendet: Freitag, 17. April 2015 um 08:16 Uhr
> Von: "Joonyoung Shim" <jy0922.shim@samsung.com>
> An: "Gustavo Padovan" <gustavo@padovan.org>, 
> linux-samsung-soc@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, "Gustavo
> Padovan" <gustavo.padovan@collabora.co.uk>
> Betreff: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on 
> pixel format
> Hi Gustavo,
> 
> On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
>> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
>> 
>> Change the switch to use the pixel_format instead of bpp to figure out
>> if we need to enable or disable the layer blending.
>> 
> 
> The default concept is ok about enable or disable of pixel blending
> feature by pixel_format, but it will make to possible blending with
> background layer. I'm not sure whether it's proper or not.
I think one of the reasons why this is currently causing confusion is 
because the background layer is not exposed to userspace. So an idea 
would be to expose BG as a normal DRM plane, with a background_rgb 
propery.

Then we just need to keep track which planes are enabled.

E.g. if just the primary plane is enabled, then we ignore any alpha 
pixelformat (in the sense that we map it to its non-alpha counterpart). 
If another plane, which is located 'underneath', is enabled, then we 
honor the alpha. This could then be the background plane.


With best wishes,
Tobias



> 
> Thanks.
> 
>> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
>> ---
>> drivers/gpu/drm/exynos/exynos_mixer.c | 29 
>> +++++++++++++++++++++++++----
>> 1 file changed, 25 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c 
>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>> index 7aff88f..0c54098 100644
>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>> @@ -529,7 +529,7 @@ static void mixer_graph_buffer(struct 
>> mixer_context *ctx, int win)
>> unsigned int x_ratio, y_ratio;
>> unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
>> dma_addr_t dma_addr;
>> - unsigned int fmt;
>> + unsigned int fmt, blend;
>> u32 val;
>> 
>> win_data = &ctx->win_data[win];
>> @@ -539,15 +539,26 @@ static void mixer_graph_buffer(struct 
>> mixer_context *ctx, int win)
>> #define ARGB4444 6
>> #define ARGB8888 7
>> 
>> - switch (win_data->bpp) {
>> - case 16:
>> + switch (win_data->pixel_format) {
>> + case DRM_FORMAT_ARGB4444:
>> fmt = ARGB4444;
>> + blend = 1;
>> break;
>> - case 32:
>> +
>> + case DRM_FORMAT_ARGB8888:
>> + fmt = ARGB8888;
>> + blend = 1;
>> + break;
>> +
>> + case DRM_FORMAT_XRGB8888:
>> fmt = ARGB8888;
>> + blend = 0;
>> break;
>> +
>> default:
>> fmt = ARGB8888;
>> + blend = 0;
>> + break;
>> }
>> 
>> if (win_data->crtc_width != win_data->src_width ||
>> @@ -586,6 +597,16 @@ static void mixer_graph_buffer(struct 
>> mixer_context *ctx, int win)
>> mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
>> win_data->fb_pitch / (win_data->bpp >> 3));
>> 
>> + if (blend) {
>> + val = MXR_GRP_CFG_BLEND_PRE_MUL;
>> + val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
>> + } else {
>> + val = 0;
>> + }
>> + mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), val,
>> + MXR_GRP_CFG_BLEND_PRE_MUL
>> + | MXR_GRP_CFG_PIXEL_BLEND_EN);
>> +
>> /* setup display size */
>> if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
>> win == MIXER_DEFAULT_WIN) {
>> 
> 
> --
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> linux-samsung-soc" in
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Re: Fw: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on pixel format

[Ville Syrjälä]

On Fri, Apr 17, 2015 at 02:55:57PM +0200, Tobias Jakobi wrote:
> Hello Joonyoung,
> 
> I thought about this some more.
> 
> 
> > Gesendet: Freitag, 17. April 2015 um 08:16 Uhr
> > Von: "Joonyoung Shim" <jy0922.shim@samsung.com>
> > An: "Gustavo Padovan" <gustavo@padovan.org>, 
> > linux-samsung-soc@vger.kernel.org
> > Cc: dri-devel@lists.freedesktop.org, inki.dae@samsung.com, "Gustavo
> > Padovan" <gustavo.padovan@collabora.co.uk>
> > Betreff: Re: [PATCH 3/3] drm/exynos: enable/disable blend based on 
> > pixel format
> > Hi Gustavo,
> > 
> > On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
> >> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> >> 
> >> Change the switch to use the pixel_format instead of bpp to figure out
> >> if we need to enable or disable the layer blending.
> >> 
> > 
> > The default concept is ok about enable or disable of pixel blending
> > feature by pixel_format, but it will make to possible blending with
> > background layer. I'm not sure whether it's proper or not.
> I think one of the reasons why this is currently causing confusion is 
> because the background layer is not exposed to userspace. So an idea 
> would be to expose BG as a normal DRM plane, with a background_rgb 
> propery.

Is it just a color? The plan is to expose that simply as a crtc
property. There have been some patches floating around for intel.
Not sure if those were cc:d to dri-devel properly.

> 
> Then we just need to keep track which planes are enabled.
> 
> E.g. if just the primary plane is enabled, then we ignore any alpha 
> pixelformat (in the sense that we map it to its non-alpha counterpart). 
> If another plane, which is located 'underneath', is enabled, then we 
> honor the alpha. This could then be the background plane.
> 
> 
> With best wishes,
> Tobias
> 
> 
> 
> > 
> > Thanks.
> > 
> >> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> >> ---
> >> drivers/gpu/drm/exynos/exynos_mixer.c | 29 
> >> +++++++++++++++++++++++++----
> >> 1 file changed, 25 insertions(+), 4 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c 
> >> b/drivers/gpu/drm/exynos/exynos_mixer.c
> >> index 7aff88f..0c54098 100644
> >> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> >> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> >> @@ -529,7 +529,7 @@ static void mixer_graph_buffer(struct 
> >> mixer_context *ctx, int win)
> >> unsigned int x_ratio, y_ratio;
> >> unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
> >> dma_addr_t dma_addr;
> >> - unsigned int fmt;
> >> + unsigned int fmt, blend;
> >> u32 val;
> >> 
> >> win_data = &ctx->win_data[win];
> >> @@ -539,15 +539,26 @@ static void mixer_graph_buffer(struct 
> >> mixer_context *ctx, int win)
> >> #define ARGB4444 6
> >> #define ARGB8888 7
> >> 
> >> - switch (win_data->bpp) {
> >> - case 16:
> >> + switch (win_data->pixel_format) {
> >> + case DRM_FORMAT_ARGB4444:
> >> fmt = ARGB4444;
> >> + blend = 1;
> >> break;
> >> - case 32:
> >> +
> >> + case DRM_FORMAT_ARGB8888:
> >> + fmt = ARGB8888;
> >> + blend = 1;
> >> + break;
> >> +
> >> + case DRM_FORMAT_XRGB8888:
> >> fmt = ARGB8888;
> >> + blend = 0;
> >> break;
> >> +
> >> default:
> >> fmt = ARGB8888;
> >> + blend = 0;
> >> + break;
> >> }
> >> 
> >> if (win_data->crtc_width != win_data->src_width ||
> >> @@ -586,6 +597,16 @@ static void mixer_graph_buffer(struct 
> >> mixer_context *ctx, int win)
> >> mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
> >> win_data->fb_pitch / (win_data->bpp >> 3));
> >> 
> >> + if (blend) {
> >> + val = MXR_GRP_CFG_BLEND_PRE_MUL;
> >> + val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
> >> + } else {
> >> + val = 0;
> >> + }
> >> + mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), val,
> >> + MXR_GRP_CFG_BLEND_PRE_MUL
> >> + | MXR_GRP_CFG_PIXEL_BLEND_EN);
> >> +
> >> /* setup display size */
> >> if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
> >> win == MIXER_DEFAULT_WIN) {
> >> 
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe 
> > linux-samsung-soc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/3] drm/exynos: don't commit if plane scaling is required

[Tobias Jakobi]

Hello Gustavo,

Gustavo Padovan wrote:
> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> 
> exynos doesn't show scaled planes properly on the screen so
> disable the feature and show a message to the user.
do you know if this is a hardware limitation/issue?

With best wishes,
Tobias

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Re: [PATCH 1/3] drm/exynos: don't commit if plane scaling is required

[Tobias Jakobi]

Hello,

I've just send an alternate version of this patch, which at least
exposes the 2x scaling feature (which is already alluded to in the code):
https://patchwork.kernel.org/patch/6095901/

@Gustavo: What do you think?

With best wishes,
Tobias


Gustavo Padovan wrote:
> From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> 
> exynos doesn't show scaled planes properly on the screen so
> disable the feature and show a message to the user.
> 
> Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
> ---
>  drivers/gpu/drm/exynos/exynos_mixer.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 2e3bc57..a95fe84 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -550,6 +550,12 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win)
>  		fmt = ARGB8888;
>  	}
>  
> +	if (win_data->crtc_width != win_data->src_width ||
> +	    win_data->crtc_height != win_data->src_height) {
> +		DRM_DEBUG_KMS("plane scaling not supported\n");
> +		return;
> +	}
> +
>  	/* 2x scaling feature */
>  	x_ratio = 0;
>  	y_ratio = 0;
>