Re: I/O write ordering

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Thu, 2004-09-23 at 01:22, James Bottomley wrote:
> On Wed, 2004-09-22 at 11:11, Benjamin Herrenschmidt wrote:
> > Set by the CPU as non-cacheable.
> 
> I know that ... but that definition is architecture specific and not
> helpful.
> 
> I mean when for I/O transactions does the CPU mark memory as
> uncacheable.  Is it for the PCI spaces only or for consistent PCI memory
> as well?  We need to ascertain in generic I/O terms exactly what it is
> that you want synchronising.

Ok, so as far as we are concerned, synchronization issue is between cacheable
vs. non-cacheable as mapped by the CPU MMU. (synchronisation between various
accesses of the same kind is already correctly handled either by the existing
barriers for cacheable space or by the MMIO accessors themselves).

This includes:

 - MMIO space is always non-cacheable (wether it is PCI or other sorts
of IOs)

 - consistent memory is either cacheable or non-cacheable depending on
the CPU type (some embedded CPUs who don't implement cache coherency
will map consistent memory as non-cacheable, most desktop CPUs and all
64 bits CPU don't mind and will map it cacheable).

Ben.