[PATCH v3 00/17] introduce exynosauto v9 ufs driver

[PATCH v3 00/17] introduce exynosauto v9 ufs driver

[Chanho Park]

In ExynosAuto(variant of the Exynos for automotive), the UFS Storage needs
to be accessed from multi-OS. To increase IO performance and reduce SW
complexity, we implemented UFS-IOV to support storage IO virtualization
feature on UFS.

IO virtualization increases IO performance and reduce SW complexity
with small area cost. And IO virtualization supports virtual machine
isolation for Security and Safety which are requested by Multi-OS system
such as automotive application.

Below figure is the conception of UFS-IOV architeture.

    +------+          +------+
    | OS#1 |          | OS#2 |
    +------+          +------+
       |                 |
 +------------+     +------------+
 |  Physical  |     |   Virtual  |
 |    Host    |     |    Host    |
 +------------+     +------------+
   |      |              | <-- UTP_CMD_SAP, UTP_TM_SAP
   |   +-------------------------+
   |   |    Function Arbitor     |
   |   +-------------------------+
 +-------------------------------+
 |           UTP Layer           |
 +-------------------------------+
 +-------------------------------+
 |           UIC Layer           |
 +-------------------------------+

There are two types of host controllers on the UFS host controller
that we designed.
The UFS device has a Function Arbitor that arranges commands of each host.
When each host transmits a command to the Arbitor, the Arbitor transmits it
to the UTP layer.
Physical Host(PH) support all UFSHCI functions(all SAPs) same as
conventional UFSHCI.
Virtual Host(VH) support only data transfer function(UTP_CMD_SAP and
UTP_TM_SAP).

In an environment where multiple OSs are used, the OS that has the
leadership of the system is called System OS(Dom0). This system OS uses
PH and controls error handling.

Since VH can only use less functions than PH, it is necessary to send a
request to PH for Detected Error Handling in VH. To interface among PH
and VHs, UFSHCI HW supports mailbox. PH can broadcast mail to other VH at
the same time with arguments and VH can mail to PH with arguments.
PH and VH generate interrupts when mails from PH or VH.

In this structure, the virtual host can't support some feature and need
to skip the some part of ufshcd code by using quirk.
This patchs add quirks so that the UIC command is ignored and the ufshcd
init process can be skipped for VH. Also, according to our UFS-IOV policy,

First two patches, I picked them up from Jonmin's patchset[1] and the third
patch has been dropped because we need to check it again.

[1]: https://lore.kernel.org/linux-scsi/20210527030901.88403-1-jjmin.jeong@samsung.com/

Patch 0003 ~ 0013, they are changes of exynos7 ufs driver to apply
exynosauto v9 variant and PH/VH capabilities.
Patch 0014 ~ 0017, the patches introduce exynosauto v9 ufs MHCI which
includes PH and VH.

Changes from v2:
- Separate dt-binding patches on top of
  https://lore.kernel.org/linux-devicetree/YUNdqnZ2kYefxFUC@robh.at.kernel.org/

Changes from v1:
- Change quirk name from UFSHCD_QUIRK_SKIP_INTERFACE_CONFIGURATION to
  UFSHCD_QUIRK_SKIP_PH_CONFIGURATION
- Add compatibles to Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
  on top of https://lore.kernel.org/linux-scsi/20200613024706.27975-9-alim.akhtar@samsung.com/

Chanho Park (15):
  scsi: ufs: ufs-exynos: change pclk available max value
  scsi: ufs: ufs-exynos: simplify drv_data retrieval
  dt-bindings: ufs: exynos-ufs: add sysreg regmap property
  scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency
  scsi: ufs: ufs-exynos: add refclkout_stop control
  scsi: ufs: ufs-exynos: add setup_clocks callback
  scsi: ufs: ufs-exynos: correct timeout value setting registers
  scsi: ufs: ufs-exynos: support custom version of ufs_hba_variant_ops
  scsi: ufs: ufs-exynos: add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option
  scsi: ufs: ufs-exynos: factor out priv data init
  scsi: ufs: ufs-exynos: add pre/post_hce_enable drv callbacks
  scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver
  scsi: ufs: ufs-exynos: multi-host configuration for exynosauto
  scsi: ufs: ufs-exynos: introduce exynosauto v9 virtual host
  dt-bindings: ufs: exynos-ufs: add exynosautov9 compatible

jongmin jeong (2):
  scsi: ufs: add quirk to handle broken UIC command
  scsi: ufs: add quirk to enable host controller without ph
    configuration

 .../bindings/ufs/samsung,exynos-ufs.yaml      |   7 +
 drivers/scsi/ufs/ufs-exynos.c                 | 318 ++++++++++++++++--
 drivers/scsi/ufs/ufs-exynos.h                 |  10 +-
 drivers/scsi/ufs/ufshcd.c                     |   6 +
 drivers/scsi/ufs/ufshcd.h                     |  12 +
 5 files changed, 327 insertions(+), 26 deletions(-)

-- 
2.33.0

[PATCH v3 01/17] scsi: ufs: add quirk to handle broken UIC command

[Chanho Park]

From: jongmin jeong <jjmin.jeong@samsung.com>

samsung ExynosAuto9 SoC has two types of host controller interface to
support the virtualization of UFS Device.
One is the physical host(PH) that the same as conventaional UFSHCI,
and the other is the virtual host(VH) that support data transfer function
only.

In this structure, the virtual host does not support UIC command.
To support this, we add the quirk and return 0 when the UIC command
send function is called.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: James E.J. Bottomley <jejb@linux.ibm.com>
Cc: Martin K. Petersen <martin.petersen@oracle.com>
Cc: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufshcd.c | 3 +++
 drivers/scsi/ufs/ufshcd.h | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3841ab49f556..8a45e8c05965 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -2324,6 +2324,9 @@ int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
 	int ret;
 	unsigned long flags;
 
+	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
+		return 0;
+
 	ufshcd_hold(hba, false);
 	mutex_lock(&hba->uic_cmd_mutex);
 	ufshcd_add_delay_before_dme_cmd(hba);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 52ea6f350b18..e1d8fd432614 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -588,6 +588,12 @@ enum ufshcd_quirks {
 	 * This quirk allows only sg entries aligned with page size.
 	 */
 	UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE		= 1 << 14,
+
+	/*
+	 * This quirk needs to be enabled if the host controller does not
+	 * support UIC command
+	 */
+	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
 };
 
 enum ufshcd_caps {
-- 
2.33.0

RE: [PATCH v3 01/17] scsi: ufs: add quirk to handle broken UIC command

[Alim Akhtar]

Hi Chanho 

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:24 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; jongmin jeong
><jjmin.jeong@samsung.com>; Chanho Park <chanho61.park@samsung.com>
>Subject: [PATCH v3 01/17] scsi: ufs: add quirk to handle broken UIC command
>
>From: jongmin jeong <jjmin.jeong@samsung.com>
>
>samsung ExynosAuto9 SoC has two types of host controller interface to support
>the virtualization of UFS Device.
>One is the physical host(PH) that the same as conventaional UFSHCI, and the
>other is the virtual host(VH) that support data transfer function only.
>
>In this structure, the virtual host does not support UIC command.
>To support this, we add the quirk and return 0 when the UIC command send
>function is called.
>
>Cc: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: James E.J. Bottomley <jejb@linux.ibm.com>
>Cc: Martin K. Petersen <martin.petersen@oracle.com>
>Cc: Bart Van Assche <bvanassche@acm.org>
>Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> drivers/scsi/ufs/ufshcd.c | 3 +++
> drivers/scsi/ufs/ufshcd.h | 6 ++++++
> 2 files changed, 9 insertions(+)
>
>diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index
>3841ab49f556..8a45e8c05965 100644
>--- a/drivers/scsi/ufs/ufshcd.c
>+++ b/drivers/scsi/ufs/ufshcd.c
>@@ -2324,6 +2324,9 @@ int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct
>uic_command *uic_cmd)
> 	int ret;
> 	unsigned long flags;
>
>+	if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
>+		return 0;
>+
> 	ufshcd_hold(hba, false);
> 	mutex_lock(&hba->uic_cmd_mutex);
> 	ufshcd_add_delay_before_dme_cmd(hba);
>diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index
>52ea6f350b18..e1d8fd432614 100644
>--- a/drivers/scsi/ufs/ufshcd.h
>+++ b/drivers/scsi/ufs/ufshcd.h
>@@ -588,6 +588,12 @@ enum ufshcd_quirks {
> 	 * This quirk allows only sg entries aligned with page size.
> 	 */
> 	UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE		= 1 << 14,
>+
>+	/*
>+	 * This quirk needs to be enabled if the host controller does not
>+	 * support UIC command
>+	 */
>+	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
> };
>
> enum ufshcd_caps {
>--
>2.33.0

[PATCH v3 02/17] scsi: ufs: add quirk to enable host controller without ph configuration

[Chanho Park]

From: jongmin jeong <jjmin.jeong@samsung.com>

samsung ExynosAuto SoC has two types of host controller interface to
support the virtualization of UFS Device.
One is the physical host(PH) that the same as conventaional UFSHCI,
and the other is the virtual host(VH) that support data transfer function only.

In this structure, the virtual host does not support like device management.
This patch skips the physical host interface configuration part that cannot
be performed in the virtual host.

Suggested-by: Alim Akhtar <alim.akhtar@samsung.com>
Cc: James E.J. Bottomley <jejb@linux.ibm.com>
Cc: Martin K. Petersen <martin.petersen@oracle.com>
Cc: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufshcd.c | 3 +++
 drivers/scsi/ufs/ufshcd.h | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 8a45e8c05965..628ef8e17531 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -8066,6 +8066,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
 	if (ret)
 		goto out;
 
+	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
+		goto out;
+
 	/* Debug counters initialization */
 	ufshcd_clear_dbg_ufs_stats(hba);
 
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index e1d8fd432614..e547fbd19d49 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -594,6 +594,12 @@ enum ufshcd_quirks {
 	 * support UIC command
 	 */
 	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
+
+	/*
+	 * This quirk needs to be enabled if the host controller cannot
+	 * support physical host configuration.
+	 */
+	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
 };
 
 enum ufshcd_caps {
-- 
2.33.0

RE: [PATCH v3 02/17] scsi: ufs: add quirk to enable host controller without ph configuration

[Alim Akhtar]

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:24 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; jongmin jeong
><jjmin.jeong@samsung.com>; Chanho Park <chanho61.park@samsung.com>
>Subject: [PATCH v3 02/17] scsi: ufs: add quirk to enable host controller without ph
>configuration
>
>From: jongmin jeong <jjmin.jeong@samsung.com>
>
>samsung ExynosAuto SoC has two types of host controller interface to support
>the virtualization of UFS Device.
>One is the physical host(PH) that the same as conventaional UFSHCI, and the
>other is the virtual host(VH) that support data transfer function only.
>
>In this structure, the virtual host does not support like device management.
>This patch skips the physical host interface configuration part that cannot be
>performed in the virtual host.
>
>Suggested-by: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: James E.J. Bottomley <jejb@linux.ibm.com>
>Cc: Martin K. Petersen <martin.petersen@oracle.com>
>Cc: Bart Van Assche <bvanassche@acm.org>
>Signed-off-by: jongmin jeong <jjmin.jeong@samsung.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> drivers/scsi/ufs/ufshcd.c | 3 +++
> drivers/scsi/ufs/ufshcd.h | 6 ++++++
> 2 files changed, 9 insertions(+)
>
>diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index
>8a45e8c05965..628ef8e17531 100644
>--- a/drivers/scsi/ufs/ufshcd.c
>+++ b/drivers/scsi/ufs/ufshcd.c
>@@ -8066,6 +8066,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool
>init_dev_params)
> 	if (ret)
> 		goto out;
>
>+	if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
>+		goto out;
>+
> 	/* Debug counters initialization */
> 	ufshcd_clear_dbg_ufs_stats(hba);
>
>diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index
>e1d8fd432614..e547fbd19d49 100644
>--- a/drivers/scsi/ufs/ufshcd.h
>+++ b/drivers/scsi/ufs/ufshcd.h
>@@ -594,6 +594,12 @@ enum ufshcd_quirks {
> 	 * support UIC command
> 	 */
> 	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
>+
>+	/*
>+	 * This quirk needs to be enabled if the host controller cannot
>+	 * support physical host configuration.
>+	 */
>+	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
> };
>
> enum ufshcd_caps {
>--
>2.33.0

[PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

[Chanho Park]

To support 167MHz PCLK, we need to adjust the maximum value.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index dadf4fd10dd8..0a31f77a5f48 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -99,7 +99,7 @@ struct exynos_ufs;
 #define PA_HIBERN8TIME_VAL	0x20
 
 #define PCLK_AVAIL_MIN	70000000
-#define PCLK_AVAIL_MAX	133000000
+#define PCLK_AVAIL_MAX	167000000
 
 struct exynos_ufs_uic_attr {
 	/* TX Attributes */
-- 
2.33.0

Re: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

[Inki Dae]

Hi Chanho,

21. 9. 17. 오후 3:54에 Chanho Park 이(가) 쓴 글:
> To support 167MHz PCLK, we need to adjust the maximum value.
> 
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  drivers/scsi/ufs/ufs-exynos.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
> index dadf4fd10dd8..0a31f77a5f48 100644
> --- a/drivers/scsi/ufs/ufs-exynos.h
> +++ b/drivers/scsi/ufs/ufs-exynos.h
> @@ -99,7 +99,7 @@ struct exynos_ufs;
>  #define PA_HIBERN8TIME_VAL	0x20
>  
>  #define PCLK_AVAIL_MIN	70000000
> -#define PCLK_AVAIL_MAX	133000000
> +#define PCLK_AVAIL_MAX	167000000
>  

I'm not sure but doesn't the maximum clock frequency depend on a given machine? Is it true for all machines using different SoC?

Thanks,
Inki Dae

>  struct exynos_ufs_uic_attr {
>  	/* TX Attributes */
> 

RE: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

[Chanho Park]

> >  #define PCLK_AVAIL_MIN	70000000
> > -#define PCLK_AVAIL_MAX	133000000
> > +#define PCLK_AVAIL_MAX	167000000
> >
> 
> I'm not sure but doesn't the maximum clock frequency depend on a given
> machine? Is it true for all machines using different SoC?

Regarding pclk(sclk_unipro)of the ufs, it can be defined by mux(MUX_CLK_FSYS2_UFS_EMBD).
It can be either 167MHz or 160MHz. And it can be defined by OSCCLK(26MHz) as well. The value was up to 133Mhz in case of exynos7 but can be extended up to 167MHz for later SoCs, AFAIK.

Best Regards,
Chanho Park

Re: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

[Inki Dae]

21. 9. 27. 오후 3:46에 Chanho Park 이(가) 쓴 글:
>>>  #define PCLK_AVAIL_MIN	70000000
>>> -#define PCLK_AVAIL_MAX	133000000
>>> +#define PCLK_AVAIL_MAX	167000000
>>>
>>
>> I'm not sure but doesn't the maximum clock frequency depend on a given
>> machine? Is it true for all machines using different SoC?
> 
> Regarding pclk(sclk_unipro)of the ufs, it can be defined by mux(MUX_CLK_FSYS2_UFS_EMBD).
> It can be either 167MHz or 160MHz. And it can be defined by OSCCLK(26MHz) as well. The value was up to 133Mhz in case of exynos7 but can be extended up to 167MHz for later SoCs, AFAIK.

Oscillator clock frequency could be different according to machine. And what if UFS driver is enabled for other machine using Exynos7? Is it true to use a fixed 167MHz frequency for these machines?
I think you could get a proper pclk frequency from device tree specific to machine.

Thanks,
Inki Dae

> 
> Best Regards,
> Chanho Park
> 
> 

RE: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

[Chanho Park]

> >>>  #define PCLK_AVAIL_MIN	70000000
> >>> -#define PCLK_AVAIL_MAX	133000000
> >>> +#define PCLK_AVAIL_MAX	167000000
> >>>
> >>
> >> I'm not sure but doesn't the maximum clock frequency depend on a
> >> given machine? Is it true for all machines using different SoC?
> >
> > Regarding pclk(sclk_unipro)of the ufs, it can be defined by
> mux(MUX_CLK_FSYS2_UFS_EMBD).
> > It can be either 167MHz or 160MHz. And it can be defined by OSCCLK(26MHz)
> as well. The value was up to 133Mhz in case of exynos7 but can be extended
> up to 167MHz for later SoCs, AFAIK.
> 
> Oscillator clock frequency could be different according to machine. And
> what if UFS driver is enabled for other machine using Exynos7? Is it true
> to use a fixed 167MHz frequency for these machines?
> I think you could get a proper pclk frequency from device tree specific to
> machine.

The actual pclk value will be get by CCF's clk_get_rate. PCLK_AVAIL_MAX represents the available maximum value of UFS's pclk to find an optimal value of unipro clock. I just extend the maximum pclk rate from 133MHz to 167MHz. The divider will be calculated according to the actual pclk value :)

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/ufs/ufs-exynos.c?h=v5.15-rc3#n287

Best Regards,
Chanho Park

Re: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

[Inki Dae]

21. 9. 27. 오후 8:08에 Chanho Park 이(가) 쓴 글:
>>>>>  #define PCLK_AVAIL_MIN	70000000
>>>>> -#define PCLK_AVAIL_MAX	133000000
>>>>> +#define PCLK_AVAIL_MAX	167000000
>>>>>
>>>>
>>>> I'm not sure but doesn't the maximum clock frequency depend on a
>>>> given machine? Is it true for all machines using different SoC?
>>>
>>> Regarding pclk(sclk_unipro)of the ufs, it can be defined by
>> mux(MUX_CLK_FSYS2_UFS_EMBD).
>>> It can be either 167MHz or 160MHz. And it can be defined by OSCCLK(26MHz)
>> as well. The value was up to 133Mhz in case of exynos7 but can be extended
>> up to 167MHz for later SoCs, AFAIK.
>>
>> Oscillator clock frequency could be different according to machine. And
>> what if UFS driver is enabled for other machine using Exynos7? Is it true
>> to use a fixed 167MHz frequency for these machines?
>> I think you could get a proper pclk frequency from device tree specific to
>> machine.
> 
> The actual pclk value will be get by CCF's clk_get_rate. PCLK_AVAIL_MAX represents the available maximum value of UFS's pclk to find an optimal value of unipro clock. I just extend the maximum pclk rate from 133MHz to 167MHz. The divider will be calculated according to the actual pclk value :)
>
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/ufs/ufs-exynos.c?h=v5.15-rc3#n287
>
Thanks for the link. I thought only PCLK_AVAIL_MAX is valid but it means available maximum clock so clock frequency between the min and max would be allowed as well. :)

Reviewed-by : Inki Dae <inki.dae@samsung.com>

Thanks,
Inki Dae

> Best Regards,
> Chanho Park
> 
> 

[PATCH v3 04/17] scsi: ufs: ufs-exynos: simplify drv_data retrieval

[Chanho Park]

The compatible field of exynos_ufs_drv_data is not necessary because
of_device_id already has it. Thus, we don't need it anymore and we can
get drv_data by device_get_match_data.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 10 +---------
 drivers/scsi/ufs/ufs-exynos.h |  3 +--
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index a14dd8ce56d4..8a17ba32a721 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -893,17 +893,10 @@ static int exynos_ufs_post_link(struct ufs_hba *hba)
 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
 {
 	struct device_node *np = dev->of_node;
-	struct exynos_ufs_drv_data *drv_data = &exynos_ufs_drvs;
 	struct exynos_ufs_uic_attr *attr;
 	int ret = 0;
 
-	while (drv_data->compatible) {
-		if (of_device_is_compatible(np, drv_data->compatible)) {
-			ufs->drv_data = drv_data;
-			break;
-		}
-		drv_data++;
-	}
+	ufs->drv_data = device_get_match_data(dev);
 
 	if (ufs->drv_data && ufs->drv_data->uic_attr) {
 		attr = ufs->drv_data->uic_attr;
@@ -1258,7 +1251,6 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
 };
 
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
-	.compatible		= "samsung,exynos7-ufs",
 	.uic_attr		= &exynos7_uic_attr,
 	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
 				  UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 0a31f77a5f48..2e72aabaa673 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -142,7 +142,6 @@ struct exynos_ufs_uic_attr {
 };
 
 struct exynos_ufs_drv_data {
-	char *compatible;
 	struct exynos_ufs_uic_attr *uic_attr;
 	unsigned int quirks;
 	unsigned int opts;
@@ -191,7 +190,7 @@ struct exynos_ufs {
 	struct ufs_pa_layer_attr dev_req_params;
 	struct ufs_phy_time_cfg t_cfg;
 	ktime_t entry_hibern8_t;
-	struct exynos_ufs_drv_data *drv_data;
+	const struct exynos_ufs_drv_data *drv_data;
 
 	u32 opts;
 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
-- 
2.33.0

[PATCH v3 05/17] dt-bindings: ufs: exynos-ufs: add sysreg regmap property

[Chanho Park]

Add "sysreg" regmap phandle property to control io coherency setting.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml          | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index b9ca8ef4f2be..c3f14f81d4b7 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -54,6 +54,11 @@ properties:
   phy-names:
     const: ufs-phy
 
+  sysreg:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description: phandle for FSYS sysreg interface, used to control
+                 sysreg register bit for UFS IO Coherency
+
 required:
   - compatible
   - reg
-- 
2.33.0

Re: [PATCH v3 05/17] dt-bindings: ufs: exynos-ufs: add sysreg regmap property

[Rob Herring]

On Fri, Sep 17, 2021 at 03:54:24PM +0900, Chanho Park wrote:
> Add "sysreg" regmap phandle property to control io coherency setting.
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml          | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> index b9ca8ef4f2be..c3f14f81d4b7 100644
> --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> @@ -54,6 +54,11 @@ properties:
>    phy-names:
>      const: ufs-phy
>  
> +  sysreg:

Needs a vendor prefix.

> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +    description: phandle for FSYS sysreg interface, used to control
> +                 sysreg register bit for UFS IO Coherency

Is there more than 1 FSYS? If not, you can just get the node by its 
compatible. 

Also, what about 'dma-coherent' property? The driver core needs to know.

> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.33.0
> 
> 

RE: [PATCH v3 05/17] dt-bindings: ufs: exynos-ufs: add sysreg regmap property

[Chanho Park]

> > +  sysreg:
> 
> Needs a vendor prefix.

Thanks. I'll use "samsung,sysreg-phandle".

> 
> > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > +    description: phandle for FSYS sysreg interface, used to control
> > +                 sysreg register bit for UFS IO Coherency
> 
> Is there more than 1 FSYS? If not, you can just get the node by its
> compatible.

The phandle can be differed each exynos SoCs, AFAIK. I think other exynos
SoCs since exnos7 will need this but not upstreamed yet...

> 
> Also, what about 'dma-coherent' property? The driver core needs to know.

Yes. 'dma-coherent' should be listed as well.

Best Regards,
Chanho Park

Re: [PATCH v3 05/17] dt-bindings: ufs: exynos-ufs: add sysreg regmap property

[Rob Herring]

On Thu, Sep 23, 2021 at 09:47:44AM +0900, Chanho Park wrote:
> > > +  sysreg:
> > 
> > Needs a vendor prefix.
> 
> Thanks. I'll use "samsung,sysreg-phandle".

No '-phandle'.

> 
> > 
> > > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > > +    description: phandle for FSYS sysreg interface, used to control
> > > +                 sysreg register bit for UFS IO Coherency
> > 
> > Is there more than 1 FSYS? If not, you can just get the node by its
> > compatible.
> 
> The phandle can be differed each exynos SoCs, AFAIK. I think other exynos
> SoCs since exnos7 will need this but not upstreamed yet...

That's still fine. You really only need a phandle if there is more than 
1 instance on a given platform.

Of course you could end up with multiple compatible strings to deal 
with, but you might need that anyway as the registers are likely to be 
different. That can sometimes be mitigated by putting register offsets 
into the DT property (something to consider here).  This is the problem 
with drivers directly twiddling bits in  other h/w blocks and why we 
have common interfaces for clocks, resets, etc.

I leave it to you to decide how you want to do it.

BTW, If you want to see another way to handle the same problem, see 
highbank_platform_notifier(). Notifiers aren't great either, but it 
keeps some SoC specifics out of the driver.

Rob

RE: [PATCH v3 05/17] dt-bindings: ufs: exynos-ufs: add sysreg regmap property

[Chanho Park]

> > > > +  sysreg:
> > >
> > > Needs a vendor prefix.
> >
> > Thanks. I'll use "samsung,sysreg-phandle".
> 
> No '-phandle'.

Will use "samsung,sysreg" next patch series.

> 
> >
> > >
> > > > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > > > +    description: phandle for FSYS sysreg interface, used to control
> > > > +                 sysreg register bit for UFS IO Coherency
> > >
> > > Is there more than 1 FSYS? If not, you can just get the node by its
> > > compatible.
> >
> > The phandle can be differed each exynos SoCs, AFAIK. I think other
> > exynos SoCs since exnos7 will need this but not upstreamed yet...
> 
> That's still fine. You really only need a phandle if there is more than
> 1 instance on a given platform.
> 
> Of course you could end up with multiple compatible strings to deal with,
> but you might need that anyway as the registers are likely to be
different.
> That can sometimes be mitigated by putting register offsets into the DT
> property (something to consider here).  This is the problem with drivers
> directly twiddling bits in  other h/w blocks and why we have common
> interfaces for clocks, resets, etc.

Regarding ufs-exynos, it can have multiple instances (ufs_0/1/22). I'm also
preparing to support ufs_1 for exynosautov9 SoC but not yet finished due to
ufs phy control. Each instances has their own sysreg offset. To support
secondary ufs, I need to rework this patch and add the offset field as DT
propery.

+#define UFS_SHAREABILITY_OFFSET        0x710

For UFS1, this should be 0x714.

> 
> I leave it to you to decide how you want to do it.
> 
> BTW, If you want to see another way to handle the same problem, see
> highbank_platform_notifier(). Notifiers aren't great either, but it keeps
> some SoC specifics out of the driver.
> 

I checked highbank_platform_notifier() implementation but I need to keep
this way to have further support multiple ufs instances and can be used for
exynos8/9 SoCs as well.

Best Regards,
Chanho Park

[PATCH v3 06/17] scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency

[Chanho Park]

UFS_EMBD sharability register of fsys block provides "sharability"
setting of ufs-exynos. It can be set via syscon and regmap.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 5 +++++
 drivers/scsi/ufs/ufs-exynos.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 8a17ba32a721..f7a1b99c823b 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 
@@ -906,6 +907,10 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
 		goto out;
 	}
 
+	ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "sysreg");
+	if (IS_ERR(ufs->sysreg))
+		ufs->sysreg = NULL;
+
 	ufs->pclk_avail_min = PCLK_AVAIL_MIN;
 	ufs->pclk_avail_max = PCLK_AVAIL_MAX;
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 2e72aabaa673..4f93db893ce8 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -191,6 +191,7 @@ struct exynos_ufs {
 	struct ufs_phy_time_cfg t_cfg;
 	ktime_t entry_hibern8_t;
 	const struct exynos_ufs_drv_data *drv_data;
+	struct regmap *sysreg;
 
 	u32 opts;
 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
-- 
2.33.0

Re: [PATCH v3 06/17] scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency

[Rob Herring]

On Fri, Sep 17, 2021 at 03:54:25PM +0900, Chanho Park wrote:
> UFS_EMBD sharability register of fsys block provides "sharability"
> setting of ufs-exynos. It can be set via syscon and regmap.
> 
> Cc: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: Kiwoong Kim <kwmad.kim@samsung.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  drivers/scsi/ufs/ufs-exynos.c | 5 +++++
>  drivers/scsi/ufs/ufs-exynos.h | 1 +
>  2 files changed, 6 insertions(+)

This patch is a nop... Fold it into the patch using sysreg.

> 
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
> index 8a17ba32a721..f7a1b99c823b 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -12,6 +12,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
> +#include <linux/mfd/syscon.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  
> @@ -906,6 +907,10 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
>  		goto out;
>  	}
>  
> +	ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "sysreg");
> +	if (IS_ERR(ufs->sysreg))
> +		ufs->sysreg = NULL;
> +
>  	ufs->pclk_avail_min = PCLK_AVAIL_MIN;
>  	ufs->pclk_avail_max = PCLK_AVAIL_MAX;
>  
> diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
> index 2e72aabaa673..4f93db893ce8 100644
> --- a/drivers/scsi/ufs/ufs-exynos.h
> +++ b/drivers/scsi/ufs/ufs-exynos.h
> @@ -191,6 +191,7 @@ struct exynos_ufs {
>  	struct ufs_phy_time_cfg t_cfg;
>  	ktime_t entry_hibern8_t;
>  	const struct exynos_ufs_drv_data *drv_data;
> +	struct regmap *sysreg;
>  
>  	u32 opts;
>  #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
> -- 
> 2.33.0
> 
> 

RE: [PATCH v3 06/17] scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency

[Chanho Park]

> >  drivers/scsi/ufs/ufs-exynos.c | 5 +++++
> > drivers/scsi/ufs/ufs-exynos.h | 1 +
> >  2 files changed, 6 insertions(+)
> 
> This patch is a nop... Fold it into the patch using sysreg.

I separated them to be reviewed easily by different maintainers. I'll squash
them on next patchset.

Best Regards,
Chanho Park

Re: [PATCH v3 06/17] scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency

[Rob Herring]

On Thu, Sep 23, 2021 at 09:39:46AM +0900, Chanho Park wrote:
> > >  drivers/scsi/ufs/ufs-exynos.c | 5 +++++
> > > drivers/scsi/ufs/ufs-exynos.h | 1 +
> > >  2 files changed, 6 insertions(+)
> > 
> > This patch is a nop... Fold it into the patch using sysreg.
> 
> I separated them to be reviewed easily by different maintainers. I'll squash
> them on next patchset.

Patch 14 is what this should be merged with. How is that a different 
maintainer?

Rob

RE: [PATCH v3 06/17] scsi: ufs: ufs-exynos: get sysreg regmap for io-coherency

[Chanho Park]

> > > This patch is a nop... Fold it into the patch using sysreg.
> >
> > I separated them to be reviewed easily by different maintainers. I'll
> > squash them on next patchset.
> 
> Patch 14 is what this should be merged with. How is that a different
> maintainer?

Ah, Okay. I got your point. I'd like to split them for getting some reviews
from previous ufs-exynos driver owner before adding exynosautov9 ufs driver.

0006-scsi-ufs-ufs-exynos-get-sysreg-regmap-for-io-coheren.patch
0014-scsi-ufs-ufs-exynos-support-exynosauto-v9-ufs-driver.patch

I think both patches can be squashed as you suggested.

Best Regards,
Chanho Park

[PATCH v3 07/17] scsi: ufs: ufs-exynos: add refclkout_stop control

[Chanho Park]

This patch adds REFCLKOUT_STOP control to CLK_STOP_MASK. It can
en/disable reference clock out control for UFS device.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index f7a1b99c823b..627edef4fbeb 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -49,10 +49,11 @@
 #define HCI_ERR_EN_T_LAYER	0x84
 #define HCI_ERR_EN_DME_LAYER	0x88
 #define HCI_CLKSTOP_CTRL	0xB0
+#define REFCLKOUT_STOP		BIT(4)
 #define REFCLK_STOP		BIT(2)
 #define UNIPRO_MCLK_STOP	BIT(1)
 #define UNIPRO_PCLK_STOP	BIT(0)
-#define CLK_STOP_MASK		(REFCLK_STOP |\
+#define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\
 				 UNIPRO_MCLK_STOP |\
 				 UNIPRO_PCLK_STOP)
 #define HCI_MISC		0xB4
-- 
2.33.0

[PATCH v3 08/17] scsi: ufs: ufs-exynos: add setup_clocks callback

[Chanho Park]

This patch adds setup_clocks callback to control/gate clocks by ufshcd.
To avoid calling before initialization, it needs to check whether ufs is
null or not and call it initially from pre_link callback.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 627edef4fbeb..2024e44a09d7 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -795,6 +795,27 @@ static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
 	}
 }
 
+static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
+				   enum ufs_notify_change_status status)
+{
+	struct exynos_ufs *ufs = ufshcd_get_variant(hba);
+
+	if (!ufs)
+		return 0;
+
+	if (on) {
+		if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
+			exynos_ufs_disable_auto_ctrl_hcc(ufs);
+		exynos_ufs_ungate_clks(ufs);
+	} else {
+		exynos_ufs_gate_clks(ufs);
+		if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
+			exynos_ufs_enable_auto_ctrl_hcc(ufs);
+	}
+
+	return 0;
+}
+
 static int exynos_ufs_pre_link(struct ufs_hba *hba)
 {
 	struct exynos_ufs *ufs = ufshcd_get_variant(hba);
@@ -813,6 +834,8 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
 	exynos_ufs_config_phy_time_attr(ufs);
 	exynos_ufs_config_phy_cap_attr(ufs);
 
+	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);
+
 	if (ufs->drv_data->pre_link)
 		ufs->drv_data->pre_link(ufs);
 
@@ -1203,6 +1226,7 @@ static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
 	.hce_enable_notify		= exynos_ufs_hce_enable_notify,
 	.link_startup_notify		= exynos_ufs_link_startup_notify,
 	.pwr_change_notify		= exynos_ufs_pwr_change_notify,
+	.setup_clocks			= exynos_ufs_setup_clocks,
 	.setup_xfer_req			= exynos_ufs_specify_nexus_t_xfer_req,
 	.setup_task_mgmt		= exynos_ufs_specify_nexus_t_tm_req,
 	.hibern8_notify			= exynos_ufs_hibern8_notify,
-- 
2.33.0

RE: [PATCH v3 08/17] scsi: ufs: ufs-exynos: add setup_clocks callback

[Alim Akhtar]

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:24 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
><chanho61.park@samsung.com>; Kiwoong Kim <kwmad.kim@samsung.com>
>Subject: [PATCH v3 08/17] scsi: ufs: ufs-exynos: add setup_clocks callback
>
>This patch adds setup_clocks callback to control/gate clocks by ufshcd.
>To avoid calling before initialization, it needs to check whether ufs is null or not
>and call it initially from pre_link callback.
>
>Cc: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: Kiwoong Kim <kwmad.kim@samsung.com>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
> drivers/scsi/ufs/ufs-exynos.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>627edef4fbeb..2024e44a09d7 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -795,6 +795,27 @@ static void exynos_ufs_config_intr(struct exynos_ufs
>*ufs, u32 errs, u8 index)
> 	}
> }
>
>+static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
>+				   enum ufs_notify_change_status status) {
>+	struct exynos_ufs *ufs = ufshcd_get_variant(hba);
>+
>+	if (!ufs)
>+		return 0;
>+
>+	if (on) {
>+		if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
>+			exynos_ufs_disable_auto_ctrl_hcc(ufs);
>+		exynos_ufs_ungate_clks(ufs);
>+	} else {
>+		exynos_ufs_gate_clks(ufs);
>+		if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
>+			exynos_ufs_enable_auto_ctrl_hcc(ufs);
>+	}
>+
>+	return 0;
>+}
>+
> static int exynos_ufs_pre_link(struct ufs_hba *hba)  {
> 	struct exynos_ufs *ufs = ufshcd_get_variant(hba); @@ -813,6 +834,8
>@@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
> 	exynos_ufs_config_phy_time_attr(ufs);
> 	exynos_ufs_config_phy_cap_attr(ufs);
>
>+	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);

For consistency and better understanding, may be PRE_CHANGE?

>+
> 	if (ufs->drv_data->pre_link)
> 		ufs->drv_data->pre_link(ufs);
>
>@@ -1203,6 +1226,7 @@ static struct ufs_hba_variant_ops ufs_hba_exynos_ops
>= {
> 	.hce_enable_notify		= exynos_ufs_hce_enable_notify,
> 	.link_startup_notify		= exynos_ufs_link_startup_notify,
> 	.pwr_change_notify		= exynos_ufs_pwr_change_notify,
>+	.setup_clocks			= exynos_ufs_setup_clocks,
> 	.setup_xfer_req			=
>exynos_ufs_specify_nexus_t_xfer_req,
> 	.setup_task_mgmt		= exynos_ufs_specify_nexus_t_tm_req,
> 	.hibern8_notify			= exynos_ufs_hibern8_notify,
>--
>2.33.0

[PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value setting registers

[Chanho Park]

PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL
PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL
PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 2024e44a09d7..e32f7d09db1a 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -644,9 +644,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
 	}
 
 	/* setting for three timeout values for traffic class #0 */
-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064);
-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 28224);
-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 20160);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
 
 	return 0;
 out:
-- 
2.33.0

RE: [PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value setting registers

[Alim Akhtar]

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:24 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
><chanho61.park@samsung.com>; Kiwoong Kim <kwmad.kim@samsung.com>
>Subject: [PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value setting
>registers
>
>PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL
>PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL
>PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL
>
>Cc: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: Kiwoong Kim <kwmad.kim@samsung.com>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
Please add a [Fixes] tag with the original commit which introduce this

With the above fix, feel free to add

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> drivers/scsi/ufs/ufs-exynos.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>2024e44a09d7..e32f7d09db1a 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -644,9 +644,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba
>*hba,
> 	}
>
> 	/* setting for three timeout values for traffic class #0 */
>-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064);
>-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
>28224);
>-	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
>20160);
>+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
>+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL),
>28224);
>+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
>
> 	return 0;
> out:
>--
>2.33.0

RE: [PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value setting registers

[Chanho Park]

> >Subject: [PATCH v3 09/17] scsi: ufs: ufs-exynos: correct timeout value
> >setting registers
> >
> >PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL
> >PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL
> >PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL
> >
> >Cc: Alim Akhtar <alim.akhtar@samsung.com>
> >Cc: Kiwoong Kim <kwmad.kim@samsung.com>
> >Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> >Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> >---
> Please add a [Fixes] tag with the original commit which introduce this

I'll add below "Fixes" tag.

Fixes: a967ddb22d94 ("scsi: ufs: ufs-exynos: Apply vendor-specific values for three timeouts")

> 
> With the above fix, feel free to add
> 
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

Thanks for your review :)

Best Regards,
Chanho Park

[PATCH v3 10/17] scsi: ufs: ufs-exynos: support custom version of ufs_hba_variant_ops

[Chanho Park]

By default, ufs_hba_exynos_ops will be used but this patch supports to
use custom version of ufs_hba_variant_ops because some variants of
exynos-ufs will use only few callbacks.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 8 +++++++-
 drivers/scsi/ufs/ufs-exynos.h | 1 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index e32f7d09db1a..a3160d9bd234 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -1238,8 +1238,14 @@ static int exynos_ufs_probe(struct platform_device *pdev)
 {
 	int err;
 	struct device *dev = &pdev->dev;
+	const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
+	const struct exynos_ufs_drv_data *drv_data =
+		device_get_match_data(dev);
 
-	err = ufshcd_pltfrm_init(pdev, &ufs_hba_exynos_ops);
+	if (drv_data && drv_data->vops)
+		vops = drv_data->vops;
+
+	err = ufshcd_pltfrm_init(pdev, vops);
 	if (err)
 		dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 4f93db893ce8..bc4b8b0324bd 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -142,6 +142,7 @@ struct exynos_ufs_uic_attr {
 };
 
 struct exynos_ufs_drv_data {
+	const struct ufs_hba_variant_ops *vops;
 	struct exynos_ufs_uic_attr *uic_attr;
 	unsigned int quirks;
 	unsigned int opts;
-- 
2.33.0

RE: [PATCH v3 10/17] scsi: ufs: ufs-exynos: support custom version of ufs_hba_variant_ops

[Alim Akhtar]

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:24 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
><chanho61.park@samsung.com>; Kiwoong Kim <kwmad.kim@samsung.com>
>Subject: [PATCH v3 10/17] scsi: ufs: ufs-exynos: support custom version of
>ufs_hba_variant_ops
>
>By default, ufs_hba_exynos_ops will be used but this patch supports to use
>custom version of ufs_hba_variant_ops because some variants of exynos-ufs will
>use only few callbacks.
>
>Cc: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: Kiwoong Kim <kwmad.kim@samsung.com>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> drivers/scsi/ufs/ufs-exynos.c | 8 +++++++-  drivers/scsi/ufs/ufs-exynos.h | 1 +
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>e32f7d09db1a..a3160d9bd234 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -1238,8 +1238,14 @@ static int exynos_ufs_probe(struct platform_device
>*pdev)  {
> 	int err;
> 	struct device *dev = &pdev->dev;
>+	const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
>+	const struct exynos_ufs_drv_data *drv_data =
>+		device_get_match_data(dev);
>
>-	err = ufshcd_pltfrm_init(pdev, &ufs_hba_exynos_ops);
>+	if (drv_data && drv_data->vops)
>+		vops = drv_data->vops;
>+
>+	err = ufshcd_pltfrm_init(pdev, vops);
> 	if (err)
> 		dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index
>4f93db893ce8..bc4b8b0324bd 100644
>--- a/drivers/scsi/ufs/ufs-exynos.h
>+++ b/drivers/scsi/ufs/ufs-exynos.h
>@@ -142,6 +142,7 @@ struct exynos_ufs_uic_attr {  };
>
> struct exynos_ufs_drv_data {
>+	const struct ufs_hba_variant_ops *vops;
> 	struct exynos_ufs_uic_attr *uic_attr;
> 	unsigned int quirks;
> 	unsigned int opts;
>--
>2.33.0

[PATCH v3 11/17] scsi: ufs: ufs-exynos: add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option

[Chanho Park]

To skip exynos_ufs_config_phy_*_attr settings for exynos-ufs variant,
this patch provides EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR as an opts
flag.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 6 ++++--
 drivers/scsi/ufs/ufs-exynos.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index a3160d9bd234..73833c186ca9 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -831,8 +831,10 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
 
 	/* m-phy */
 	exynos_ufs_phy_init(ufs);
-	exynos_ufs_config_phy_time_attr(ufs);
-	exynos_ufs_config_phy_cap_attr(ufs);
+	if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
+		exynos_ufs_config_phy_time_attr(ufs);
+		exynos_ufs_config_phy_cap_attr(ufs);
+	}
 
 	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index bc4b8b0324bd..a0899aaa902e 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -200,6 +200,7 @@ struct exynos_ufs {
 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
+#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR	BIT(5)
 };
 
 #define for_each_ufs_rx_lane(ufs, i) \
-- 
2.33.0

RE: [PATCH v3 11/17] scsi: ufs: ufs-exynos: add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option

[Alim Akhtar]

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:25 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
><chanho61.park@samsung.com>; Kiwoong Kim <kwmad.kim@samsung.com>
>Subject: [PATCH v3 11/17] scsi: ufs: ufs-exynos: add
>EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option
>
>To skip exynos_ufs_config_phy_*_attr settings for exynos-ufs variant, this patch
>provides EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR as an opts flag.
>
Please add a bit more information on why this has to be skipped for this HCI.

Thanks

>Cc: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: Kiwoong Kim <kwmad.kim@samsung.com>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---
> drivers/scsi/ufs/ufs-exynos.c | 6 ++++--  drivers/scsi/ufs/ufs-exynos.h | 1 +
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>a3160d9bd234..73833c186ca9 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -831,8 +831,10 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
>
> 	/* m-phy */
> 	exynos_ufs_phy_init(ufs);
>-	exynos_ufs_config_phy_time_attr(ufs);
>-	exynos_ufs_config_phy_cap_attr(ufs);
>+	if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
>+		exynos_ufs_config_phy_time_attr(ufs);
>+		exynos_ufs_config_phy_cap_attr(ufs);
>+	}
>
> 	exynos_ufs_setup_clocks(hba, true, POST_CHANGE);
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index
>bc4b8b0324bd..a0899aaa902e 100644
>--- a/drivers/scsi/ufs/ufs-exynos.h
>+++ b/drivers/scsi/ufs/ufs-exynos.h
>@@ -200,6 +200,7 @@ struct exynos_ufs {
> #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL	BIT(2)
> #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX	BIT(3)
> #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER	BIT(4)
>+#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR	BIT(5)
> };
>
> #define for_each_ufs_rx_lane(ufs, i) \
>--
>2.33.0

[PATCH v3 12/17] scsi: ufs: ufs-exynos: factor out priv data init

[Chanho Park]

To be used this assignment code for other variant exynos-ufs driver,
this patch factors out the codes as inline code.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 73833c186ca9..753b22358186 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -951,6 +951,18 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
 	return ret;
 }
 
+static inline void exynos_ufs_priv_init(struct ufs_hba *hba,
+					struct exynos_ufs *ufs)
+{
+	ufs->hba = hba;
+	ufs->opts = ufs->drv_data->opts;
+	ufs->rx_sel_idx = PA_MAXDATALANES;
+	if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
+		ufs->rx_sel_idx = 0;
+	hba->priv = (void *)ufs;
+	hba->quirks = ufs->drv_data->quirks;
+}
+
 static int exynos_ufs_init(struct ufs_hba *hba)
 {
 	struct device *dev = hba->dev;
@@ -1000,13 +1012,8 @@ static int exynos_ufs_init(struct ufs_hba *hba)
 	if (ret)
 		goto phy_off;
 
-	ufs->hba = hba;
-	ufs->opts = ufs->drv_data->opts;
-	ufs->rx_sel_idx = PA_MAXDATALANES;
-	if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
-		ufs->rx_sel_idx = 0;
-	hba->priv = (void *)ufs;
-	hba->quirks = ufs->drv_data->quirks;
+	exynos_ufs_priv_init(hba, ufs);
+
 	if (ufs->drv_data->drv_init) {
 		ret = ufs->drv_data->drv_init(dev, ufs);
 		if (ret) {
-- 
2.33.0

[PATCH v3 13/17] scsi: ufs: ufs-exynos: add pre/post_hce_enable drv callbacks

[Chanho Park]

This patch adds driver-specific pre/post_hce_enable callbacks to execute
extra initializations before and after hce_enable_notify callback.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 10 ++++++++++
 drivers/scsi/ufs/ufs-exynos.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 753b22358186..7fb4514f700d 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -1141,6 +1141,12 @@ static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
 
 	switch (status) {
 	case PRE_CHANGE:
+		if (ufs->drv_data->pre_hce_enable) {
+			ret = ufs->drv_data->pre_hce_enable(ufs);
+			if (ret)
+				return ret;
+		}
+
 		ret = exynos_ufs_host_reset(hba);
 		if (ret)
 			return ret;
@@ -1150,6 +1156,10 @@ static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
 		exynos_ufs_calc_pwm_clk_div(ufs);
 		if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
 			exynos_ufs_enable_auto_ctrl_hcc(ufs);
+
+		if (ufs->drv_data->post_hce_enable)
+			ret = ufs->drv_data->post_hce_enable(ufs);
+
 		break;
 	}
 
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index a0899aaa902e..c291ae51dd41 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -154,6 +154,8 @@ struct exynos_ufs_drv_data {
 				struct ufs_pa_layer_attr *pwr);
 	int (*post_pwr_change)(struct exynos_ufs *ufs,
 				struct ufs_pa_layer_attr *pwr);
+	int (*pre_hce_enable)(struct exynos_ufs *ufs);
+	int (*post_hce_enable)(struct exynos_ufs *ufs);
 };
 
 struct ufs_phy_time_cfg {
-- 
2.33.0

RE: [PATCH v3 13/17] scsi: ufs: ufs-exynos: add pre/post_hce_enable drv callbacks

[Alim Akhtar]

Hi Chanho

>-----Original Message-----
>From: Chanho Park [mailto:chanho61.park@samsung.com]
>Sent: Friday, September 17, 2021 12:25 PM
>To: Alim Akhtar <alim.akhtar@samsung.com>; Avri Altman
><avri.altman@wdc.com>; James E . J . Bottomley <jejb@linux.ibm.com>; Martin
>K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski
><krzysztof.kozlowski@canonical.com>
>Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche
><bvanassche@acm.org>; Adrian Hunter <adrian.hunter@intel.com>; Christoph
>Hellwig <hch@infradead.org>; Can Guo <cang@codeaurora.org>; Jaegeuk Kim
><jaegeuk@kernel.org>; Gyunghoon Kwon <goodjob.kwon@samsung.com>;
>linux-samsung-soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park
><chanho61.park@samsung.com>; Kiwoong Kim <kwmad.kim@samsung.com>
>Subject: [PATCH v3 13/17] scsi: ufs: ufs-exynos: add pre/post_hce_enable drv
>callbacks
>
>This patch adds driver-specific pre/post_hce_enable callbacks to execute extra
>initializations before and after hce_enable_notify callback.
>
>Cc: Alim Akhtar <alim.akhtar@samsung.com>
>Cc: Kiwoong Kim <kwmad.kim@samsung.com>
>Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>Signed-off-by: Chanho Park <chanho61.park@samsung.com>
>---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>


> drivers/scsi/ufs/ufs-exynos.c | 10 ++++++++++  drivers/scsi/ufs/ufs-exynos.h |  2
>++
> 2 files changed, 12 insertions(+)
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index
>753b22358186..7fb4514f700d 100644
>--- a/drivers/scsi/ufs/ufs-exynos.c
>+++ b/drivers/scsi/ufs/ufs-exynos.c
>@@ -1141,6 +1141,12 @@ static int exynos_ufs_hce_enable_notify(struct
>ufs_hba *hba,
>
> 	switch (status) {
> 	case PRE_CHANGE:
>+		if (ufs->drv_data->pre_hce_enable) {
>+			ret = ufs->drv_data->pre_hce_enable(ufs);
>+			if (ret)
>+				return ret;
>+		}
>+
> 		ret = exynos_ufs_host_reset(hba);
> 		if (ret)
> 			return ret;
>@@ -1150,6 +1156,10 @@ static int exynos_ufs_hce_enable_notify(struct
>ufs_hba *hba,
> 		exynos_ufs_calc_pwm_clk_div(ufs);
> 		if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
> 			exynos_ufs_enable_auto_ctrl_hcc(ufs);
>+
>+		if (ufs->drv_data->post_hce_enable)
>+			ret = ufs->drv_data->post_hce_enable(ufs);
>+
> 		break;
> 	}
>
>diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index
>a0899aaa902e..c291ae51dd41 100644
>--- a/drivers/scsi/ufs/ufs-exynos.h
>+++ b/drivers/scsi/ufs/ufs-exynos.h
>@@ -154,6 +154,8 @@ struct exynos_ufs_drv_data {
> 				struct ufs_pa_layer_attr *pwr);
> 	int (*post_pwr_change)(struct exynos_ufs *ufs,
> 				struct ufs_pa_layer_attr *pwr);
>+	int (*pre_hce_enable)(struct exynos_ufs *ufs);
>+	int (*post_hce_enable)(struct exynos_ufs *ufs);
> };
>
> struct ufs_phy_time_cfg {
>--
>2.33.0

[PATCH v3 14/17] scsi: ufs: ufs-exynos: support exynosauto v9 ufs driver

[Chanho Park]

This patch adds to support ufs variant for ExynosAuto v9 SoC. This
requires control UFS IP sharability register via syscon and regmap.
Regarding uic_attr, most of values can be shared with exynos7 except
tx_dif_p_nsec value.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 96 +++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 7fb4514f700d..28f027d45917 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -15,6 +15,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #include "ufshcd.h"
 #include "ufshcd-pltfrm.h"
@@ -76,6 +77,12 @@
 				 UIC_TRANSPORT_NO_CONNECTION_RX |\
 				 UIC_TRANSPORT_BAD_TC)
 
+/* FSYS UFS Shareability */
+#define UFS_WR_SHARABLE		BIT(2)
+#define UFS_RD_SHARABLE		BIT(1)
+#define UFS_SHARABLE		(UFS_WR_SHARABLE | UFS_RD_SHARABLE)
+#define UFS_SHAREABILITY_OFFSET	0x710
+
 enum {
 	UNIPRO_L1_5 = 0,/* PHY Adapter */
 	UNIPRO_L2,	/* Data Link */
@@ -151,6 +158,79 @@ static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
 	return 0;
 }
 
+static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
+{
+	struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+
+	/* IO Coherency setting */
+	if (ufs->sysreg) {
+		return regmap_update_bits(ufs->sysreg, UFS_SHAREABILITY_OFFSET,
+					  UFS_SHARABLE, UFS_SHARABLE);
+	}
+
+	attr->tx_dif_p_nsec = 3200000;
+
+	return 0;
+}
+
+static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+	int i;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i),
+			       DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, i), 0x0);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, i), 0x2);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, i), 0x8a);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, i), 0xa3);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
+	}
+
+	for_each_ufs_tx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, i),
+			       DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, i), 0x02);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, i), 0x8);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, i), 0x22);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, i), 0x8);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
+
+	return 0;
+}
+
+static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+					 struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	/* PACP_PWR_req and delivered to the remote DME */
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+
+	return 0;
+}
+
 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
 {
 	struct ufs_hba *hba = ufs->hba;
@@ -1305,6 +1385,20 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
 	.pa_dbg_option_suite		= 0x30103,
 };
 
+static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
+	.uic_attr		= &exynos7_uic_attr,
+	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+	.opts			= EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+	.drv_init		= exynosauto_ufs_drv_init,
+	.pre_link		= exynosauto_ufs_pre_link,
+	.pre_pwr_change		= exynosauto_ufs_pre_pwr_change,
+};
+
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.uic_attr		= &exynos7_uic_attr,
 	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
@@ -1330,6 +1424,8 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 static const struct of_device_id exynos_ufs_of_match[] = {
 	{ .compatible = "samsung,exynos7-ufs",
 	  .data	      = &exynos_ufs_drvs },
+	{ .compatible = "samsung,exynosautov9-ufs",
+	  .data	      = &exynosauto_ufs_drvs },
 	{},
 };
 
-- 
2.33.0

[PATCH v3 15/17] scsi: ufs: ufs-exynos: multi-host configuration for exynosauto

[Chanho Park]

UFS controller of ExynosAuto v9 SoC supports multi-host interface for I/O
virtualization. In general, we're using para-virtualized driver to
support a block device by several virtual machines. However, it should
be relayed by backend driver. Multi-host functionality extends the host
controller by providing register interfaces that can be used by each
VM's ufs drivers respectively. By this, we can provide direct access to
the UFS device for multiple VMs. It's similar with SR-IOV of PCIe.

We divide this M-HCI as PH(Physical Host) and VHs(Virtual Host). The PH
supports all UFSHCI functions(all SAPs) same as conventional UFSHCI but
the VH only supports data transfer function. Thus, except UTP_CMD_SAP and
UTP_TMPSAP, the PH should handle all the physical features.

This patch provides an initial implementation of PH part. M-HCI can
support up to four interfaces but this patch initially supports only 1
PH and 1 VH. For this, we uses TASK_TAG[7:5] field so TASK_TAG[4:0] for
32 doorbel will be supported. After the PH is initiated, this will send
a ready message to VHs through a mailbox register. The message handler
is not fully implemented yet such as supporting reset / abort cases.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 45 +++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 28f027d45917..0ca21cd8e76e 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -83,6 +83,21 @@
 #define UFS_SHARABLE		(UFS_WR_SHARABLE | UFS_RD_SHARABLE)
 #define UFS_SHAREABILITY_OFFSET	0x710
 
+/* Multi-host registers */
+#define MHCTRL					0xC4
+#define MHCTRL_EN_VH_MASK			(0xE)
+#define MHCTRL_EN_VH(vh)			(vh << 1)
+#define PH2VH_MBOX				0xD8
+
+#define MH_MSG_MASK				(0xFF)
+
+#define MH_MSG(id, msg)				((id << 8) | (msg & 0xFF))
+#define MH_MSG_PH_READY				0x1
+#define MH_MSG_VH_READY				0x2
+
+#define HCI_MH_ALLOWABLE_TRAN_OF_VH		0x30C
+#define HCI_MH_IID_IN_TASK_TAG			0X308
+
 enum {
 	UNIPRO_L1_5 = 0,/* PHY Adapter */
 	UNIPRO_L2,	/* Data Link */
@@ -173,6 +188,20 @@ static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
 	return 0;
 }
 
+static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	/* Enable Virtual Host #1 */
+	ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
+	/* Default VH Transfer permissions */
+	hci_writel(ufs, 0x03FFE1FE, HCI_MH_ALLOWABLE_TRAN_OF_VH);
+	/* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
+	hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
+
+	return 0;
+}
+
 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
 {
 	struct ufs_hba *hba = ufs->hba;
@@ -231,6 +260,20 @@ static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
 	return 0;
 }
 
+static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
+					  struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+	u32 enabled_vh;
+
+	enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
+
+	/* Send physical host ready message to virtual hosts */
+	ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
+
+	return 0;
+}
+
 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
 {
 	struct ufs_hba *hba = ufs->hba;
@@ -1395,8 +1438,10 @@ static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
 				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
 				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
 	.drv_init		= exynosauto_ufs_drv_init,
+	.post_hce_enable	= exynosauto_ufs_post_hce_enable,
 	.pre_link		= exynosauto_ufs_pre_link,
 	.pre_pwr_change		= exynosauto_ufs_pre_pwr_change,
+	.post_pwr_change	= exynosauto_ufs_post_pwr_change,
 };
 
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
-- 
2.33.0

Re: [PATCH v3 15/17] scsi: ufs: ufs-exynos: multi-host configuration for exynosauto

[Inki Dae]

21. 9. 17. 오후 3:54에 Chanho Park 이(가) 쓴 글:
> UFS controller of ExynosAuto v9 SoC supports multi-host interface for I/O
> virtualization. In general, we're using para-virtualized driver to
> support a block device by several virtual machines. However, it should
> be relayed by backend driver. Multi-host functionality extends the host
> controller by providing register interfaces that can be used by each
> VM's ufs drivers respectively. By this, we can provide direct access to
> the UFS device for multiple VMs. It's similar with SR-IOV of PCIe.
> 
> We divide this M-HCI as PH(Physical Host) and VHs(Virtual Host). The PH
> supports all UFSHCI functions(all SAPs) same as conventional UFSHCI but
> the VH only supports data transfer function. Thus, except UTP_CMD_SAP and
> UTP_TMPSAP, the PH should handle all the physical features.
> 
> This patch provides an initial implementation of PH part. M-HCI can
> support up to four interfaces but this patch initially supports only 1
> PH and 1 VH. For this, we uses TASK_TAG[7:5] field so TASK_TAG[4:0] for
> 32 doorbel will be supported. After the PH is initiated, this will send
> a ready message to VHs through a mailbox register. The message handler
> is not fully implemented yet such as supporting reset / abort cases.
> 
> Cc: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: Kiwoong Kim <kwmad.kim@samsung.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  drivers/scsi/ufs/ufs-exynos.c | 45 +++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
> index 28f027d45917..0ca21cd8e76e 100644
> --- a/drivers/scsi/ufs/ufs-exynos.c
> +++ b/drivers/scsi/ufs/ufs-exynos.c
> @@ -83,6 +83,21 @@
>  #define UFS_SHARABLE		(UFS_WR_SHARABLE | UFS_RD_SHARABLE)
>  #define UFS_SHAREABILITY_OFFSET	0x710
>  
> +/* Multi-host registers */
> +#define MHCTRL					0xC4
> +#define MHCTRL_EN_VH_MASK			(0xE)
> +#define MHCTRL_EN_VH(vh)			(vh << 1)
> +#define PH2VH_MBOX				0xD8
> +
> +#define MH_MSG_MASK				(0xFF)
> +
> +#define MH_MSG(id, msg)				((id << 8) | (msg & 0xFF))
> +#define MH_MSG_PH_READY				0x1
> +#define MH_MSG_VH_READY				0x2
> +
> +#define HCI_MH_ALLOWABLE_TRAN_OF_VH		0x30C
> +#define HCI_MH_IID_IN_TASK_TAG			0X308
> +
>  enum {
>  	UNIPRO_L1_5 = 0,/* PHY Adapter */
>  	UNIPRO_L2,	/* Data Link */
> @@ -173,6 +188,20 @@ static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
>  	return 0;
>  }
>  
> +static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
> +{
> +	struct ufs_hba *hba = ufs->hba;
> +
> +	/* Enable Virtual Host #1 */
> +	ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
> +	/* Default VH Transfer permissions */
> +	hci_writel(ufs, 0x03FFE1FE, HCI_MH_ALLOWABLE_TRAN_OF_VH);

How about using a defined macro instead of constant value, 0x03FFE1FE for code readability? And maybe 0x03FFE1FE to 0x3FFE1FE.

Thanks,
Inki Dae

> +	/* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
> +	hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
> +
> +	return 0;
> +}
> +
>  static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
>  {
>  	struct ufs_hba *hba = ufs->hba;
> @@ -231,6 +260,20 @@ static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
>  	return 0;
>  }
>  
> +static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
> +					  struct ufs_pa_layer_attr *pwr)
> +{
> +	struct ufs_hba *hba = ufs->hba;
> +	u32 enabled_vh;
> +
> +	enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
> +
> +	/* Send physical host ready message to virtual hosts */
> +	ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
> +
> +	return 0;
> +}
> +
>  static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
>  {
>  	struct ufs_hba *hba = ufs->hba;
> @@ -1395,8 +1438,10 @@ static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
>  				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
>  				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
>  	.drv_init		= exynosauto_ufs_drv_init,
> +	.post_hce_enable	= exynosauto_ufs_post_hce_enable,
>  	.pre_link		= exynosauto_ufs_pre_link,
>  	.pre_pwr_change		= exynosauto_ufs_pre_pwr_change,
> +	.post_pwr_change	= exynosauto_ufs_post_pwr_change,
>  };
>  
>  static struct exynos_ufs_drv_data exynos_ufs_drvs = {
> 

RE: [PATCH v3 15/17] scsi: ufs: ufs-exynos: multi-host configuration for exynosauto

[Chanho Park]

> > +static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) {
> > +	struct ufs_hba *hba = ufs->hba;
> > +
> > +	/* Enable Virtual Host #1 */
> > +	ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
> > +	/* Default VH Transfer permissions */
> > +	hci_writel(ufs, 0x03FFE1FE, HCI_MH_ALLOWABLE_TRAN_OF_VH);
> 
> How about using a defined macro instead of constant value, 0x03FFE1FE for
> code readability? And maybe 0x03FFE1FE to 0x3FFE1FE.

When I saw the value first time, I also thought it should be defined as macro but there are too many bits(26) to be described and I felt no one controls it from the default value. I'll try to use macro or at least documentation by comment next patch.
Thanks.

Best Regards,
Chanho Park

[PATCH v3 16/17] scsi: ufs: ufs-exynos: introduce exynosauto v9 virtual host

[Chanho Park]

This patch introduces virtual host driver of exynosauto v9 ufs mHCI.
VH(Virtual Host) only supports data transfer functions. So, most of
physical features are broken. So, we need to set below quirks.
- UFSHCD_QUIRK_BROKEN_UIC_CMD
- UFSHCD_QUIRK_SKIP_PH_CONFIGURATION
Before initialization, the VH is necessary to wait until PH is ready.
It's implemented as polling at the moment.

Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Kiwoong Kim <kwmad.kim@samsung.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.c | 84 +++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c
index 0ca21cd8e76e..2e71138ce566 100644
--- a/drivers/scsi/ufs/ufs-exynos.c
+++ b/drivers/scsi/ufs/ufs-exynos.c
@@ -98,6 +98,8 @@
 #define HCI_MH_ALLOWABLE_TRAN_OF_VH		0x30C
 #define HCI_MH_IID_IN_TASK_TAG			0X308
 
+#define PH_READY_TIMEOUT_MS			(5 * MSEC_PER_SEC)
+
 enum {
 	UNIPRO_L1_5 = 0,/* PHY Adapter */
 	UNIPRO_L2,	/* Data Link */
@@ -1362,6 +1364,68 @@ static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 	return 0;
 }
 
+static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba,
+						 enum ufs_notify_change_status status)
+{
+	if (status == POST_CHANGE) {
+		ufshcd_set_link_active(hba);
+		ufshcd_set_ufs_dev_active(hba);
+		hba->wlun_dev_clr_ua = true;
+	}
+
+	return 0;
+}
+
+static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba)
+{
+	u32 mbox;
+	ktime_t start, stop;
+
+	start = ktime_get();
+	stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS));
+
+	do {
+		mbox = ufshcd_readl(hba, PH2VH_MBOX);
+		if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY)
+			return 0;
+
+		usleep_range(40, 50);
+	} while (ktime_before(ktime_get(), stop));
+
+	return -ETIME;
+}
+
+static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
+{
+	struct device *dev = hba->dev;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct exynos_ufs *ufs;
+	int ret;
+
+	ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
+	if (!ufs)
+		return -ENOMEM;
+
+	/* exynos-specific hci */
+	ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
+	if (IS_ERR(ufs->reg_hci)) {
+		dev_err(dev, "cannot ioremap for hci vendor register\n");
+		return PTR_ERR(ufs->reg_hci);
+	}
+
+	ret = exynosauto_ufs_vh_wait_ph_ready(hba);
+	if (ret)
+		return ret;
+
+	ufs->drv_data = device_get_match_data(dev);
+	if (!ufs->drv_data)
+		return -ENODEV;
+
+	exynos_ufs_priv_init(hba, ufs);
+
+	return 0;
+}
+
 static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
 	.name				= "exynos_ufs",
 	.init				= exynos_ufs_init,
@@ -1376,6 +1440,12 @@ static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
 	.resume				= exynos_ufs_resume,
 };
 
+static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
+	.name				= "exynosauto_ufs_vh",
+	.init				= exynosauto_ufs_vh_init,
+	.link_startup_notify		= exynosauto_ufs_vh_link_startup_notify,
+};
+
 static int exynos_ufs_probe(struct platform_device *pdev)
 {
 	int err;
@@ -1444,6 +1514,18 @@ static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
 	.post_pwr_change	= exynosauto_ufs_post_pwr_change,
 };
 
+static struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = {
+	.vops			= &ufs_hba_exynosauto_vh_ops,
+	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+				  UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
+				  UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+				  UFSHCI_QUIRK_BROKEN_HCE |
+				  UFSHCD_QUIRK_BROKEN_UIC_CMD |
+				  UFSHCD_QUIRK_SKIP_PH_CONFIGURATION |
+				  UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+	.opts			= EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
+};
+
 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
 	.uic_attr		= &exynos7_uic_attr,
 	.quirks			= UFSHCD_QUIRK_PRDT_BYTE_GRAN |
@@ -1471,6 +1553,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
 	  .data	      = &exynos_ufs_drvs },
 	{ .compatible = "samsung,exynosautov9-ufs",
 	  .data	      = &exynosauto_ufs_drvs },
+	{ .compatible = "samsung,exynosautov9-ufs-vh",
+	  .data	      = &exynosauto_ufs_vh_drvs },
 	{},
 };
 
-- 
2.33.0

[PATCH v3 17/17] dt-bindings: ufs: exynos-ufs: add exynosautov9 compatible

[Chanho Park]

Below two compatibles can be used for exynosautov9 SoC UFS controller.

- samsung,exynosautov9-ufs: ExynosAutov9 UFS Physical Host
- samsung,exynosautov9-ufs-vh: ExynosAutov9 UFS Virtual Host

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index c3f14f81d4b7..832f0770433e 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -20,6 +20,8 @@ properties:
   compatible:
     enum:
       - samsung,exynos7-ufs
+      - samsung,exynosautov9-ufs
+      - samsung,exynosautov9-ufs-vh
 
   reg:
     items:
-- 
2.33.0

Re: [PATCH v3 17/17] dt-bindings: ufs: exynos-ufs: add exynosautov9 compatible

[Rob Herring]

On Fri, 17 Sep 2021 15:54:36 +0900, Chanho Park wrote:
> Below two compatibles can be used for exynosautov9 SoC UFS controller.
> 
> - samsung,exynosautov9-ufs: ExynosAutov9 UFS Physical Host
> - samsung,exynosautov9-ufs-vh: ExynosAutov9 UFS Virtual Host
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>