[PATCH 0/2] scsi: ufs: ufs-pci: Intel UFS 4.0 HS-Gear5 and MCQ support

[PATCH 0/2] scsi: ufs: ufs-pci: Intel UFS 4.0 HS-Gear5 and MCQ support

[sangram kumar yerra]

096cd6b7adf2 ("scsi: ufs: ufs-pci: Add support for Intel Nova Lake")
added the PCI ID for Intel's UFS 4.0 controller (8086:D335), reusing
the existing Meteor Lake variant operations table. That table is
missing two things this controller needs to work correctly at UFS 4.0
capability: a PA_INITIAL_ADAPT sequence for reliable HS-Gear5 link
training, and the MCQ resource/runtime-config hooks required for
ufshcd_alloc_mcq() to succeed. Without either, the controller still
works, but silently falls back to Gear5 link instability or legacy
single-doorbell mode respectively.

Patch 1 adds a pwr_change_notify hook that configures
PA_INITIAL_ADAPT (resetting to the default PA_NO_ADAPT otherwise)
before Gear5 power mode changes.

Patch 2 adds the mcq_config_resource and op_runtime_config hooks,
with the OPR register offsets and stride this controller uses.

Both were validated on real NVL silicon: a 10-cycle reboot trial (5
minutes monitored each) with this exact configuration showed zero
UIC-layer errors throughout, and MCQ hardware queues were confirmed
carrying real doorbell traffic at the documented addresses.

sangram kumar yerra (2):
  scsi: ufs: ufs-pci: Add support for Intel UFS 4.0 HS-Gear5
  scsi: ufs: ufs-pci: Add MCQ support for Intel UFS 4.0 controllers

 drivers/ufs/host/ufshcd-pci.c | 59 +++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

-- 
2.34.1

[PATCH 1/2] scsi: ufs: ufs-pci: Add support for Intel UFS 4.0 HS-Gear5

[sangram kumar yerra]

Reliable HS-Gear5 operation on Intel UFS 4.0 controllers requires
configuring PA_INITIAL_ADAPT before changing the power mode. Without
this setting, the link fails to train reliably at Gear5.

Add a pwr_change_notify() hook to configure the adaptation mode before
the power mode transition. Enable this only for UFS 4.0 and later
controllers by checking hba->ufs_version.

Wire the hook into the existing Meteor Lake family variant operations
table (ufs_intel_mtl_hba_vops) instead of introducing a separate table,
since the Intel UFS 4.0 PCI variant (PCI ID 8086:D335) already uses
this vops table and the hook is internally gated on UFS version >= 4.0.

Use PA_INITIAL_ADAPT when the negotiated TX power mode is FAST_MODE or
FASTAUTO_MODE. Otherwise, reset the adaptation mode to PA_NO_ADAPT,
which is the default setting.

Fixes: 096cd6b7adf2 ("scsi: ufs: ufs-pci: Add support for Intel Nova Lake")
Signed-off-by: sangram kumar yerra <sangram.k.y@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
---
 drivers/ufs/host/ufshcd-pci.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c
index f2433879b0eb..93bfafc25018 100644
--- a/drivers/ufs/host/ufshcd-pci.c
+++ b/drivers/ufs/host/ufshcd-pci.c
@@ -181,6 +181,25 @@ static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba,
 	return err;
 }
 
+static int ufs_intel_nvl_pwr_change_notify(struct ufs_hba *hba,
+					   enum ufs_notify_change_status stage,
+					   struct ufs_pa_layer_attr *dev_req_params)
+{
+	int adapt_val;
+
+	if (stage != PRE_CHANGE || hba->ufs_version < ufshci_version(4, 0))
+		return 0;
+
+	if (dev_req_params->pwr_tx == FAST_MODE || dev_req_params->pwr_tx == FASTAUTO_MODE)
+		adapt_val = PA_INITIAL_ADAPT;
+	else
+		adapt_val = PA_NO_ADAPT;
+
+	ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, adapt_val);
+
+	return 0;
+}
+
 static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba)
 {
 	u32 granularity, peer_granularity;
@@ -527,6 +546,7 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
 	.exit			= ufs_intel_common_exit,
 	.hce_enable_notify	= ufs_intel_hce_enable_notify,
 	.link_startup_notify	= ufs_intel_link_startup_notify,
+	.pwr_change_notify	= ufs_intel_nvl_pwr_change_notify,
 	.resume			= ufs_intel_resume,
 	.device_reset		= ufs_intel_device_reset,
 };
-- 
2.34.1

[PATCH 2/2] scsi: ufs: ufs-pci: Add MCQ support for Intel UFS 4.0 controllers

[sangram kumar yerra]

The Intel UFS 4.0 PCI variant (PCI ID 8086:D335) advertises MCQ
support in its capability register. However, ufshcd_alloc_mcq() also
requires an .op_runtime_config hook to locate the per-queue operation
and runtime (OPR) register blocks, which was not provided by this
variant operations table.

As a result, MCQ initialization fails and ufshcd_add_scsi_host()
prints "MCQ mode is disabled, err=%d\n" before falling back to
legacy single-doorbell (SDB) mode.

Add ufs_intel_mcq_config_resource() to initialize the MCQ
configuration base and add ufs_intel_op_runtime_config() to set up
the OPR register offsets and stride.

Wire both hooks into the variant operations table so MCQ is enabled
when supported by the hardware.

Fixes: 096cd6b7adf2 ("scsi: ufs: ufs-pci: Add support for Intel Nova Lake")
Signed-off-by: sangram kumar yerra <sangram.k.y@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
---
 drivers/ufs/host/ufshcd-pci.c | 39 +++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/ufs/host/ufshcd-pci.c b/drivers/ufs/host/ufshcd-pci.c
index 93bfafc25018..21bb11c724be 100644
--- a/drivers/ufs/host/ufshcd-pci.c
+++ b/drivers/ufs/host/ufshcd-pci.c
@@ -460,6 +460,43 @@ static int ufs_intel_mtl_init(struct ufs_hba *hba)
 	return ufs_intel_common_init(hba);
 }
 
+static int ufs_intel_mcq_config_resource(struct ufs_hba *hba)
+{
+	hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba);
+
+	return 0;
+}
+
+/*
+ * This Intel UFS4.0 controller maps MCQ doorbell and interrupt-status
+ * registers into the same PCI BAR as the legacy HCI space, at this
+ * fixed offset/stride.
+ */
+#define UFS_INTEL_SQDAO0	0x2800
+#define UFS_INTEL_SQISAO0	0x2814
+#define UFS_INTEL_CQDAO0	0x281C
+#define UFS_INTEL_CQISAO0	0x2824
+#define UFS_INTEL_MCQ_STRIDE	0x30
+
+static int ufs_intel_op_runtime_config(struct ufs_hba *hba)
+{
+	struct ufshcd_mcq_opr_info_t *opr;
+	int i;
+
+	hba->mcq_opr[OPR_SQD].offset  = UFS_INTEL_SQDAO0;
+	hba->mcq_opr[OPR_SQIS].offset = UFS_INTEL_SQISAO0;
+	hba->mcq_opr[OPR_CQD].offset  = UFS_INTEL_CQDAO0;
+	hba->mcq_opr[OPR_CQIS].offset = UFS_INTEL_CQISAO0;
+
+	for (i = 0; i < OPR_MAX; i++) {
+		opr = &hba->mcq_opr[i];
+		opr->stride = UFS_INTEL_MCQ_STRIDE;
+		opr->base = hba->mmio_base + opr->offset;
+	}
+
+	return 0;
+}
+
 static int ufs_qemu_get_hba_mac(struct ufs_hba *hba)
 {
 	return MAX_SUPP_MAC;
@@ -547,6 +584,8 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
 	.hce_enable_notify	= ufs_intel_hce_enable_notify,
 	.link_startup_notify	= ufs_intel_link_startup_notify,
 	.pwr_change_notify	= ufs_intel_nvl_pwr_change_notify,
+	.mcq_config_resource	= ufs_intel_mcq_config_resource,
+	.op_runtime_config	= ufs_intel_op_runtime_config,
 	.resume			= ufs_intel_resume,
 	.device_reset		= ufs_intel_device_reset,
 };
-- 
2.34.1

Re: [PATCH 0/2] scsi: ufs: ufs-pci: Intel UFS 4.0 HS-Gear5 and MCQ support

[Bart Van Assche]

On 8/18/26 4:28 AM, sangram kumar yerra wrote:
> [ ... ]

Reviewed-by: Bart Van Assche <bvanassche@acm.org>