[PATCH V2 0/2] ufs: ufs-qcom: Fixes and optimizations for Qualcomm UFS Controller

[PATCH V2 0/2] ufs: ufs-qcom: Fixes and optimizations for Qualcomm UFS Controller

[Nitin Rawat]

This patch series introduces few fixes and performance optimizations
for the Qualcomm UFS host controller driver to improve performance
and to align with Qualcomm UFS hardware programming sequence.

The series addresses below issues:
1. Hardware programming sequence alignment for UFS controller v6.2
2. Performance tuning for sequential read workloads.

Changes from V1:
1. Dropped ufs: ufs-qcom: Add UFS ESI CPU affinity support from V1.
   I'll work and take it in separately in different series.
2. Addressed Konrad's comment to change version check from "only v6.2"
   to "starting with v6.2".
3. Addressed Konrad's comment to fix comment wording ("HS/LS" instead
    of "HS-LSS"):

Nitin Rawat (2):
  ufs: ufs-qcom: Restore HS/LS link startup mode for Qualcomm UFS
    controller v6.2+
  ufs: ufs-qcom: Fix sequential read variance

 drivers/ufs/host/ufs-qcom.c | 17 +++++++++++++----
 drivers/ufs/host/ufs-qcom.h |  1 +
 2 files changed, 14 insertions(+), 4 deletions(-)

--
2.34.1

[PATCH V2 1/2] ufs: ufs-qcom: Restore HS/LS link startup mode for Qualcomm UFS controller v6.2+

[Nitin Rawat]

The link startup mode (HS LSS - high-speed link startup, or LS LSS -
low-speed link startup) is decided in the boot stage based on the
bootconfig GPIO. This selection is carried forward through the secondary
stage bootloaders and finally to HLOS via the spare configuration
register (REG_UFS_DEBUG_SPARE_CFG).

On Qualcomm UFS controller v6.2 and later, bit 31 in the spare
configuration register indicates the high-speed link startup mode
selection, as per the Hardware Programming Guide (HPG).

The spare register value is read during host driver initialization but
gets cleared after UFS reset. Preserve the spare register value during
initialization and restore it during link startup to maintain the
bootloader-configured link startup mode.

Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
---
 drivers/ufs/host/ufs-qcom.c | 15 ++++++++++++---
 drivers/ufs/host/ufs-qcom.h |  1 +
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 291c43448764..35bb9ab5fa2c 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -715,6 +715,7 @@ static void ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 					enum ufs_notify_change_status status)
 {
+	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 	int err = 0;

 	switch (status) {
@@ -737,6 +738,14 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 		 */
 		err = ufshcd_disable_host_tx_lcc(hba);

+		/*
+		 * Restore HS/LS link startup mode set by bootloader
+		 * after UFS reset clears REG_UFS_DEBUG_SPARE_CFG.
+		 */
+		if (host->hw_ver.major > 0x6 ||
+		    (host->hw_ver.major == 0x6 && host->hw_ver.minor >= 0x2))
+			ufshcd_writel(hba, host->boot_spare_cfg,
+				      REG_UFS_DEBUG_SPARE_CFG);
 		break;
 	case POST_CHANGE:
 		ufs_qcom_link_startup_post_change(hba);
@@ -1325,7 +1334,7 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
 {
 	struct ufs_host_params *host_params = &host->host_params;
-	u32 val, dev_major;
+	u32 dev_major;

 	/*
 	 * Default to powering up the PHY to the max gear possible, which is
@@ -1344,8 +1353,8 @@ static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
 		 */
 		host->phy_gear = UFS_HS_G2;
 	} else if (host->hw_ver.major >= 0x5) {
-		val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
-		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
+		host->boot_spare_cfg = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
+		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, host->boot_spare_cfg);

 		/*
 		 * Since the UFS device version is populated, let's remove the
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index e20b3ca50577..a5ad5ce44a19 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -361,6 +361,7 @@ struct ufs_qcom_host {
 	bool esi_enabled;

 	u32 saved_tx_eq_g1_setting;
+	u32 boot_spare_cfg;
 };

 struct ufs_qcom_drvdata {
--
2.34.1

[PATCH V2 2/2] ufs: ufs-qcom: Fix sequential read variance

[Nitin Rawat]

The current devfreq downdifferential threshold of 5% causes overly
aggressive frequency downscaling, leading to performance degradation
sometimes during sequential read workloads.

Update the UFS devfreq downdifferential threshold to 65.
This widens the hysteresis window and prevents overly aggressive
downscaling, ensuring that frequency is maintained for loads above 5%
and scaling down occurs only when utilization falls below this level,
while scale-up still triggers above the 70% threshold.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
---
 drivers/ufs/host/ufs-qcom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 35bb9ab5fa2c..16cf1260cbfb 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -2291,7 +2291,7 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
 	p->polling_ms = 60;
 	p->timer = DEVFREQ_TIMER_DELAYED;
 	d->upthreshold = 70;
-	d->downdifferential = 5;
+	d->downdifferential = 65;

 	hba->clk_scaling.suspend_on_no_request = true;
 }
--
2.34.1

Re: [PATCH V2 1/2] ufs: ufs-qcom: Restore HS/LS link startup mode for Qualcomm UFS controller v6.2+

[Mukesh Ojha]

On Tue, Aug 25, 2026 at 08:22:02PM +0530, Nitin Rawat wrote:
> The link startup mode (HS LSS - high-speed link startup, or LS LSS -
> low-speed link startup) is decided in the boot stage based on the
> bootconfig GPIO. This selection is carried forward through the secondary
> stage bootloaders and finally to HLOS via the spare configuration
> register (REG_UFS_DEBUG_SPARE_CFG).
> 
> On Qualcomm UFS controller v6.2 and later, bit 31 in the spare
> configuration register indicates the high-speed link startup mode
> selection, as per the Hardware Programming Guide (HPG).
> 
> The spare register value is read during host driver initialization but
> gets cleared after UFS reset. Preserve the spare register value during
> initialization and restore it during link startup to maintain the
> bootloader-configured link startup mode.
> 
> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>


Tested-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>

-Mukesh