* [PATCH V7 1/2] ufs: core: Configure only active lanes during link
2026-04-23 10:20 [PATCH V7 0/2] Add post change sequence for link start notify palash.kambar
@ 2026-04-23 10:20 ` palash.kambar
2026-04-23 10:20 ` [PATCH V7 2/2] ufs: ufs-qcom: Enable Auto Hibern8 clock request support palash.kambar
1 sibling, 0 replies; 4+ messages in thread
From: palash.kambar @ 2026-04-23 10:20 UTC (permalink / raw)
To: mani, James.Bottomley, martin.petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, bvanassche, shawn.lin,
nitin.rawat, Palash Kambar
From: Palash Kambar <palash.kambar@oss.qualcomm.com>
The number of connected lanes detected during UFS link startup can be
fewer than the lanes specified in the device tree. The current driver
logic attempts to configure all lanes defined in the device tree,
regardless of their actual availability. This mismatch may cause
failures during power mode changes.
Hence, Add a check during link startup to ensure that only the lanes
actually discovered are considered valid. If a mismatch is detected,
fail the initialization early, preventing the driver from entering
an unsupported configuration that could cause power mode transition
failures.
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Palash Kambar <palash.kambar@oss.qualcomm.com>
---
drivers/ufs/core/ufshcd.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 31950fc51a4c..81a71616230a 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -5035,6 +5035,35 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
}
EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
+static int ufshcd_validate_link_params(struct ufs_hba *hba)
+{
+ int ret, val;
+
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
+ &val);
+ if (ret)
+ return ret;
+
+ if (val != hba->lanes_per_direction) {
+ dev_err(hba->dev, "Tx lane mismatch [config,reported] [%d,%d]\n",
+ hba->lanes_per_direction, val);
+ return -ENOLINK;
+ }
+
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
+ &val);
+ if (ret)
+ return ret;
+
+ if (val != hba->lanes_per_direction) {
+ dev_err(hba->dev, "Rx lane mismatch [config,reported] [%d,%d]\n",
+ hba->lanes_per_direction, val);
+ return -ENOLINK;
+ }
+
+ return 0;
+}
+
/**
* ufshcd_link_startup - Initialize unipro link startup
* @hba: per adapter instance
@@ -5108,6 +5137,10 @@ static int ufshcd_link_startup(struct ufs_hba *hba)
goto out;
}
+ ret = ufshcd_validate_link_params(hba);
+ if (ret)
+ goto out;
+
/* Include any host controller configuration via UIC commands */
ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
if (ret)
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH V7 2/2] ufs: ufs-qcom: Enable Auto Hibern8 clock request support
2026-04-23 10:20 [PATCH V7 0/2] Add post change sequence for link start notify palash.kambar
2026-04-23 10:20 ` [PATCH V7 1/2] ufs: core: Configure only active lanes during link palash.kambar
@ 2026-04-23 10:20 ` palash.kambar
2026-04-27 15:57 ` Bart Van Assche
1 sibling, 1 reply; 4+ messages in thread
From: palash.kambar @ 2026-04-23 10:20 UTC (permalink / raw)
To: mani, James.Bottomley, martin.petersen
Cc: linux-arm-msm, linux-scsi, linux-kernel, bvanassche, shawn.lin,
nitin.rawat, Palash Kambar
From: Palash Kambar <palash.kambar@oss.qualcomm.com>
On platforms that support Auto Hibern8 (AH8), the UFS controller can
autonomously de-assert clk_req signals to the Global Clock Controller
when entering the Hibern8 state. This allows Global Clock Controller
(GCC) to gate unused clocks, improving power efficiency.
Enable the Clock Request feature by setting the UFS_HW_CLK_CTRL_EN
bit in the UFS_AH8_CFG register, as recommended in the Hardware
Programming Guidelines.
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Palash Kambar <palash.kambar@oss.qualcomm.com>
---
drivers/ufs/host/ufs-qcom.c | 10 ++++++++++
drivers/ufs/host/ufs-qcom.h | 11 +++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 8ebee0cc5313..ed4c531e1fb2 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -683,6 +683,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
return 0;
}
+static void ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
+{
+ if (ufshcd_is_auto_hibern8_supported(hba))
+ ufshcd_rmwl(hba, UFS_HW_CLK_CTRL_EN, UFS_HW_CLK_CTRL_EN,
+ UFS_AH8_CFG);
+}
+
static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status)
{
@@ -708,6 +715,9 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
*/
err = ufshcd_disable_host_tx_lcc(hba);
+ break;
+ case POST_CHANGE:
+ ufs_qcom_link_startup_post_change(hba);
break;
default:
break;
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 380d02333d38..f19def37c86f 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -228,6 +228,17 @@ enum {
*/
#define NUM_TX_R1W1 13
+/* bit definitions for UFS_AH8_CFG register */
+#define CC_UFS_SYS_CLK_REQ_EN BIT(2)
+#define CC_UFS_ICE_CORE_CLK_REQ_EN BIT(3)
+#define CC_UFS_UNIPRO_CORE_CLK_REQ_EN BIT(4)
+#define CC_UFS_AUXCLK_REQ_EN BIT(5)
+
+#define UFS_HW_CLK_CTRL_EN (CC_UFS_SYS_CLK_REQ_EN |\
+ CC_UFS_ICE_CORE_CLK_REQ_EN |\
+ CC_UFS_UNIPRO_CORE_CLK_REQ_EN |\
+ CC_UFS_AUXCLK_REQ_EN)
+
static inline void
ufs_qcom_get_controller_revision(struct ufs_hba *hba,
u8 *major, u16 *minor, u16 *step)
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread