[PATCH v3 0/2] pm80xx updates

[PATCH v3 0/2] pm80xx updates

[Ajish Koshy]

This patchset includes bugfixes for pm80xx driver

Changes from v2 to v3:
	- For upper interrupt vector patch
		- Removed 'mask' and 'vec' variables
	- For upper inbound outbound queues patch
		- Added a space before '*/'

Changes from v1 to v2:
        - For upper interrupt vectors patch
                - Removed unrequired casts u32
                - Removed '& 0xFFFFFFFF' operation
                - Removed 'vec_u' variable
                - Added 'Fixes' tag.
        - For upper inbound outbound queues patch
                - Removed brackets
                - Removed comments about msleep
                - Added 'Fixes' tag.

Ajish Koshy (2):
  scsi: pm80xx: mask and unmask upper interrupt vectors 32-63
  scsi: pm80xx: enable upper inbound, outbound queues

 drivers/scsi/pm8001/pm80xx_hwi.c | 36 +++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 10 deletions(-)

-- 
2.31.1

[PATCH v3 1/2] scsi: pm80xx: mask and unmask upper interrupt vectors 32-63

[Ajish Koshy]

When upper inbound and outbound queues 32-63 are enabled, we see upper
vectors 32-63 in interrupt service routine. We need corresponding
registers to handle masking and unmasking of these upper interrupts.

To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and
MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit
0-31 represents interrupt vectors 32-63.

Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
Signed-off-by: Viswas G <Viswas.G@microchip.com>
Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")
---
 drivers/scsi/pm8001/pm80xx_hwi.c | 30 ++++++++++++++++++++----------
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
index 9bb31f66db85..cdb31679f419 100644
--- a/drivers/scsi/pm8001/pm80xx_hwi.c
+++ b/drivers/scsi/pm8001/pm80xx_hwi.c
@@ -1727,10 +1727,14 @@ static void
 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
 #ifdef PM8001_USE_MSIX
-	u32 mask;
-	mask = (u32)(1 << vec);
-
-	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
+	if (vec < 32) {
+		/* vectors 0 - 31 */
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
+	} else {
+		/* vectors 32 - 63 */
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
+			    1U << (vec - 32));
+	}
 	return;
 #endif
 	pm80xx_chip_intx_interrupt_enable(pm8001_ha);
@@ -1746,12 +1750,18 @@ static void
 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
 {
 #ifdef PM8001_USE_MSIX
-	u32 mask;
-	if (vec == 0xFF)
-		mask = 0xFFFFFFFF;
-	else
-		mask = (u32)(1 << vec);
-	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
+	if (vec == 0xFF) {
+		/* disable all vectors 0-31, 32-63 */
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
+	} else if (vec < 32) {
+		/* vectors 0 - 31 */
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
+	} else {
+		/* vectors 32 - 63 */
+		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
+			    1U << (vec - 32));
+	}
 	return;
 #endif
 	pm80xx_chip_intx_interrupt_disable(pm8001_ha);
-- 
2.31.1

[PATCH v3 2/2] scsi: pm80xx: enable upper inbound, outbound queues

[Ajish Koshy]

Executing driver on servers with more than 32 CPUs were faced with command
timeouts. This is because we were not geting completions for commands
submitted on IQ32 - IQ63.

Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in the
MPI main configuration table.

Added 500ms delay after successful MPI initialization as mentioned in
controller datasheet.

Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
Signed-off-by: Viswas G <Viswas.G@microchip.com>
Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
 drivers/scsi/pm8001/pm80xx_hwi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
index cdb31679f419..71b6cc4b9420 100644
--- a/drivers/scsi/pm8001/pm80xx_hwi.c
+++ b/drivers/scsi/pm8001/pm80xx_hwi.c
@@ -766,6 +766,10 @@ static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity	= 0x01;
 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt		= 0x01;
 
+	/* Enable higher IQs and OQs, 32 to 63, bit 16 */
+	if (pm8001_ha->max_q_num > 32)
+		pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
+							1 << 16;
 	/* Disable end to end CRC checking */
 	pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 
@@ -1027,6 +1031,8 @@ static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 	if (0x0000 != gst_len_mpistate)
 		return -EBUSY;
 
+	msleep(500);
+
 	return 0;
 }
 
-- 
2.31.1

Re: [PATCH v3 1/2] scsi: pm80xx: mask and unmask upper interrupt vectors 32-63

[Jinpu Wang]

On Fri, Apr 8, 2022 at 10:05 AM Ajish Koshy <Ajish.Koshy@microchip.com> wrote:
>
> When upper inbound and outbound queues 32-63 are enabled, we see upper
> vectors 32-63 in interrupt service routine. We need corresponding
> registers to handle masking and unmasking of these upper interrupts.
>
> To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and
> MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit
> 0-31 represents interrupt vectors 32-63.
>
> Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
> Signed-off-by: Viswas G <Viswas.G@microchip.com>
> Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")
Acked-by: Jack Wang <jinpu.wang@ionos.com>
> ---
>  drivers/scsi/pm8001/pm80xx_hwi.c | 30 ++++++++++++++++++++----------
>  1 file changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
> index 9bb31f66db85..cdb31679f419 100644
> --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> @@ -1727,10 +1727,14 @@ static void
>  pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
>  {
>  #ifdef PM8001_USE_MSIX
> -       u32 mask;
> -       mask = (u32)(1 << vec);
> -
> -       pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
> +       if (vec < 32) {
> +               /* vectors 0 - 31 */
> +               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
> +       } else {
> +               /* vectors 32 - 63 */
> +               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
> +                           1U << (vec - 32));
> +       }
>         return;
>  #endif
>         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
> @@ -1746,12 +1750,18 @@ static void
>  pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
>  {
>  #ifdef PM8001_USE_MSIX
> -       u32 mask;
> -       if (vec == 0xFF)
> -               mask = 0xFFFFFFFF;
> -       else
> -               mask = (u32)(1 << vec);
> -       pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
> +       if (vec == 0xFF) {
> +               /* disable all vectors 0-31, 32-63 */
> +               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
> +               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
> +       } else if (vec < 32) {
> +               /* vectors 0 - 31 */
> +               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
> +       } else {
> +               /* vectors 32 - 63 */
> +               pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
> +                           1U << (vec - 32));
> +       }
>         return;
>  #endif
>         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
> --
> 2.31.1
>

Re: [PATCH v3 2/2] scsi: pm80xx: enable upper inbound, outbound queues

[Jinpu Wang]

On Fri, Apr 8, 2022 at 10:05 AM Ajish Koshy <Ajish.Koshy@microchip.com> wrote:
>
> Executing driver on servers with more than 32 CPUs were faced with command
> timeouts. This is because we were not geting completions for commands
> submitted on IQ32 - IQ63.
>
> Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in the
> MPI main configuration table.
>
> Added 500ms delay after successful MPI initialization as mentioned in
> controller datasheet.
>
> Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
> Signed-off-by: Viswas G <Viswas.G@microchip.com>
> Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")
> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Acked-by: Jack Wang <jinpu.wang@ionos.com>
> ---
>  drivers/scsi/pm8001/pm80xx_hwi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
> index cdb31679f419..71b6cc4b9420 100644
> --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> @@ -766,6 +766,10 @@ static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
>         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
>         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
>
> +       /* Enable higher IQs and OQs, 32 to 63, bit 16 */
> +       if (pm8001_ha->max_q_num > 32)
> +               pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
> +                                                       1 << 16;
>         /* Disable end to end CRC checking */
>         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
>
> @@ -1027,6 +1031,8 @@ static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
>         if (0x0000 != gst_len_mpistate)
>                 return -EBUSY;
>
> +       msleep(500);
> +
>         return 0;
>  }
>
> --
> 2.31.1
>

Re: [PATCH v3 2/2] scsi: pm80xx: enable upper inbound, outbound queues

[John Garry]

On 08/04/2022 09:05, Ajish Koshy wrote:
> Executing driver on servers with more than 32 CPUs were faced with command
> timeouts. This is because we were not geting completions for commands
> submitted on IQ32 - IQ63.
> 
> Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in the
> MPI main configuration table.
> 
> Added 500ms delay after successful MPI initialization as mentioned in
> controller datasheet.
> 
> Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
> Signed-off-by: Viswas G <Viswas.G@microchip.com>
> Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")
> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
> ---
>   drivers/scsi/pm8001/pm80xx_hwi.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
> index cdb31679f419..71b6cc4b9420 100644
> --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> @@ -766,6 +766,10 @@ static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
>   	pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity	= 0x01;
>   	pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt		= 0x01;
>   
> +	/* Enable higher IQs and OQs, 32 to 63, bit 16 */
> +	if (pm8001_ha->max_q_num > 32)
> +		pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
> +							1 << 16;
>   	/* Disable end to end CRC checking */
>   	pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
>   
> @@ -1027,6 +1031,8 @@ static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
>   	if (0x0000 != gst_len_mpistate)
>   		return -EBUSY;
>   
> +	msleep(500);

Personally I think you should mention where this 500ms value comes from 
  (the datasheet), as it is not arbitrary

The change looks ok apart from that

> +
>   	return 0;
>   }
>   

Re: [PATCH v3 1/2] scsi: pm80xx: mask and unmask upper interrupt vectors 32-63

[John Garry]

On 08/04/2022 09:05, Ajish Koshy wrote:
> When upper inbound and outbound queues 32-63 are enabled, we see upper
> vectors 32-63 in interrupt service routine. We need corresponding
> registers to handle masking and unmasking of these upper interrupts.
> 
> To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and
> MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit
> 0-31 represents interrupt vectors 32-63.
> 
> Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
> Signed-off-by: Viswas G <Viswas.G@microchip.com>
> Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues")

Regardless of nitpick:
Reviewed-by: John Garry <john.garry@huawei.com>

> ---
>   drivers/scsi/pm8001/pm80xx_hwi.c | 30 ++++++++++++++++++++----------
>   1 file changed, 20 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
> index 9bb31f66db85..cdb31679f419 100644
> --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> @@ -1727,10 +1727,14 @@ static void
>   pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)

comment on current code: using u8 for vec seems dubious

>   {
>   #ifdef PM8001_USE_MSIX
> -	u32 mask;
> -	mask = (u32)(1 << vec);
> -
> -	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
> +	if (vec < 32) {
> +		/* vectors 0 - 31 */

nit: I doubt the use of these sort of comments. I mean, a check for vec 
< 32 makes it pretty obvious

> +		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
> +	} else {
> +		/* vectors 32 - 63 */
> +		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
> +			    1U << (vec - 32));
> +	}
>   	return;
>   #endif
>   	pm80xx_chip_intx_interrupt_enable(pm8001_ha);
> @@ -1746,12 +1750,18 @@ static void
>   pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
>   {
>   #ifdef PM8001_USE_MSIX
> -	u32 mask;
> -	if (vec == 0xFF)
> -		mask = 0xFFFFFFFF;
> -	else
> -		mask = (u32)(1 << vec);
> -	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
> +	if (vec == 0xFF) {
> +		/* disable all vectors 0-31, 32-63 */
> +		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
> +		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
> +	} else if (vec < 32) {
> +		/* vectors 0 - 31 */
> +		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
> +	} else {
> +		/* vectors 32 - 63 */
> +		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
> +			    1U << (vec - 32));
> +	}
>   	return;
>   #endif
>   	pm80xx_chip_intx_interrupt_disable(pm8001_ha);

RE: [PATCH v3 2/2] scsi: pm80xx: enable upper inbound, outbound queues

[Ajish.Koshy]

Thanks John for your comments here.
Will do it in v4.

> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> On 08/04/2022 09:05, Ajish Koshy wrote:
> > Executing driver on servers with more than 32 CPUs were faced with
> > command timeouts. This is because we were not geting completions for
> > commands submitted on IQ32 - IQ63.
> >
> > Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in
> > the MPI main configuration table.
> >
> > Added 500ms delay after successful MPI initialization as mentioned in
> > controller datasheet.
> >
> > Signed-off-by: Ajish Koshy <Ajish.Koshy@microchip.com>
> > Signed-off-by: Viswas G <Viswas.G@microchip.com>
> > Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported
> > queues")
> > Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
> > ---
> >   drivers/scsi/pm8001/pm80xx_hwi.c | 6 ++++++
> >   1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c
> > b/drivers/scsi/pm8001/pm80xx_hwi.c
> > index cdb31679f419..71b6cc4b9420 100644
> > --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> > +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> > @@ -766,6 +766,10 @@ static void init_default_table_values(struct
> pm8001_hba_info *pm8001_ha)
> >       pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       =
> 0x01;
> >       pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
> >
> > +     /* Enable higher IQs and OQs, 32 to 63, bit 16 */
> > +     if (pm8001_ha->max_q_num > 32)
> > +             pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
> > +                                                     1 << 16;
> >       /* Disable end to end CRC checking */
> >       pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
> >
> > @@ -1027,6 +1031,8 @@ static int mpi_init_check(struct
> pm8001_hba_info *pm8001_ha)
> >       if (0x0000 != gst_len_mpistate)
> >               return -EBUSY;
> >
> > +     msleep(500);
> 
> Personally I think you should mention where this 500ms value comes from
>   (the datasheet), as it is not arbitrary

OK.

> 
> The change looks ok apart from that
> 
> > +
> >       return 0;
> >   }
> >