* [PATCH] serial:ifx6x60:SPI header is decoded incorrectly
@ 2012-11-06 3:13 chao bi
2012-11-06 9:42 ` Alan Cox
0 siblings, 1 reply; 2+ messages in thread
From: chao bi @ 2012-11-06 3:13 UTC (permalink / raw)
To: alan; +Cc: linux-serial, richardx.r.gorby, jun.d.chen
This patch is to correct the bit mapping of "MORE" and "CTS" in SPI frame header.
Per SPI protocol, SPI header is encoded with length of 4 byte, which is defined
as below:
bit 0 ~ 11: current data size;
bit 12: "MORE" bit;
bit 13: reserve
bit 14 ~ 15: reserve
bit 16 ~ 27: next data size
bit 28: RI
bit 29: DCD
bit 30: CTS/RTS
bit 31: DSR/DTR
According to above SPI header structure, the bit mapping of "MORE" and "CTS" is
incorrect in function ifx_spi_decode_spi_header();
cc: Chen Jun <jun.d.chen@intel.com>
Signed-off-by: channing <chao.bi@intel.com>
---
drivers/tty/serial/ifx6x60.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
index 5b9bc19..60e767f 100644
--- a/drivers/tty/serial/ifx6x60.c
+++ b/drivers/tty/serial/ifx6x60.c
@@ -64,8 +64,8 @@
#include "ifx6x60.h"
#define IFX_SPI_MORE_MASK 0x10
-#define IFX_SPI_MORE_BIT 12 /* bit position in u16 */
-#define IFX_SPI_CTS_BIT 13 /* bit position in u16 */
+#define IFX_SPI_MORE_BIT 4 /* bit position in u8 */
+#define IFX_SPI_CTS_BIT 6 /* bit position in u8 */
#define IFX_SPI_MODE SPI_MODE_1
#define IFX_SPI_TTY_ID 0
#define IFX_SPI_TIMEOUT_SEC 2
--
1.7.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] serial:ifx6x60:SPI header is decoded incorrectly
2012-11-06 3:13 [PATCH] serial:ifx6x60:SPI header is decoded incorrectly chao bi
@ 2012-11-06 9:42 ` Alan Cox
0 siblings, 0 replies; 2+ messages in thread
From: Alan Cox @ 2012-11-06 9:42 UTC (permalink / raw)
To: chao bi; +Cc: alan, linux-serial, richardx.r.gorby, jun.d.chen
On Tue, 06 Nov 2012 11:13:59 +0800
chao bi <chao.bi@intel.com> wrote:
>
> This patch is to correct the bit mapping of "MORE" and "CTS" in SPI frame header.
> Per SPI protocol, SPI header is encoded with length of 4 byte, which is defined
> as below:
> bit 0 ~ 11: current data size;
> bit 12: "MORE" bit;
> bit 13: reserve
> bit 14 ~ 15: reserve
> bit 16 ~ 27: next data size
> bit 28: RI
> bit 29: DCD
> bit 30: CTS/RTS
> bit 31: DSR/DTR
>
> According to above SPI header structure, the bit mapping of "MORE" and "CTS" is
> incorrect in function ifx_spi_decode_spi_header();
>
> cc: Chen Jun <jun.d.chen@intel.com>
> Signed-off-by: channing <chao.bi@intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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