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From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
	basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
	mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	tianfei.zhang@intel.com, corbet@lwn.net,
	gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
	jirislaby@kernel.org, geert+renesas@glider.be,
	andriy.shevchenko@linux.intel.com,
	niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
	macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts
Date: Tue,  6 Sep 2022 12:04:25 -0700	[thread overview]
Message-ID: <20220906190426.3139760-5-matthew.gerlach@linux.intel.com> (raw)
In-Reply-To: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com>

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Define and use a DFHv1 parameter to add generic support for MSIX
interrupts for DFL devices.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 drivers/fpga/dfl.c  | 59 +++++++++++++++++++++++++++++++++------------
 include/linux/dfl.h | 13 ++++++++++
 2 files changed, 57 insertions(+), 15 deletions(-)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index b9aae85ba930..17f704dc8483 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -941,25 +941,11 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
 	void __iomem *base = binfo->ioaddr + ofst;
 	unsigned int i, ibase, inr = 0;
 	enum dfl_id_type type;
-	int virq;
+	int virq, off;
 	u64 v;
 
 	type = feature_dev_id_type(binfo->feature_dev);
 
-	/*
-	 * Ideally DFL framework should only read info from DFL header, but
-	 * current version DFL only provides mmio resources information for
-	 * each feature in DFL Header, no field for interrupt resources.
-	 * Interrupt resource information is provided by specific mmio
-	 * registers of each private feature which supports interrupt. So in
-	 * order to parse and assign irq resources, DFL framework has to look
-	 * into specific capability registers of these private features.
-	 *
-	 * Once future DFL version supports generic interrupt resource
-	 * information in common DFL headers, the generic interrupt parsing
-	 * code will be added. But in order to be compatible to old version
-	 * DFL, the driver may still fall back to these quirks.
-	 */
 	if (type == PORT_ID) {
 		switch (fid) {
 		case PORT_FEATURE_ID_UINT:
@@ -981,6 +967,28 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
 		}
 	}
 
+	if (fid != FEATURE_ID_AFU && fid != PORT_FEATURE_ID_ERROR &&
+	    fid != PORT_FEATURE_ID_UINT && fid != FME_FEATURE_ID_GLOBAL_ERR) {
+		v = readq(base);
+		v = FIELD_GET(DFH_VERSION, v);
+
+		if (v == 1) {
+			v =  readq(base + DFHv1_CSR_SIZE_GRP);
+			if (FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, v)) {
+				off = dfl_find_param(base + DFHv1_PARAM_HDR, ofst,
+						     DFHv1_PARAM_ID_MSIX);
+				if (off >= 0) {
+					ibase = readl(base + DFHv1_PARAM_HDR +
+						      off + DFHv1_PARAM_MSIX_STARTV);
+					inr = readl(base + DFHv1_PARAM_HDR +
+						    off + DFHv1_PARAM_MSIX_NUMV);
+					dev_dbg(binfo->dev, "%s start %d num %d fid 0x%x\n",
+						__func__, ibase, inr, fid);
+				}
+			}
+		}
+	}
+
 	if (!inr) {
 		*irq_base = 0;
 		*nr_irqs = 0;
@@ -1879,6 +1887,27 @@ long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
 }
 EXPORT_SYMBOL_GPL(dfl_feature_ioctl_set_irq);
 
+int dfl_find_param(void __iomem *base, resource_size_t max, int param)
+{
+	int off = 0;
+	u64 v, next;
+
+	while (off < max) {
+		v = readq(base + off);
+		if (param == FIELD_GET(DFHv1_PARAM_HDR_ID, v))
+			return off;
+
+		next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v);
+		if (!next)
+			break;
+
+		off += next;
+	}
+
+	return -ENOENT;
+}
+EXPORT_SYMBOL_GPL(dfl_find_param);
+
 static void __exit dfl_fpga_exit(void)
 {
 	dfl_chardev_uinit();
diff --git a/include/linux/dfl.h b/include/linux/dfl.h
index 61bcf20c1bc8..5652879ab48e 100644
--- a/include/linux/dfl.h
+++ b/include/linux/dfl.h
@@ -69,6 +69,10 @@
 #define DFHv1_PARAM_HDR_VERSION		GENMASK_ULL(31, 16) /* Version Param */
 #define DFHv1_PARAM_HDR_NEXT_OFFSET	GENMASK_ULL(63, 32) /* Offset of next Param */
 
+#define DFHv1_PARAM_ID_MSIX	0x1
+#define DFHv1_PARAM_MSIX_STARTV	0x8
+#define DFHv1_PARAM_MSIX_NUMV	0xc
+
 /**
  * enum dfl_id_type - define the DFL FIU types
  */
@@ -142,4 +146,13 @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv);
 	module_driver(__dfl_driver, dfl_driver_register, \
 		      dfl_driver_unregister)
 
+/*
+ * dfl_find_param() - find the offset of the given parameter
+ * @base: base pointer to start of dfl parameters in DFH
+ * @max: maximum offset to search
+ * @param: id of dfl parameter
+ *
+ * Return: positive offset on success, negative error code otherwise.
+ */
+int dfl_find_param(void __iomem *base, resource_size_t max, int param);
 #endif /* __LINUX_DFL_H */
-- 
2.25.1


  parent reply	other threads:[~2022-09-06 19:04 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 19:04 [PATCH v1 0/5] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-06 20:08   ` Andy Shevchenko
2022-09-07 19:15     ` matthew.gerlach
2022-09-11  9:57   ` Xu Yilun
2022-09-11 16:06     ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 2/5] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-06 20:07   ` Andy Shevchenko
2022-09-07 21:01     ` matthew.gerlach
2022-09-07  5:08   ` Greg KH
2022-09-11 15:40     ` matthew.gerlach
2022-09-11 17:54       ` Geert Uytterhoeven
2022-09-11  8:04   ` Xu Yilun
2022-09-11 16:13     ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-11  8:27   ` Xu Yilun
2022-09-11 16:21     ` matthew.gerlach
2022-09-06 19:04 ` matthew.gerlach [this message]
2022-09-06 20:15   ` [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts Andy Shevchenko
2022-09-07 21:37     ` matthew.gerlach
2022-09-08 11:04       ` Andy Shevchenko
2022-09-08 17:34         ` matthew.gerlach
2022-09-08 17:51           ` Andy Shevchenko
2022-09-08 19:28           ` Geert Uytterhoeven
2022-09-08 20:21             ` matthew.gerlach
2022-09-11  9:06   ` Xu Yilun
2022-09-06 19:04 ` [PATCH v1 5/5] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-06 20:24   ` Andy Shevchenko
2022-09-08 18:27     ` matthew.gerlach
2022-09-08 21:16       ` Andy Shevchenko
2022-09-11 15:56         ` matthew.gerlach
2022-09-12 10:54           ` Andy Shevchenko
2022-09-11  9:41   ` Xu Yilun
2022-09-12 15:29     ` matthew.gerlach
2022-09-13  2:48       ` Xu Yilun

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