Re: [PATCH v2] serial: 8250 dw: clear FIFO before writting LCR

[Greg KH <gregkh@linuxfoundation.org>]

On Tue, Aug 19, 2025 at 12:13:14PM -0700, adriana@arista.com wrote:
> The USR register may report that UART is busy even if TX/TX FIFO is already
> empty so we will loop until all USR[0] (UART busy status) is cleared and USR[1]
> TX FIFO is empty (RX FIFO bits should be 0 in this case).
> Keeping the same timeout of 20ms as measurements with the 9600 baud when
> the console was busy it took max 1.9ms to get the UART free state.
> 
> ---
> Changes in v2:
> - Updated the mailing list.
> 
> Signed-off-by: Adriana Nicolae <adriana@arista.com>
> ---

Your signed-off-by needs to be above the --- line.  Take a look at a few
of the thousands of examples on the mailing list for how to get this
right.

One tiny comment:

> diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
> index 9c007a106330..8386436b813f 100644
> --- a/include/uapi/linux/serial_core.h
> +++ b/include/uapi/linux/serial_core.h
> @@ -231,6 +231,9 @@
>  /* Sunplus UART */
>  #define PORT_SUNPLUS	123
>  
> +/* Synopsys DesignWare */
> +#define PORT_DWAPB		124

Why do you need to export this value to userspace?

thanks,

greg k-h