[PATCH] serial: 8250: handle ixp4xx register endianness correctly

[PATCH] serial: 8250: handle ixp4xx register endianness correctly

[Linus Walleij]

From: Arnd Bergmann <arnd@arndb.de>

Unlike modern SoCs that just work in both big-endian and little-endian
mode using the readl()/writel() or readb()/writeb() accessors, the
internal registers on ixp4xx behave like native-endian 32-bit registers
in both modes, which requires adjusting the register address
when using 8-bit access.

The existing dts files are written for big-endian kernels and 8-bit
access, which does not work with little-endian kernels.

Add a quirk that makes the 8250 OF driver:

1. Mask off any hardcoded offset.
2. Add the += 3 offset if and only if we are running on big endian.

This should work in all combinations of big-endian and little-endian
kernels with either variant of the DTS file.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[linusw@kernel.org: Modified to just play with the offset]
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 drivers/tty/serial/8250/8250_of.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
index 81644d40b09a..859dff3af0eb 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -122,6 +122,17 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
 	if (ret)
 		goto err_pmruntime;
 
+	if (IS_ENABLED(CONFIG_CPU_XSCALE) && type == PORT_XSCALE) {
+		/*
+		 * Adjust for BE32 register accesses: drop any hardcoded
+		 * address for the big endian byte target, add it explicitly
+		 * if running on BE32.
+		 */
+		port->mapbase &= ~3;
+		if (IS_ENABLED(CONFIG_CPU_ENDIAN_BE32))
+			port->mapbase += 3;
+	}
+
 	/* Get clk rate through clk driver if present */
 	if (!port->uartclk) {
 		struct clk *bus_clk;

---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260709-ixp4xx-serial-hackfix-c5cd90dcca93

Best regards,
--  
Linus Walleij <linusw@kernel.org>

Re: [PATCH] serial: 8250: handle ixp4xx register endianness correctly

[Arnd Bergmann]

On Thu, Jul 9, 2026, at 01:05, Linus Walleij wrote:
> @@ -122,6 +122,17 @@ static int of_platform_serial_setup(struct 
> platform_device *ofdev,
>  	if (ret)
>  		goto err_pmruntime;
> 
> +	if (IS_ENABLED(CONFIG_CPU_XSCALE) && type == PORT_XSCALE) {
> +		/*
> +		 * Adjust for BE32 register accesses: drop any hardcoded
> +		 * address for the big endian byte target, add it explicitly
> +		 * if running on BE32.
> +		 */
> +		port->mapbase &= ~3;
> +		if (IS_ENABLED(CONFIG_CPU_ENDIAN_BE32))
> +			port->mapbase += 3;
> +	}

I tried to adjust my original patch the same way yesterday, but
got stuck after I noticed that a similar change is needed
for the earlycon side that runs before of_platform_serial_setup().

I think I've come up with a simple enough fix, essentially putting
the same change in a second location, see below.

The other thing I realized is that I had the incorrect
"port->regshift = 0" in my broken patch at first, which
would mean that UPIO_MEM32 couldn't work either even if
the hardware could do it after all.

     Arnd

diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c
index dc0371857ecb..bfe8232e0ebb 100644
--- a/drivers/tty/serial/8250/8250_early.c
+++ b/drivers/tty/serial/8250/8250_early.c
@@ -177,16 +177,24 @@ OF_EARLYCON_DECLARE(ns16550a, "ns16550a", early_serial8250_setup);
 OF_EARLYCON_DECLARE(uart, "nvidia,tegra20-uart", early_serial8250_setup);
 OF_EARLYCON_DECLARE(uart, "snps,dw-apb-uart", early_serial8250_setup);
 
-static int __init early_serial8250_rs2_setup(struct earlycon_device *device,
+static int __init early_serial8250_xscale_setup(struct earlycon_device *device,
 					     const char *options)
 {
+	/*
+	 * Adjust for BE32 register accesses: drop any hardcoded
+	 * address for the big endian byte target, add it explicitly
+	 * if running on BE32.
+	 */
+	port->membase &= ~3;
+	if (IS_ENABLED(CONFIG_CPU_ENDIAN_BE32))
+		port->membase += 3;
 	device->port.regshift = 2;
 
 	return early_serial8250_setup(device, options);
 }
-OF_EARLYCON_DECLARE(uart, "intel,xscale-uart", early_serial8250_rs2_setup);
-OF_EARLYCON_DECLARE(uart, "mrvl,mmp-uart", early_serial8250_rs2_setup);
-OF_EARLYCON_DECLARE(uart, "mrvl,pxa-uart", early_serial8250_rs2_setup);
+OF_EARLYCON_DECLARE(uart, "intel,xscale-uart", early_serial8250_xscale_setup);
+OF_EARLYCON_DECLARE(uart, "mrvl,mmp-uart", early_serial8250_xscale_setup);
+OF_EARLYCON_DECLARE(uart, "mrvl,pxa-uart", early_serial8250_xscale_setup);
 
 #ifdef CONFIG_SERIAL_8250_OMAP