Re: [PATCH v2 RESEND 2/2] serial: sc16is7xx: reduce TX refill rate with half-FIFO trigger

[sashiko-bot@kernel.org]

> With the TX trigger set to 8 free spaces, THRI is generated roughly once
> per 8 transmitted bytes. At 115200 baud 8N1, this corresponds to
> approximately 0.7 ms between TX refill events.
> 
> Set the TX trigger to 32 free spaces via TLR[3:0]. This makes each refill
> larger and reduces the refill rate by about 4x. At 115200 baud 8N1, the
> refill cadence becomes approximately 2.8 ms.
> 
> The trade-off is that the time-to-empty after THRI asserts is reduced
> from 56 to 32 byte times. The fresh-TXLVL refill loop fills the hardware
> TX FIFO strictly below whichever trigger is selected. This patch changes
> only the refill frequency and the associated latency trade-off.
> 
> With the two TX gap fixes applied in both configurations, changing the
> trigger from 8 to 32 free spaces produced the following median values
> [ ... ]
> the TCR setup immediately preceding the TLR write.
> 
> Reviewed-by: Joachim Knorr <joachim.knorr@ziehl-abegg.de>
> Link: https://lore.kernel.org/linux-serial/20260623112225.82386-3-paultyson.mbewe@ziehl-abegg.de/
> Signed-off-by: Paul Mbewe <paultyson.mbewe@ziehl-abegg.de>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260930145628.566535-1-paultyson.mbewe@ziehl-abegg.de?part=2