Re: [PATCH v2 RESEND 1/2] serial: sc16is7xx: refill TX FIFO below trigger using fresh TXLVL

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] serial: sc16is7xx: unbounded tx refill loop starves rx irqs
--

commit a658261936f3762a047ddfec6aa9737edd0babeb
Author: Paul Mbewe <paultyson.mbewe@ziehl-abegg.de>

serial: sc16is7xx: refill TX FIFO below trigger using fresh TXLVL

This commit changes the driver to continually refill the hardware TX FIFO
by polling the available space (TXLVL) until the hardware reports a level
strictly below the trigger.

Link: https://lore.kernel.org/linux-serial/20260623112225.82386-3-paultyson.mbewe@ziehl-abegg.de/

> diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
> index fa7805d2cde23..1f7e98c2b5709 100644
> --- a/drivers/tty/serial/sc16is7xx.c
> +++ b/drivers/tty/serial/sc16is7xx.c

[ ... ]

> @@ -687,7 +698,14 @@ static void sc16is7xx_handle_tx(struct uart_port *port)
>  
>  		sc16is7xx_fifo_write(port, tail, to_send);
>  		uart_xmit_advance(port, to_send);
> -		txlen -= to_send;
> +
> +		if (kfifo_is_empty(&tport->xmit_fifo))
> +			break;
> +
> +		/* Refill below the trigger to enable the next THRI crossing. */
> +		txlen = sc16is7xx_txlvl(port);
> +		if (txlen < SC16IS7XX_TX_TRIGGER_LEVEL)
> +			break;
>  	}

[Severity: High]
Could updating the loop boundary directly from the hardware without an
iteration limit cause an unbounded loop that starves RX interrupts?

If the UART baud rate exceeds the I2C or SPI bus throughput (for example,
921600 baud over 400kHz I2C), the hardware TX FIFO will drain faster than
sc16is7xx_fifo_write() can fill it over the bus.

In this scenario, the fresh txlvl reading remains high, meaning the loop exit
condition fails to trigger. This allows the loop to spin continuously until
the 4KB xmit_fifo is completely emptied.

Because sc16is7xx_handle_tx() is executed in the shared IRQ handling thread,
spinning here completely blocks the thread while it flushes the xmit_fifo. RX
interrupts cannot be serviced during this time, which could cause the 64-byte
hardware RX FIFO to rapidly overrun, resulting in data loss.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260930145628.566535-1-paultyson.mbewe@ziehl-abegg.de?part=1