Re: [PATCH 1/3] serial: 8250: Identify Renesas RZ/V2M 16750 UART

["Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>]

On Thu, 9 Feb 2023, Biju Das wrote:

> Add identification support for RZ/V2M 16750 UART.
> 
> Currently, RZ/V2M UART is detected as 16550A instead of 16750.
> "a4040000.serial: ttyS0 at MMIO 0xa4040000 (irq = 14, base_baud = 3000000)
> is a 16550A"
> 
> After adding identification support, it is detected as
> "a4040000.serial: ttyS0 at MMIO 0xa4040000 (irq = 24, base_baud = 3000000)
> is a Renesas RZ/V2M 16750".
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/tty/serial/8250/8250_port.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
> index e61753c295d5..e4b205e3756b 100644
> --- a/drivers/tty/serial/8250/8250_port.c
> +++ b/drivers/tty/serial/8250/8250_port.c
> @@ -111,6 +111,15 @@ static const struct serial8250_config uart_config[] = {
>  		.rxtrig_bytes	= {1, 16, 32, 56},
>  		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
>  	},
> +	[PORT_16750] = {
> +		.name		= "Renesas RZ/V2M 16750",
> +		.fifo_size	= 64,
> +		.tx_loadsz	= 64,
> +		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
> +				  UART_FCR7_64BYTE,
> +		.rxtrig_bytes	= {1, 16, 32, 56},
> +		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
> +	},

Eh, how can you reuse [PORT_16750] again in the initializer like that?

-- 
 i.

>  	[PORT_STARTECH] = {
>  		.name		= "Startech",
>  		.fifo_size	= 1,
> @@ -1142,6 +1151,24 @@ static void autoconfig_16550a(struct uart_8250_port *up)
>  		return;
>  	}
>  
> +	/*
> +	 * No EFR.  Try to detect a Renesas RZ/V2M 16750, which only sets bit 5
> +	 * of the IIR when 64 byte FIFO mode is enabled.
> +	 * Try setting/clear bit5 of FCR.
> +	 */
> +	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
> +	status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
> +
> +	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
> +	status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
> +
> +	if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
> +	    status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
> +		up->port.type = PORT_16750;
> +		up->capabilities |= UART_CAP_AFE;
> +		return;
> +	}
> +
>  	/*
>  	 * Try writing and reading the UART_IER_UUE bit (b6).
>  	 * If it works, this is probably one of the Xscale platform's
>