Re: [PATCH v2 00/11] riscv: Add initial support for Anlogic DR1V90

From: Troy Mitchell <troy.mitchell@linux.dev>
To: "fushan.zeng" <fushan.zeng@anlogic.com>, junhui.liu@pigmoral.tech
Cc: alex@ghiti.fr, anup@brainfault.org, aou@eecs.berkeley.edu,
	conor+dt@kernel.org, conor@kernel.org, daniel.lezcano@linaro.org,
	devicetree@vger.kernel.org, gregkh@linuxfoundation.org,
	jirislaby@kernel.org, krzk+dt@kernel.org,
	krzysztof.kozlowski@linaro.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
	palmer@dabbelt.com, palmer@sifive.com, paul.walmsley@sifive.com,
	robh@kernel.org, samuel.holland@sifive.com, tglx@linutronix.de,
	Troy Mitchell <troy.mitchell@linux.dev>
Subject: Re: [PATCH v2 00/11] riscv: Add initial support for Anlogic DR1V90
Date: Thu, 25 Sep 2025 11:49:12 +0800	[thread overview]
Message-ID: <aNS7uMHC4iTDHel4@LT-Guozexi> (raw)
In-Reply-To: <20250925030650.35694-1-fushan.zeng@anlogic.com>

On Thu, Sep 25, 2025 at 11:06:50AM +0800, fushan.zeng wrote:
> On Mon, 22 Sep 2025 20:46:30 +0800, Junhui Liu wrote:
> > This patch series introduces initial support for the Anlogic DR1V90 SoC
> > [1] and the Milianke MLKPAI-FS01 [2] board.
> > 
> > The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
> > UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
> > programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
> > the first platforms based on this SoC, with UART1 routed to a Type-C
> > interface for console access.
> > 
> > Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
> > and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
> > U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
> > to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
> > overlap if using vendor's OpenSBI.
> > 
> > Notice: A "no4lvl" bootarg or dependency patch [5] is currently required
> > for successful boot on the DR1V90 platform, since the SoC hangs if the
> > kernel attempts to use unsupported 4-level or 5-level paging modes.
> 
> Thanks first.
> Anloigc already has the open source SDK at https://gitee.com/anlogic/sdk,
I think very few people actually use Gitee around here.

> and will submit it to mainline at suitable time.
> It is better that anlogic SOCs are long term maintained and supported
> by Anlogic officially in mainline and for customers.
> The code should be a full feature version after lots of tests, not the
> modified and simplified version from Anlogic open source.
I understand how you feel:
You want to be responsible for both the code and the customers.

> And we hope that there won't be two different versions code of anlogic SOCs,
> it may confuse customers.
This is almost impossible.
Mainline means simple, clear, compliant, fully open source.
Some features, like GPU, are nearly impossible to fully upstream.
Vendor versions are complex and implement full hardware features.
It also seems you expect only official folks to handle this,
which would take significant effort to maintain,
perhaps even requiring dedicated personnel.

                - Troy
> 
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