From: "Bin Meng" <bmeng@tinylab.org>
To: "Sergey Matyukevich" <geomatsi@gmail.com>
Cc: linux-kernel <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
linux-serial <linux-serial@vger.kernel.org>,
aou <aou@eecs.berkeley.edu>,
"catalin.marinas" <catalin.marinas@arm.com>,
gregkh <gregkh@linuxfoundation.org>,
jirislaby <jirislaby@kernel.org>, palmer <palmer@dabbelt.com>,
"paul.walmsley" <paul.walmsley@sifive.com>,
linux <linux@armlinux.org.uk>, will <will@kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver
Date: Fri, 23 Dec 2022 09:11:42 +0000 [thread overview]
Message-ID: <em1edb1bed-77fc-4deb-9de1-7f35bc962d0e@a9022134.com> (raw)
In-Reply-To: <Y6S4v7t0n0BI1P7d@curiosity>
Hi Sergey,
On 2022/12/23 4:06:23, "Sergey Matyukevich" <geomatsi@gmail.com> wrote:
>Hi Bin,
>
>> RISC-V semihosting spec [1] is built on top of the existing Arm one;
>> we can add RISC-V earlycon semihost driver easily.
>>
>> This series refactors the existing driver a little bit, to move smh_putc()
>> variants in respective arch's semihost.h, then we can implement RISC-V's
>> version in the riscv arch directory.
>>
>> Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1]
>>
>> Changes in v3:
>> - add #ifdef in the header to prevent from multiple inclusion
>> - add forward-declare struct uart_port
>> - add a Link tag in the commit message
>>
>> Changes in v2:
>> - new patch: "serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h"
>> - Move the RISC-V implementation to semihost.h
>>
>> Bin Meng (3):
>> serial: earlycon-arm-semihost: Move smh_putc() variants in respective
>> arch's semihost.h
>> riscv: Implement semihost.h for earlycon semihost driver
>> serial: Rename earlycon semihost driver
>>
>> arch/arm/include/asm/semihost.h | 30 +++++++++++++++++++
>> arch/arm64/include/asm/semihost.h | 24 +++++++++++++++
>> arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++
>> drivers/tty/serial/Kconfig | 14 ++++-----
>> drivers/tty/serial/Makefile | 2 +-
>> ...con-arm-semihost.c => earlycon-semihost.c} | 25 +---------------
>> 6 files changed, 89 insertions(+), 32 deletions(-)
>> create mode 100644 arch/arm/include/asm/semihost.h
>> create mode 100644 arch/arm64/include/asm/semihost.h
>> create mode 100644 arch/riscv/include/asm/semihost.h
>> rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (57%)
>
>Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
>
>Applied the patches on top of Linux 6.1 and tested earlycon logs from
>RISC-V target in OpenOCD.
>
Thanks for your testing!
Regards,
Bin
next prev parent reply other threads:[~2022-12-23 9:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-09 15:04 [PATCH v3 0/3] serial: Add RISC-V support to the earlycon semihost driver Bin Meng
2022-12-09 15:04 ` [PATCH v3 1/3] serial: earlycon-arm-semihost: Move smh_putc() variants in respective arch's semihost.h Bin Meng
2022-12-09 15:04 ` [PATCH v3 2/3] riscv: Implement semihost.h for earlycon semihost driver Bin Meng
2022-12-09 15:04 ` [PATCH v3 3/3] serial: Rename " Bin Meng
2022-12-21 15:51 ` [PATCH v3 0/3] serial: Add RISC-V support to the " Bin Meng
2022-12-21 16:09 ` gregkh
2022-12-22 20:06 ` Sergey Matyukevich
2022-12-23 9:11 ` Bin Meng [this message]
2022-12-29 16:22 ` Palmer Dabbelt
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