Questions about the interrupt controller

Questions about the interrupt controller

[Francis Moreau]

Hello,

I read the sh4 core peripherals manual avalaible on renesas web site
(BTW do you know other 'good' documentations on the sh4 architecture ?)
in order to understand how the 'intc' works.

My question is: are there any examples in the linux kernel which use the
IRL interrupts when *not* configured as 4 independent interrupt requests ?

Do such interrupts need to use make_imask_irq() ?

The documentation says: "Other compatible interrupt controllers can be
cascaded with INTC.". Where can I find some details about that ?

Thanks !
-- 
Francis

Re: Questions about the interrupt controller

[Manuel Lauss]

Francis Moreau wrote:
> Hello,
> 
> I read the sh4 core peripherals manual avalaible on renesas web site
> (BTW do you know other 'good' documentations on the sh4 architecture ?)
> in order to understand how the 'intc' works.
> 
> My question is: are there any examples in the linux kernel which use the
> IRL interrupts when *not* configured as 4 independent interrupt requests ?

The platform I'm working on does that.  A CPLD with 15 IRQ sources uses 
the 4 IRL lines to signal them (low-active 4-bit "bus" if you will).

> Do such interrupts need to use make_imask_irq() ?

Again, I can only tell for my SH7760 platform. You need to register your 
own irq_chip with mask/unmask/mask_ack callbacks. On the SH7760, the 
IRLs trigger as vectors 0-15, and one has to provide external logic to
do the irq masking/acking. SH7780 and newer IIRC provide an INTC 
register for that.

This is code I use:

/* CPU MODULE CPLD IRQ "CONTROLLER" */
static void exm7760_en_cpld_irq(unsigned int irq)
{
         unsigned short val = ctrl_inw(EXM7760_CPLD_MASK) & ~(1 << irq);
         ctrl_outw(val, EXM7760_CPLD_MASK);
}

static void exm7760_dis_cpld_irq(unsigned int irq)
{
         unsigned short val = ctrl_inw(EXM7760_CPLD_MASK) | (1 << irq);
         ctrl_outw(val, EXM7760_CPLD_MASK);
}

static struct irq_chip exm7760_cpld_chip __read_mostly = {
         .name           = "CPLD",
         .unmask         = exm7760_en_cpld_irq,
         .mask           = exm7760_dis_cpld_irq,
         .mask_ack       = exm7760_dis_cpld_irq,
};

static void __init exm7760_init_cpld_irq(void)
{
         int i;
         for (i = 0; i < EXM7760_CPLD_IRQNUM; i++)  {
                 set_irq_chip_and_handler_name(i, &exm7760_cpld_chip,
                                 handle_level_irq, "level");
                 set_irq_chip_data(i, NULL);
         }
}


> The documentation says: "Other compatible interrupt controllers can be
> cascaded with INTC.". Where can I find some details about that ?

have a look at set_irq_chained_handler() function, for example:

static struct irq_chip exm7760_pcmcia_chip __read_mostly = {
         .name           = "CPLD-PCMCIA",
         .unmask         = exm7760_en_cardirq,
         .mask           = exm7760_dis_cardirq,
         .mask_ack       = exm7760_dis_cardirq,
};

static void exm7760_pcmcia_chain_handler(unsigned int irq,
                                          struct irq_desc *desc)
{
         unsigned short cfctl = ctrl_inw(EXM7760_CPLD_CFCTL);
         if ((cfctl & CFCTL_RDY) = 0)
                 generic_handle_irq(EXM7760_CF_CARD0_IRQ);

         if ((cfctl & (CFCTL_RDY << CFCTL_SOCK1_SHIFT)) = 0)
                 generic_handle_irq(EXM7760_CF_CARD1_IRQ);
}

static void __init exm7760_init_pcmcia_irq(void)
{
         set_irq_chip_and_handler_name(EXM7760_CF_CARD0_IRQ,
                       &exm7760_pcmcia_chip, handle_level_irq, "level");
         set_irq_chip_and_handler_name(EXM7760_CF_CARD1_IRQ,
                       &exm7760_pcmcia_chip, handle_level_irq, "level");

         set_irq_chained_handler(EXM7760_CF_IRQ,
                                 exm7760_pcmcia_chain_handler);
}


Best regards,
	Manuel Lauss

Re: Questions about the interrupt controller

[Francis Moreau]

Hello Manuel,

On Fri, Feb 29, 2008 at 4:32 PM, Manuel Lauss
<mano@roarinelk.homelinux.net> wrote:
>  Again, I can only tell for my SH7760 platform. You need to register your
>  own irq_chip with mask/unmask/mask_ack callbacks. On the SH7760, the
>  IRLs trigger as vectors 0-15, and one has to provide external logic to
>  do the irq masking/acking. SH7780 and newer IIRC provide an INTC
>  register for that.
>
>  This is code I use:
>

[snip]

But couldn't you use make_imask_irq() instead ?

>  > The documentation says: "Other compatible interrupt controllers can be
>  > cascaded with INTC.". Where can I find some details about that ?
>
>  have a look at set_irq_chained_handler() function, for example:
>

[snip]

Actually I'm wondering what does 'compatible' mean.... ?

Thanks
-- 
Francis

Re: Questions about the interrupt controller

[Manuel Lauss]

Francis Moreau wrote:
> Hello Manuel,
> 
> On Fri, Feb 29, 2008 at 4:32 PM, Manuel Lauss
> <mano@roarinelk.homelinux.net> wrote:
>>  Again, I can only tell for my SH7760 platform. You need to register your
>>  own irq_chip with mask/unmask/mask_ack callbacks. On the SH7760, the
>>  IRLs trigger as vectors 0-15, and one has to provide external logic to
>>  do the irq masking/acking. SH7780 and newer IIRC provide an INTC
>>  register for that.
>>
>>  This is code I use:
>>
> 
> [snip]
> 
> But couldn't you use make_imask_irq() instead ?

Yes, that works too; at least for the IRL irqs if the source does not
have to be acked (CF cards).


>>  > The documentation says: "Other compatible interrupt controllers can be
>>  > cascaded with INTC.". Where can I find some details about that ?
>>
>>  have a look at set_irq_chained_handler() function, for example:
>>
> 
> [snip]
> 
> Actually I'm wondering what does 'compatible' mean.... ?

4 lines which are pulled low to signal IRQ condition and the ~bitmask of 
those 4 lines indicates the number of the irq to trigger?
Thats my understanding of how it works...

-- 
  ml.

Re: Questions about the interrupt controller

[Manuel Lauss]

I wrote:
>> But couldn't you use make_imask_irq() instead ?
> 
> Yes, that works too; at least for the IRL irqs if the source does not
> have to be acked (CF cards).

Now I'm not so sure about that. Paul or Magnus can probably give you
better advice.  I'm curious why you'd want to use IMASK?

-- 
  ml.

Re: Questions about the interrupt controller

[Manuel Lauss]

Manuel Lauss wrote:
>> But couldn't you use make_imask_irq() instead ?

Ah now I understand. You are talking about the 4 IMASK bits in the
SR register, right?  If yes then disregard all I wrote earlier.

I'm going to shut up now. ;-)

-- 
  ml.

Re: Questions about the interrupt controller

[Francis Moreau]

On Fri, Feb 29, 2008 at 6:20 PM, Manuel Lauss
<mano@roarinelk.homelinux.net> wrote:
> Francis Moreau wrote:
>  > But couldn't you use make_imask_irq() instead ?
>
>  Yes, that works too; at least for the IRL irqs if the source does not
>  have to be acked (CF cards).
>

What do you mean by "the source doesn't have to be acked" ?

The possible case where it couldn't be used is when the irqs are edge
triggered.

Another drawback is that we can't mask one single IRL irq but we have
to mask all IRQs whose priority are less than the IRL irq's priority,

>
>
>  >>  > The documentation says: "Other compatible interrupt controllers can be
>  >>  > cascaded with INTC.". Where can I find some details about that ?
>  >>
>  >>  have a look at set_irq_chained_handler() function, for example:
>  >>
>  >
>  > [snip]
>  >
>  > Actually I'm wondering what does 'compatible' mean.... ?
>
>  4 lines which are pulled low to signal IRQ condition and the ~bitmask of
>  those 4 lines indicates the number of the irq to trigger?
>  Thats my understanding of how it works...
>

Do you know any datasheets out there describing this ?

In the same vein, could you point out some good documents about the SH
architecture ? The ones available from Renesas web site aren't very good
IMHO

Thanks Manuel
-- 
Francis

Re: Questions about the interrupt controller

[Francis Moreau]

On Fri, Feb 29, 2008 at 6:35 PM, Manuel Lauss
<mano@roarinelk.homelinux.net> wrote:
> Manuel Lauss wrote:
>  >> But couldn't you use make_imask_irq() instead ?
>
>  Ah now I understand. You are talking about the 4 IMASK bits in the
>  SR register, right?  If yes then disregard all I wrote earlier.
>

Yes.

>  I'm going to shut up now. ;-)
>

Well what you wrote earlier is still usefull.

-- 
Francis

Re: Questions about the interrupt controller

[Manuel Lauss]

  > The possible case where it couldn't be used is when the irqs are edge
> triggered.
> 
> Another drawback is that we can't mask one single IRL irq but we have
> to mask all IRQs whose priority are less than the IRL irq's priority,

According to the SH7760 datasheet, the INTC compares the priority of 
_every_ interrupt (IRL, On-chip peripheral) to the IMASK register. If 
IRQ priority is HIGHER than the level set in IMASK then the interrupt is
accepted and the exception handler is invoked.

So no, I don't believen you can have a "sane" IRL irq handling scheme
only with IMASK irq chip.

>>  >>  > The documentation says: "Other compatible interrupt controllers can be
>>  >>  > cascaded with INTC.". Where can I find some details about that ?
>>  >>
>>  >>  have a look at set_irq_chained_handler() function, for example:
>>  >>
>>  >
>>  > [snip]
>>  >
>>  > Actually I'm wondering what does 'compatible' mean.... ?
>>
>>  4 lines which are pulled low to signal IRQ condition and the ~bitmask of
>>  those 4 lines indicates the number of the irq to trigger?
>>  Thats my understanding of how it works...
>>
> 
> Do you know any datasheets out there describing this ?

Take the SH7751/SH7760/SH7780 datasheets for example, it's described in 
the INTC chapter (Page 217 of the 7760 manual).

> In the same vein, could you point out some good documents about the SH
> architecture ? The ones available from Renesas web site aren't very good
> IMHO

Maybe ST has some manuals for their ST40 based parts (also SH4 variants)
on their site.

-- 
  ml.

Re: Questions about the interrupt controller

[Stuart MENEFY]

Manuel Lauss wrote:
>> In the same vein, could you point out some good documents about the SH
>> architecture ? The ones available from Renesas web site aren't very good
>> IMHO
> 
> Maybe ST has some manuals for their ST40 based parts (also SH4 variants)
> on their site.

There is some general information on the architecture and core at:
   http://www.st.com/mcu/modules.php?name=mcu&fileúmiliesdocs&famQ
but most of it is pretty old.

Most of the recent chip datasheets are only available under NDA, although
there is an old ST40RA datasheet available there.

Stuart