pirq settings for dual Athlon MPX system

pirq settings for dual Athlon MPX system

[Erik Barker]

Hi there,

I read through your document on pirq settings located at
http://www.linuxhq.com/kernel/v2.4/doc/i386/IO-APIC.txt.html but
unfortunately I'm still having a problem with IRQ's.

The problem is that I would like to have each device on its own IRQ
instead of some devices sharing IRQs. Here is a list of my current IRQ
layout:

RedHat Linux 7.2 kernel 2.4.18-pre8/2.4.18-pre8-ac5

           CPU0       CPU1       
  0:      10021       8687    IO-APIC-edge  timer
  1:          2          0    IO-APIC-edge  keyboard
  2:          0          0          XT-PIC  cascade
  5:        334        347   IO-APIC-level  eth0
  8:          0          1    IO-APIC-edge  rtc
  9:          0          0    IO-APIC-edge  acpi
 10:     129142     129730   IO-APIC-level  aic7xxx, eth1
 11:     380213     379892   IO-APIC-level  aic7xxx, eth2
NMI:          0          0 
LOC:      18650      18564 
ERR:          0
MIS:          0

Motherboard: Tyan Thunder K7X (AMD 760MPX)

The motherboard has 3 32-bit PCI slots and 2 64bit PCI. This system has
a total of 4 Nics... 2 onboard 3Com nics (1 which has been disabled) and
2 PCI 3Com Gig ethernet nics. The 2 Gig E Nics (eth1,eth2) are in the
64-bit slots. For some reason, the onboard adaptec controller (AIC-7899)
ALWAYS shares the IRQs with the Gig E Nics which is really annoying.
I've tried passing tons of parameters to grub in hopes that it would
separate the Adaptec channels (A,B) and the Nics but nothing seems to
change the IRQs at all. I've even considered trying to change the
built-in IRQ settings for both channels of the SCSI controller but can't
find any utils to do this. The motherboard has separate PCI buses for
64-bit hardware/slots and the 32-bit PCI slots.

Here is a snippet of my dmesg:

########### Snippet ################

Total of 2 processors activated (6127.61 BogoMIPS).
ENABLING IO-APIC IRQs
Setting 2 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 2 ... ok.
init IO_APIC IRQs
 IO-APIC (apicid-pin) 2-0, 2-22, 2-23 not connected.
..TIMER: vector=0x31 pin1=2 pin2=0
number of MP IRQ sources: 22.
number of IO-APIC #2 registers: 24.
testing the IO APIC.......................

IO APIC #2......
.... register #00: 02000000
.......    : physical APIC id: 02
.... register #01: 00170011
.......     : max redirection entries: 0017
.......     : PRQ implemented: 0
.......     : IO APIC version: 0011
.... register #02: 00000000
.......     : arbitration: 00
.... IRQ redirection table:
 NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:   
 00 000 00  1    0    0   0   0    0    0    00
 01 003 03  0    0    0   0   0    1    1    39
 02 003 03  0    0    0   0   0    1    1    31
 03 003 03  0    0    0   0   0    1    1    41
 04 003 03  0    0    0   0   0    1    1    49
 05 003 03  1    1    0   1   0    1    1    51
 06 003 03  0    0    0   0   0    1    1    59
 07 003 03  0    0    0   0   0    1    1    61
 08 003 03  0    0    0   0   0    1    1    69
 09 003 03  0    0    0   0   0    1    1    71
 0a 003 03  1    1    0   1   0    1    1    79
 0b 003 03  1    1    0   1   0    1    1    81
 0c 003 03  0    0    0   0   0    1    1    89
 0d 003 03  0    0    0   0   0    1    1    91
 0e 003 03  0    0    0   0   0    1    1    99
 0f 003 03  0    0    0   0   0    1    1    A1
 10 003 03  0    0    0   0   0    1    1    A9
 11 003 03  0    0    0   0   0    1    1    B1
 12 003 03  0    0    0   0   0    1    1    B9
 13 003 03  0    0    0   0   0    1    1    C1
 14 003 03  0    0    0   0   0    1    1    C9
 15 003 03  1    1    0   1   0    1    1    D1
 16 000 00  1    0    0   0   0    0    0    00
 17 000 00  1    0    0   0   0    0    0    00
IRQ to pin mappings:
IRQ0 -> 0:2
IRQ1 -> 0:1
IRQ3 -> 0:3
IRQ4 -> 0:4
IRQ5 -> 0:5
IRQ6 -> 0:6
IRQ7 -> 0:7
IRQ8 -> 0:8
IRQ9 -> 0:9
IRQ10 -> 0:10
IRQ11 -> 0:11
IRQ12 -> 0:12
IRQ13 -> 0:13
IRQ14 -> 0:14
IRQ15 -> 0:15
IRQ16 -> 0:16
IRQ17 -> 0:17
IRQ18 -> 0:18
IRQ19 -> 0:19
IRQ20 -> 0:20
IRQ21 -> 0:21
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1533.4294 MHz.
..... host bus clock speed is 266.6833 MHz.
cpu: 0, clocks: 2666833, slice: 888944
CPU0<T0:2666832,T1:1777888,D:0,S:888944,C:2666833>
cpu: 1, clocks: 2666833, slice: 888944
CPU1<T0:2666832,T1:888944,D:0,S:888944,C:2666833>
checking TSC synchronization across CPUs: passed.
migration_task 0 on cpu=0
migration_task 1 on cpu=1
PCI: PCI BIOS revision 2.10 entry at 0xfd7c0, last bus=2
PCI: Using configuration type 1
PCI: Probing PCI hardware
Unknown bridge resource 0: assuming transparent
Unknown bridge resource 1: assuming transparent
Unknown bridge resource 2: assuming transparent
Unknown bridge resource 2: assuming transparent
PCI: Using IRQ router AMD768 [1022/7443] at 00:07.3
BIOS failed to enable PCI standards compliance, fixing this error.

#####################################

The driver I'm using for the Gig E cards is the tg3 driver (Tigon III).
Is there some setting I can pass to the kernel to make these cards
choose another IRQ (like 6,7,12)??

Any help would be appreciated,


-- 
Erik Barker
Sr. Systems Engineer
NetNation Communications Inc.
http://www.netnation.com | http://www.domainpeople.com