Re: [PATCH v2 6/6] ASoC: dt-bindings: renesas,fsi: add support for multiple clocks

[Krzysztof Kozlowski <krzk@kernel.org>]

On Mon, Apr 13, 2026 at 05:07:00PM +0700, phucduc.bui@gmail.com wrote:
> From: bui duc phuc <phucduc.bui@gmail.com>
> 
> The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before
> accessing its registers. Without this clock, any register access leads to
> a system hang as the FSI block sits behind the SPU bus.
> Update the binding to support a flexible positional clock list to properly

Flexible is not allowed. Provide reasons for exception.

> describe the hardware clock tree, including:
>   - SPU bus/bridge clock (spu) for register access.
>   - CPG DIV6 clocks (icka/b) as functional clock parents.
>   - FSI internal dividers (diva/b) for audio clock generation.
>   - External clock inputs (xcka/b) provided by the board.
> 
> Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
> ---
> 
> Changes in v2:
>  - Rename FSI module clock to "own" to match driver.
>  - Add "spu", "icka/b", "diva/b", "xcka/b" clock names.
>  - Use YAML anchors to constrain clock-names properly.
>  - Add "if" rule to require "spu" clock for r8a7740.
>  - Update example with full clock configuration.
>  - Clean up schema by moving allOf location.
> 
>  .../bindings/sound/renesas,fsi.yaml           | 61 +++++++++++++++++--
>  1 file changed, 56 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
> index df91991699a7..d0ae54f3d321 100644
> --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
> +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
> @@ -9,9 +9,6 @@ title: Renesas FIFO-buffered Serial Interface (FSI)
>  maintainers:
>    - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>  
> -allOf:
> -  - $ref: dai-common.yaml#
> -
>  properties:
>    $nodename:
>      pattern: "^sound@.*"
> @@ -38,7 +35,36 @@ properties:
>      maxItems: 1
>  
>    clocks:
> -    maxItems: 1
> +    description: |
> +      Clock driving the FSI Controller. The first clock must be
> +      the module clock ("own").
> +    minItems: 1
> +    maxItems: 8
> +
> +  clock-names:
> +    description: |
> +      Names of clocks corresponding to entries in "clocks":
> +      - "own": Main FSI module clock (must be first and always present)
> +      - "spu": SPU bus/bridge clock. On R8A7740, this clock must be
> +        enabled to allow register access as the FSI block is connected
> +        behind the SPU bus.
> +      - "icka" / "ickb": CPG DIV6 functional clocks for FSI port A/B
> +      - "diva"/"divb": Internal FSI dividers for port A/B used for
> +        audio clock generation
> +      - "xcka"/"xckb": External clock inputs for FSI port A/B
> +        provided by the board

This goes to the "clocks:"

> +    minItems: 1
> +    items:
> +      - const: own
> +      - &fsi_all_clks

I don't understand this syntax.

Best regards,
Krzysztof