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From: phucduc.bui@gmail.com
To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org
Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, geert+renesas@glider.be,
	magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com,
	linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	bui duc phuc <phucduc.bui@gmail.com>
Subject: [PATCH v2 6/6] ASoC: dt-bindings: renesas,fsi: add support for multiple clocks
Date: Mon, 13 Apr 2026 17:07:00 +0700	[thread overview]
Message-ID: <20260413100700.30995-7-phucduc.bui@gmail.com> (raw)
In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com>

From: bui duc phuc <phucduc.bui@gmail.com>

The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before
accessing its registers. Without this clock, any register access leads to
a system hang as the FSI block sits behind the SPU bus.
Update the binding to support a flexible positional clock list to properly
describe the hardware clock tree, including:
  - SPU bus/bridge clock (spu) for register access.
  - CPG DIV6 clocks (icka/b) as functional clock parents.
  - FSI internal dividers (diva/b) for audio clock generation.
  - External clock inputs (xcka/b) provided by the board.

Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---

Changes in v2:
 - Rename FSI module clock to "own" to match driver.
 - Add "spu", "icka/b", "diva/b", "xcka/b" clock names.
 - Use YAML anchors to constrain clock-names properly.
 - Add "if" rule to require "spu" clock for r8a7740.
 - Update example with full clock configuration.
 - Clean up schema by moving allOf location.

 .../bindings/sound/renesas,fsi.yaml           | 61 +++++++++++++++++--
 1 file changed, 56 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
index df91991699a7..d0ae54f3d321 100644
--- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
@@ -9,9 +9,6 @@ title: Renesas FIFO-buffered Serial Interface (FSI)
 maintainers:
   - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 
-allOf:
-  - $ref: dai-common.yaml#
-
 properties:
   $nodename:
     pattern: "^sound@.*"
@@ -38,7 +35,36 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    description: |
+      Clock driving the FSI Controller. The first clock must be
+      the module clock ("own").
+    minItems: 1
+    maxItems: 8
+
+  clock-names:
+    description: |
+      Names of clocks corresponding to entries in "clocks":
+      - "own": Main FSI module clock (must be first and always present)
+      - "spu": SPU bus/bridge clock. On R8A7740, this clock must be
+        enabled to allow register access as the FSI block is connected
+        behind the SPU bus.
+      - "icka" / "ickb": CPG DIV6 functional clocks for FSI port A/B
+      - "diva"/"divb": Internal FSI dividers for port A/B used for
+        audio clock generation
+      - "xcka"/"xckb": External clock inputs for FSI port A/B
+        provided by the board
+    minItems: 1
+    items:
+      - const: own
+      - &fsi_all_clks
+        enum: [spu, icka, ickb, diva, divb, xcka, xckb]
+      - &fsi_no_spu_clks
+        enum: [icka, ickb, diva, divb, xcka, xckb]
+      - *fsi_no_spu_clks
+      - *fsi_no_spu_clks
+      - *fsi_no_spu_clks
+      - *fsi_no_spu_clks
+      - *fsi_no_spu_clks
 
   power-domains:
     maxItems: 1
@@ -69,6 +95,27 @@ required:
 
 unevaluatedProperties: false
 
+allOf:
+  - $ref: dai-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,fsi2-r8a7740
+    then:
+      properties:
+        clock-names:
+          minItems: 2
+          items:
+            - const: own
+            - const: spu
+            - *fsi_no_spu_clks
+            - *fsi_no_spu_clks
+            - *fsi_no_spu_clks
+            - *fsi_no_spu_clks
+            - *fsi_no_spu_clks
+            - *fsi_no_spu_clks
+
 examples:
   - |
     #include <dt-bindings/clock/r8a7740-clock.h>
@@ -77,7 +124,11 @@ examples:
             compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
             reg = <0xfe1f0000 0x400>;
             interrupts = <GIC_SPI 9 0x4>;
-            clocks = <&mstp3_clks R8A7740_CLK_FSI>;
+            clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>,
+                     <&fsia_clk>, <&fsib_clk>, <&fsidiva_clk>,
+                     <&fsidivb_clk>,<&fsiack_clk>,<&fsibck_clk>;
+            clock-names = "own", "spu", "icka", "ickb",
+                          "diva", "divb", "xcka", "xckb";
             power-domains = <&pd_a4mp>;
 
             #sound-dai-cells = <1>;
-- 
2.43.0


  parent reply	other threads:[~2026-04-13 10:07 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-13 10:06 [PATCH v2 0/6] ASoC: renesas: fsi: Fix system hang by adding SPU clock phucduc.bui
2026-04-13 10:06 ` [PATCH v2 1/6] ASoC: renesas: fsi: Add shared SPU clock support phucduc.bui
2026-04-14  0:02   ` Kuninori Morimoto
2026-04-14 10:53     ` Bui Duc Phuc
2026-04-13 10:06 ` [PATCH v2 2/6] ASoC: renesas: fsi: Fix hang by enabling SPU clock phucduc.bui
2026-04-14  0:27   ` Kuninori Morimoto
2026-04-15  9:02     ` Bui Duc Phuc
2026-04-13 10:06 ` [PATCH v2 3/6] ASoC: renesas: fsi: Fix trigger stop ordering phucduc.bui
2026-04-14  0:28   ` Kuninori Morimoto
2026-04-15  9:20     ` Bui Duc Phuc
2026-04-13 10:06 ` [PATCH v2 4/6] ASoC: renesas: fsi: refactor clock initialization phucduc.bui
2026-04-14  0:51   ` Kuninori Morimoto
2026-04-14 14:25     ` Bui Duc Phuc
2026-04-15  4:55       ` Kuninori Morimoto
2026-04-15  9:24         ` Bui Duc Phuc
2026-04-13 10:06 ` [PATCH v2 5/6] arm: dts: renesas: r8a7740: Add clocks for FSI phucduc.bui
2026-04-13 10:07 ` phucduc.bui [this message]
2026-04-14  6:55   ` [PATCH v2 6/6] ASoC: dt-bindings: renesas,fsi: add support for multiple clocks Krzysztof Kozlowski
2026-04-14 10:40     ` Bui Duc Phuc

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