Re: [PATCH] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

[Charles Keepax <ckeepax@opensource.cirrus.com>]

On Fri, Mar 27, 2026 at 04:23:31PM +0800, shumingf@realtek.com wrote:
> From: Shuming Fan <shumingf@realtek.com>
> 
> The division calculation should be implemented using signed integer format.
> This patch changes mc->shift from an unsigned type to a signed integer during the calculation.
> 
> Fixes: 501efdcb3b3a ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops")
> Signed-off-by: Shuming Fan <shumingf@realtek.com>
> ---
>  sound/soc/sdca/sdca_asoc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/sound/soc/sdca/sdca_asoc.c b/sound/soc/sdca/sdca_asoc.c
> index 733c9808891a..7709a4ce26e0 100644
> --- a/sound/soc/sdca/sdca_asoc.c
> +++ b/sound/soc/sdca/sdca_asoc.c
> @@ -850,7 +850,7 @@ static int q78_read(struct snd_soc_component *component,
>  
>  	reg_val = snd_soc_component_read(component, reg);
>  
> -	val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min;
> +	val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min;

oops... yeah thanks for catching that.

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles