[PATCH] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

[PATCH] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

[shumingf]

From: Shuming Fan <shumingf@realtek.com>

The division calculation should be implemented using signed integer format.
This patch changes mc->shift from an unsigned type to a signed integer during the calculation.

Fixes: 501efdcb3b3a ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops")
Signed-off-by: Shuming Fan <shumingf@realtek.com>
---
 sound/soc/sdca/sdca_asoc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/sdca/sdca_asoc.c b/sound/soc/sdca/sdca_asoc.c
index 733c9808891a..7709a4ce26e0 100644
--- a/sound/soc/sdca/sdca_asoc.c
+++ b/sound/soc/sdca/sdca_asoc.c
@@ -850,7 +850,7 @@ static int q78_read(struct snd_soc_component *component,
 
 	reg_val = snd_soc_component_read(component, reg);
 
-	val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min;
+	val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min;
 
 	return val & GENMASK(mc->sign_bit, 0);
 }
-- 
2.53.0

Re: [PATCH] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

[Charles Keepax]

On Fri, Mar 27, 2026 at 04:23:31PM +0800, shumingf@realtek.com wrote:
> From: Shuming Fan <shumingf@realtek.com>
> 
> The division calculation should be implemented using signed integer format.
> This patch changes mc->shift from an unsigned type to a signed integer during the calculation.
> 
> Fixes: 501efdcb3b3a ("ASoC: SDCA: Pull the Q7.8 volume helpers out of soc-ops")
> Signed-off-by: Shuming Fan <shumingf@realtek.com>
> ---
>  sound/soc/sdca/sdca_asoc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/sound/soc/sdca/sdca_asoc.c b/sound/soc/sdca/sdca_asoc.c
> index 733c9808891a..7709a4ce26e0 100644
> --- a/sound/soc/sdca/sdca_asoc.c
> +++ b/sound/soc/sdca/sdca_asoc.c
> @@ -850,7 +850,7 @@ static int q78_read(struct snd_soc_component *component,
>  
>  	reg_val = snd_soc_component_read(component, reg);
>  
> -	val = (sign_extend32(reg_val, mc->sign_bit) / mc->shift) - mc->min;
> +	val = (sign_extend32(reg_val, mc->sign_bit) / (int)mc->shift) - mc->min;

oops... yeah thanks for catching that.

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles

Re: [PATCH] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

[Mark Brown]

On Fri, 27 Mar 2026 16:23:31 +0800, shumingf@realtek.com wrote:
> ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.1

Thanks!

[1/1] ASoC: SDCA: fix the register to ctl value conversion for Q7.8 format
      https://git.kernel.org/broonie/sound/c/ae00200acb87

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark