[PATCH V2 0/2] soundwire: amd: clock related changes

[PATCH V2 0/2] soundwire: amd: clock related changes

[Vijendar Mukunda]

Refactor clock init sequence to support different bus clock frequencies
other than 12Mhz. Modify the bandwidth calculation logic to support 12Mhz,
6Mhz with different frame sizes.

Vijendar Mukunda (2):
  soundwire: amd: add clock init control function
  soundwire: amd: refactor bandwidth calculation logic

Changes since v1:
	- Update Cover letter title.
	- Fix typo error in commit message.
	- drop unnecessary condition check in compute params callback.

 drivers/soundwire/amd_manager.c   | 106 ++++++++++++++++++++++++++----
 drivers/soundwire/amd_manager.h   |   4 --
 include/linux/soundwire/sdw_amd.h |   4 ++
 3 files changed, 99 insertions(+), 15 deletions(-)

-- 
2.45.2

[PATCH V2 1/2] soundwire: amd: add clock init control function

[Vijendar Mukunda]

Add generic SoundWire clock initialization sequence to support
different SoundWire bus clock frequencies for ACP6.3/7.0/7.1/7.2
platforms and remove hard coding initializations for 12Mhz bus
clock frequency.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
---
 drivers/soundwire/amd_manager.c | 56 ++++++++++++++++++++++++++++-----
 drivers/soundwire/amd_manager.h |  4 ---
 2 files changed, 49 insertions(+), 11 deletions(-)

diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c
index 5fd311ee4107..ee3c37a5a48b 100644
--- a/drivers/soundwire/amd_manager.c
+++ b/drivers/soundwire/amd_manager.c
@@ -27,6 +27,49 @@
 
 #define to_amd_sdw(b)	container_of(b, struct amd_sdw_manager, bus)
 
+static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager)
+{
+	struct sdw_bus *bus = &amd_manager->bus;
+	struct sdw_master_prop *prop = &bus->prop;
+	u32 val;
+	int divider;
+
+	dev_dbg(amd_manager->dev, "mclk %d max %d row %d col %d frame_rate:%d\n",
+		prop->mclk_freq, prop->max_clk_freq, prop->default_row,
+		prop->default_col, prop->default_frame_rate);
+
+	if (!prop->default_frame_rate || !prop->default_row) {
+		dev_err(amd_manager->dev, "Default frame_rate %d or row %d is invalid\n",
+			prop->default_frame_rate, prop->default_row);
+		return -EINVAL;
+	}
+
+	/* Set clock divider */
+	dev_dbg(amd_manager->dev, "bus params curr_dr_freq: %d\n",
+		bus->params.curr_dr_freq);
+	divider = (prop->mclk_freq / bus->params.curr_dr_freq);
+
+	writel(divider, amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL);
+	val = readl(amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL);
+	dev_dbg(amd_manager->dev, "ACP_SW_CLK_FREQUENCY_CTRL:0x%x\n", val);
+
+	/* Set frame shape base on the actual bus frequency. */
+	prop->default_col = bus->params.curr_dr_freq /
+			    prop->default_frame_rate / prop->default_row;
+
+	dev_dbg(amd_manager->dev, "default_frame_rate:%d default_row: %d default_col: %d\n",
+		prop->default_frame_rate, prop->default_row, prop->default_col);
+	amd_manager->cols_index = sdw_find_col_index(prop->default_col);
+	amd_manager->rows_index = sdw_find_row_index(prop->default_row);
+	bus->params.col = prop->default_col;
+	bus->params.row = prop->default_row;
+	dev_dbg(amd_manager->dev, "rows_index: %d cols_index: %d\n",
+		amd_manager->rows_index, amd_manager->cols_index);
+	dev_dbg(amd_manager->dev, "params.col:0x%x params.row:0x%x\n",
+		bus->params.col, bus->params.row);
+	return 0;
+}
+
 static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager)
 {
 	u32 val;
@@ -961,6 +1004,9 @@ int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)
 
 	prop = &amd_manager->bus.prop;
 	if (!prop->hw_disabled) {
+		ret = amd_sdw_clk_init_ctrl(amd_manager);
+		if (ret)
+			return ret;
 		ret = amd_init_sdw_manager(amd_manager);
 		if (ret)
 			return ret;
@@ -985,7 +1031,6 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
 	struct resource *res;
 	struct device *dev = &pdev->dev;
 	struct sdw_master_prop *prop;
-	struct sdw_bus_params *params;
 	struct amd_sdw_manager *amd_manager;
 	int ret;
 
@@ -1049,14 +1094,8 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	params = &amd_manager->bus.params;
-
-	params->col = AMD_SDW_DEFAULT_COLUMNS;
-	params->row = AMD_SDW_DEFAULT_ROWS;
 	prop = &amd_manager->bus.prop;
-	prop->clk_freq = &amd_sdw_freq_tbl[0];
 	prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
-	prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;
 
 	ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode);
 	if (ret) {
@@ -1348,6 +1387,9 @@ static int __maybe_unused amd_resume_runtime(struct device *dev)
 			}
 		}
 		sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
+		ret = amd_sdw_clk_init_ctrl(amd_manager);
+		if (ret)
+			return ret;
 		amd_init_sdw_manager(amd_manager);
 		amd_enable_sdw_interrupts(amd_manager);
 		ret = amd_enable_sdw_manager(amd_manager);
diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manager.h
index 6cc916b0c820..88cf8a426a0c 100644
--- a/drivers/soundwire/amd_manager.h
+++ b/drivers/soundwire/amd_manager.h
@@ -203,10 +203,6 @@
 #define AMD_SDW_DEVICE_STATE_D3				3
 #define ACP_PME_EN					0x0001400
 
-static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
-	AMD_SDW_DEFAULT_CLK_FREQ,
-};
-
 struct sdw_manager_dp_reg {
 	u32 frame_fmt_reg;
 	u32 sample_int_reg;
-- 
2.45.2

[PATCH V2 2/2] soundwire: amd: refactor bandwidth calculation logic

[Vijendar Mukunda]

For ACP6.3/7.0/7.1/7.2 platforms, amd SoundWire manager doesn't have
banked registers concept. For bandwidth calculation, need to use static
mapping for block offset calculation based on master port request.
Refactor bandwidth calculation logic to support 6Mhz bus clock frequency
with frame size as 50 x 10, 125 x 2 and 12Mhz bus clock frequency with
frame size as 50 x 10 based on static port block offset logic.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
---
 drivers/soundwire/amd_manager.c   | 50 ++++++++++++++++++++++++++++---
 include/linux/soundwire/sdw_amd.h |  4 +++
 2 files changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c
index ee3c37a5a48b..fef5da7e29c5 100644
--- a/drivers/soundwire/amd_manager.c
+++ b/drivers/soundwire/amd_manager.c
@@ -480,12 +480,16 @@ static u32 amd_sdw_read_ping_status(struct sdw_bus *bus)
 
 static int amd_sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
 {
+	struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);
 	struct sdw_transport_data t_data = {0};
 	struct sdw_master_runtime *m_rt;
 	struct sdw_port_runtime *p_rt;
 	struct sdw_bus_params *b_params = &bus->params;
 	int port_bo, hstart, hstop, sample_int;
-	unsigned int rate, bps;
+	unsigned int rate, bps, channels;
+	int stream_slot_size, max_slots;
+	static int next_offset[AMD_SDW_MAX_MANAGER_COUNT] = {1};
+	unsigned int inst_id = amd_manager->instance;
 
 	port_bo = 0;
 	hstart = 1;
@@ -496,11 +500,44 @@ static int amd_sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime
 	list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 		rate = m_rt->stream->params.rate;
 		bps = m_rt->stream->params.bps;
+		channels = m_rt->stream->params.ch_count;
 		sample_int = (bus->params.curr_dr_freq / rate);
+
+		/* Compute slots required for this stream dynamically */
+		stream_slot_size = bps * channels;
+
 		list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
-			port_bo = (p_rt->num * 64) + 1;
-			dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n",
-				p_rt->num, hstart, hstop, port_bo);
+			if (p_rt->num >= amd_manager->max_ports) {
+				dev_err(bus->dev, "Port %d exceeds max ports %d\n",
+					p_rt->num, amd_manager->max_ports);
+				return -EINVAL;
+			}
+
+			/* Static mapping logic */
+			if (!amd_manager->port_offset_map[p_rt->num]) {
+				if (bus->params.curr_dr_freq == 12000000) {
+					max_slots = bus->params.row * (bus->params.col - 1);
+					if (next_offset[inst_id] + stream_slot_size <=
+					    (max_slots - 1)) {
+						amd_manager->port_offset_map[p_rt->num] =
+									next_offset[inst_id];
+						next_offset[inst_id] += stream_slot_size;
+					} else {
+						dev_err(bus->dev,
+							"No space for port %d\n", p_rt->num);
+						return -ENOMEM;
+					}
+				} else {
+					amd_manager->port_offset_map[p_rt->num] =
+									(p_rt->num * 64) + 1;
+				}
+			}
+			port_bo = amd_manager->port_offset_map[p_rt->num];
+			dev_dbg(bus->dev,
+				"Port=%d hstart=%d hstop=%d port_bo=%d slots=%d max_ports=%d\n",
+				p_rt->num, hstart, hstop, port_bo, stream_slot_size,
+				amd_manager->max_ports);
+
 			sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
 					      false, SDW_BLK_GRP_CNT_1, sample_int,
 					      port_bo, port_bo >> 8, hstart, hstop,
@@ -1093,6 +1130,11 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
 	default:
 		return -EINVAL;
 	}
+	amd_manager->max_ports = amd_manager->num_dout_ports + amd_manager->num_din_ports;
+	amd_manager->port_offset_map = devm_kcalloc(dev, amd_manager->max_ports,
+						    sizeof(int), GFP_KERNEL);
+	if (!amd_manager->port_offset_map)
+		return -ENOMEM;
 
 	prop = &amd_manager->bus.prop;
 	prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
diff --git a/include/linux/soundwire/sdw_amd.h b/include/linux/soundwire/sdw_amd.h
index fe31773d5210..470360a2723c 100644
--- a/include/linux/soundwire/sdw_amd.h
+++ b/include/linux/soundwire/sdw_amd.h
@@ -66,8 +66,10 @@ struct sdw_amd_dai_runtime {
  * @status: peripheral devices status array
  * @num_din_ports: number of input ports
  * @num_dout_ports: number of output ports
+ * @max_ports: total number of input ports and output ports
  * @cols_index: Column index in frame shape
  * @rows_index: Rows index in frame shape
+ * @port_offset_map: dynamic array to map port block offset
  * @instance: SoundWire manager instance
  * @quirks: SoundWire manager quirks
  * @wake_en_mask: wake enable mask per SoundWire manager
@@ -92,10 +94,12 @@ struct amd_sdw_manager {
 
 	int num_din_ports;
 	int num_dout_ports;
+	int max_ports;
 
 	int cols_index;
 	int rows_index;
 
+	int *port_offset_map;
 	u32 instance;
 	u32 quirks;
 	u32 wake_en_mask;
-- 
2.45.2

Re: [PATCH V2 1/2] soundwire: amd: add clock init control function

[Mario Limonciello (AMD) (kernel.org)]

On 1/13/2026 8:13 AM, Vijendar Mukunda wrote:
> Add generic SoundWire clock initialization sequence to support
> different SoundWire bus clock frequencies for ACP6.3/7.0/7.1/7.2
> platforms and remove hard coding initializations for 12Mhz bus
> clock frequency.
> 
> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>

> ---
>   drivers/soundwire/amd_manager.c | 56 ++++++++++++++++++++++++++++-----
>   drivers/soundwire/amd_manager.h |  4 ---
>   2 files changed, 49 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c
> index 5fd311ee4107..ee3c37a5a48b 100644
> --- a/drivers/soundwire/amd_manager.c
> +++ b/drivers/soundwire/amd_manager.c
> @@ -27,6 +27,49 @@
>   
>   #define to_amd_sdw(b)	container_of(b, struct amd_sdw_manager, bus)
>   
> +static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager)
> +{
> +	struct sdw_bus *bus = &amd_manager->bus;
> +	struct sdw_master_prop *prop = &bus->prop;
> +	u32 val;
> +	int divider;
> +
> +	dev_dbg(amd_manager->dev, "mclk %d max %d row %d col %d frame_rate:%d\n",
> +		prop->mclk_freq, prop->max_clk_freq, prop->default_row,
> +		prop->default_col, prop->default_frame_rate);
> +
> +	if (!prop->default_frame_rate || !prop->default_row) {
> +		dev_err(amd_manager->dev, "Default frame_rate %d or row %d is invalid\n",
> +			prop->default_frame_rate, prop->default_row);
> +		return -EINVAL;
> +	}
> +
> +	/* Set clock divider */
> +	dev_dbg(amd_manager->dev, "bus params curr_dr_freq: %d\n",
> +		bus->params.curr_dr_freq);
> +	divider = (prop->mclk_freq / bus->params.curr_dr_freq);
> +
> +	writel(divider, amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL);
> +	val = readl(amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL);
> +	dev_dbg(amd_manager->dev, "ACP_SW_CLK_FREQUENCY_CTRL:0x%x\n", val);
> +
> +	/* Set frame shape base on the actual bus frequency. */
> +	prop->default_col = bus->params.curr_dr_freq /
> +			    prop->default_frame_rate / prop->default_row;
> +
> +	dev_dbg(amd_manager->dev, "default_frame_rate:%d default_row: %d default_col: %d\n",
> +		prop->default_frame_rate, prop->default_row, prop->default_col);
> +	amd_manager->cols_index = sdw_find_col_index(prop->default_col);
> +	amd_manager->rows_index = sdw_find_row_index(prop->default_row);
> +	bus->params.col = prop->default_col;
> +	bus->params.row = prop->default_row;
> +	dev_dbg(amd_manager->dev, "rows_index: %d cols_index: %d\n",
> +		amd_manager->rows_index, amd_manager->cols_index);
> +	dev_dbg(amd_manager->dev, "params.col:0x%x params.row:0x%x\n",
> +		bus->params.col, bus->params.row);
> +	return 0;
> +}
> +
>   static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager)
>   {
>   	u32 val;
> @@ -961,6 +1004,9 @@ int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)
>   
>   	prop = &amd_manager->bus.prop;
>   	if (!prop->hw_disabled) {
> +		ret = amd_sdw_clk_init_ctrl(amd_manager);
> +		if (ret)
> +			return ret;
>   		ret = amd_init_sdw_manager(amd_manager);
>   		if (ret)
>   			return ret;
> @@ -985,7 +1031,6 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
>   	struct resource *res;
>   	struct device *dev = &pdev->dev;
>   	struct sdw_master_prop *prop;
> -	struct sdw_bus_params *params;
>   	struct amd_sdw_manager *amd_manager;
>   	int ret;
>   
> @@ -1049,14 +1094,8 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
>   		return -EINVAL;
>   	}
>   
> -	params = &amd_manager->bus.params;
> -
> -	params->col = AMD_SDW_DEFAULT_COLUMNS;
> -	params->row = AMD_SDW_DEFAULT_ROWS;
>   	prop = &amd_manager->bus.prop;
> -	prop->clk_freq = &amd_sdw_freq_tbl[0];
>   	prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
> -	prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;
>   
>   	ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode);
>   	if (ret) {
> @@ -1348,6 +1387,9 @@ static int __maybe_unused amd_resume_runtime(struct device *dev)
>   			}
>   		}
>   		sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
> +		ret = amd_sdw_clk_init_ctrl(amd_manager);
> +		if (ret)
> +			return ret;
>   		amd_init_sdw_manager(amd_manager);
>   		amd_enable_sdw_interrupts(amd_manager);
>   		ret = amd_enable_sdw_manager(amd_manager);
> diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manager.h
> index 6cc916b0c820..88cf8a426a0c 100644
> --- a/drivers/soundwire/amd_manager.h
> +++ b/drivers/soundwire/amd_manager.h
> @@ -203,10 +203,6 @@
>   #define AMD_SDW_DEVICE_STATE_D3				3
>   #define ACP_PME_EN					0x0001400
>   
> -static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
> -	AMD_SDW_DEFAULT_CLK_FREQ,
> -};
> -
>   struct sdw_manager_dp_reg {
>   	u32 frame_fmt_reg;
>   	u32 sample_int_reg;

Re: [PATCH V2 2/2] soundwire: amd: refactor bandwidth calculation logic

[Pierre-Louis Bossart]

On 1/13/26 15:13, Vijendar Mukunda wrote:
> For ACP6.3/7.0/7.1/7.2 platforms, amd SoundWire manager doesn't have
> banked registers concept. For bandwidth calculation, need to use static
> mapping for block offset calculation based on master port request.
> Refactor bandwidth calculation logic to support 6Mhz bus clock frequency
> with frame size as 50 x 10, 125 x 2 and 12Mhz bus clock frequency with
> frame size as 50 x 10 based on static port block offset logic.

Consider rewriting this commit message, it's quite unclear how you went from 'no banked registers' to static mapping of block offset calculation logic. There's also a built-in contradiction between the need for bandwidth calculation and static mappings. If you force a specific port to use a specific part of the frame, then you don't really need to calculate the bandwidth, do you? Or maybe only to control that the space allocated statically for the port is enough for a stream.

In addition the text says both 6 and 12 MHz are supported, but....


> +			/* Static mapping logic */
> +			if (!amd_manager->port_offset_map[p_rt->num]) {
> +				if (bus->params.curr_dr_freq == 12000000) {

.... this only deals with 6MHz bus clock. 

> +					max_slots = bus->params.row * (bus->params.col - 1);
> +					if (next_offset[inst_id] + stream_slot_size <=
> +					    (max_slots - 1)) {
> +						amd_manager->port_offset_map[p_rt->num] =
> +									next_offset[inst_id];
> +						next_offset[inst_id] += stream_slot_size;
> +					} else {
> +						dev_err(bus->dev,
> +							"No space for port %d\n", p_rt->num);
> +						return -ENOMEM;
> +					}
> +				} else {
> +					amd_manager->port_offset_map[p_rt->num] =
> +									(p_rt->num * 64) + 1;

... and this doesn't seem related to 12 MHz.

> +				}
> +			}
> +			port_bo = amd_manager->port_offset_map[p_rt->num];
> +			dev_dbg(bus->dev,
> +				"Port=%d hstart=%d hstop=%d port_bo=%d slots=%d max_ports=%d\n",
> +				p_rt->num, hstart, hstop, port_bo, stream_slot_size,
> +				amd_manager->max_ports);
> +
>  			sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
>  					      false, SDW_BLK_GRP_CNT_1, sample_int,
>  					      port_bo, port_bo >> 8, hstart, hstop,
> @@ -1093,6 +1130,11 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
>  	default:
>  		return -EINVAL;
>  	}
> +	amd_manager->max_ports = amd_manager->num_dout_ports + amd_manager->num_din_ports;
> +	amd_manager->port_offset_map = devm_kcalloc(dev, amd_manager->max_ports,
> +						    sizeof(int), GFP_KERNEL);
> +	if (!amd_manager->port_offset_map)
> +		return -ENOMEM;
>  
>  	prop = &amd_manager->bus.prop;
>  	prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
> diff --git a/include/linux/soundwire/sdw_amd.h b/include/linux/soundwire/sdw_amd.h
> index fe31773d5210..470360a2723c 100644
> --- a/include/linux/soundwire/sdw_amd.h
> +++ b/include/linux/soundwire/sdw_amd.h
> @@ -66,8 +66,10 @@ struct sdw_amd_dai_runtime {
>   * @status: peripheral devices status array
>   * @num_din_ports: number of input ports
>   * @num_dout_ports: number of output ports
> + * @max_ports: total number of input ports and output ports
>   * @cols_index: Column index in frame shape
>   * @rows_index: Rows index in frame shape
> + * @port_offset_map: dynamic array to map port block offset
>   * @instance: SoundWire manager instance
>   * @quirks: SoundWire manager quirks
>   * @wake_en_mask: wake enable mask per SoundWire manager
> @@ -92,10 +94,12 @@ struct amd_sdw_manager {
>  
>  	int num_din_ports;
>  	int num_dout_ports;
> +	int max_ports;
>  
>  	int cols_index;
>  	int rows_index;
>  
> +	int *port_offset_map;
>  	u32 instance;
>  	u32 quirks;
>  	u32 wake_en_mask;

Re: [PATCH V2 2/2] soundwire: amd: refactor bandwidth calculation logic

[Mukunda,Vijendar]

On 14/01/26 03:09, Pierre-Louis Bossart wrote:
> On 1/13/26 15:13, Vijendar Mukunda wrote:
>> For ACP6.3/7.0/7.1/7.2 platforms, amd SoundWire manager doesn't have
>> banked registers concept. For bandwidth calculation, need to use static
>> mapping for block offset calculation based on master port request.
>> Refactor bandwidth calculation logic to support 6Mhz bus clock frequency
>> with frame size as 50 x 10, 125 x 2 and 12Mhz bus clock frequency with
>> frame size as 50 x 10 based on static port block offset logic.
> Consider rewriting this commit message, it's quite unclear how you went from 'no banked registers' to static mapping of block offset calculation logic. There's also a built-in contradiction between the need for bandwidth calculation and static mappings. If you force a specific port to use a specific part of the frame, then you don't really need to calculate the bandwidth, do you? Or maybe only to control that the space allocated statically for the port is enough for a stream.
>
> In addition the text says both 6 and 12 MHz are supported, but....

For Current platforms(ACP6.3/ACP7.0/ACP7.1/ACP7.2), AMD SoundWire manager
doesn't have banked registers for data port programming on Manager side, 
so we need to use fixed block offsets , hstart & hstop for manager ports.

Earlier we only support 12Mhz frequency with frame shape as 50 x10 with fixed block
offset mapping based on port number, i.e. For example for ACP7.0 platform,
we have two SoundWire instances where it can support 3 TX ports and 3 RX ports.
Else condition logic points to block offset calculation based on port number.

amd_manager->port_offset_map[p_rt->num] =  (p_rt->num * 64) + 1;

Now we got a requirement to support 6Mhz bus clock frequency with different frame
shapes, i.e 125 x2 and 50 x 10.

First, if condition checks for 6Mhz frequency. As max available bit slots vary
based on
frame shape, we have implemented logic to calculate block offset for a port where 
it should use fixed block offset for that port.

Will update the commit message, add comments in the code.



>
>
>> +			/* Static mapping logic */
>> +			if (!amd_manager->port_offset_map[p_rt->num]) {
>> +				if (bus->params.curr_dr_freq == 12000000) {
> .... this only deals with 6MHz bus clock. 
>
>> +					max_slots = bus->params.row * (bus->params.col - 1);
>> +					if (next_offset[inst_id] + stream_slot_size <=
>> +					    (max_slots - 1)) {
>> +						amd_manager->port_offset_map[p_rt->num] =
>> +									next_offset[inst_id];
>> +						next_offset[inst_id] += stream_slot_size;
>> +					} else {
>> +						dev_err(bus->dev,
>> +							"No space for port %d\n", p_rt->num);
>> +						return -ENOMEM;
>> +					}
>> +				} else {
>> +					amd_manager->port_offset_map[p_rt->num] =
>> +									(p_rt->num * 64) + 1;
> ... and this doesn't seem related to 12 MHz.
>
>> +				}
>> +			}
>> +			port_bo = amd_manager->port_offset_map[p_rt->num];
>> +			dev_dbg(bus->dev,
>> +				"Port=%d hstart=%d hstop=%d port_bo=%d slots=%d max_ports=%d\n",
>> +				p_rt->num, hstart, hstop, port_bo, stream_slot_size,
>> +				amd_manager->max_ports);
>> +
>>  			sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
>>  					      false, SDW_BLK_GRP_CNT_1, sample_int,
>>  					      port_bo, port_bo >> 8, hstart, hstop,
>> @@ -1093,6 +1130,11 @@ static int amd_sdw_manager_probe(struct platform_device *pdev)
>>  	default:
>>  		return -EINVAL;
>>  	}
>> +	amd_manager->max_ports = amd_manager->num_dout_ports + amd_manager->num_din_ports;
>> +	amd_manager->port_offset_map = devm_kcalloc(dev, amd_manager->max_ports,
>> +						    sizeof(int), GFP_KERNEL);
>> +	if (!amd_manager->port_offset_map)
>> +		return -ENOMEM;
>>  
>>  	prop = &amd_manager->bus.prop;
>>  	prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;
>> diff --git a/include/linux/soundwire/sdw_amd.h b/include/linux/soundwire/sdw_amd.h
>> index fe31773d5210..470360a2723c 100644
>> --- a/include/linux/soundwire/sdw_amd.h
>> +++ b/include/linux/soundwire/sdw_amd.h
>> @@ -66,8 +66,10 @@ struct sdw_amd_dai_runtime {
>>   * @status: peripheral devices status array
>>   * @num_din_ports: number of input ports
>>   * @num_dout_ports: number of output ports
>> + * @max_ports: total number of input ports and output ports
>>   * @cols_index: Column index in frame shape
>>   * @rows_index: Rows index in frame shape
>> + * @port_offset_map: dynamic array to map port block offset
>>   * @instance: SoundWire manager instance
>>   * @quirks: SoundWire manager quirks
>>   * @wake_en_mask: wake enable mask per SoundWire manager
>> @@ -92,10 +94,12 @@ struct amd_sdw_manager {
>>  
>>  	int num_din_ports;
>>  	int num_dout_ports;
>> +	int max_ports;
>>  
>>  	int cols_index;
>>  	int rows_index;
>>  
>> +	int *port_offset_map;
>>  	u32 instance;
>>  	u32 quirks;
>>  	u32 wake_en_mask;