[PATCH 0/2] Add Renesas RZ/G3L RSPI support

[PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

This patch series adds binding and driver support for RSPI IP found on the
RZ/G3L SoC. The RSPI is compatible with RZ/V2H RSPI, but has 2 clocks
compared to 3 on RZ/V2H.

Biju Das (2):
  dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
  spi: rzv2h-rspi: Add support for RZ/G3L (R9A08G046)

 .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
 drivers/spi/spi-rzv2h-rspi.c                  |  8 ++++++
 2 files changed, 34 insertions(+)

-- 
2.43.0

[PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with
the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
index cf8b733b766d..599c06ff08e5 100644
--- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - renesas,r9a08g046-rspi # RZ/G3L
           - renesas,r9a09g057-rspi # RZ/V2H(P)
           - renesas,r9a09g077-rspi # RZ/T2H
       - items:
@@ -85,6 +86,31 @@ required:
 
 allOf:
   - $ref: spi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a08g046-rspi
+    then:
+      properties:
+        clocks:
+          maxItems: 2
+
+        clock-names:
+          items:
+            - const: pclk
+            - const: tclk
+        dmas:
+          maxItems: 2
+
+        dma-names:
+          maxItems: 2
+
+      required:
+        - resets
+        - reset-names
+
   - if:
       properties:
         compatible:
-- 
2.43.0

[PATCH 2/2] spi: rzv2h-rspi: Add support for RZ/G3L (R9A08G046)

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add support for RZ/G3L RSPI. The RZ/G3L variant requires only
2 clocks (pclk + tclk), unlike the RZ/V2H which needs 3.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/spi/spi-rzv2h-rspi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c
index 23f0e92ae208..38ee09e389c9 100644
--- a/drivers/spi/spi-rzv2h-rspi.c
+++ b/drivers/spi/spi-rzv2h-rspi.c
@@ -811,6 +811,13 @@ static const struct rzv2h_rspi_info rzv2h_info = {
 	.num_clks = 3,
 };
 
+static const struct rzv2h_rspi_info rzg3l_info = {
+	.find_tclk_rate = rzv2h_rspi_find_rate_fixed,
+	.tclk_name = "tclk",
+	.fifo_size = 16,
+	.num_clks = 2,
+};
+
 static const struct rzv2h_rspi_info rzt2h_info = {
 	.find_tclk_rate = rzv2h_rspi_find_rate_variable,
 	.find_pclk_rate = rzv2h_rspi_find_rate_fixed,
@@ -820,6 +827,7 @@ static const struct rzv2h_rspi_info rzt2h_info = {
 };
 
 static const struct of_device_id rzv2h_rspi_match[] = {
+	{ .compatible = "renesas,r9a08g046-rspi", &rzg3l_info },
 	{ .compatible = "renesas,r9a09g057-rspi", &rzv2h_info },
 	{ .compatible = "renesas,r9a09g077-rspi", &rzt2h_info },
 	{ /* sentinel */ }
-- 
2.43.0

Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Krzysztof Kozlowski]

On 04/03/2026 08:49, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with
> the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> index cf8b733b766d..599c06ff08e5 100644
> --- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> @@ -13,6 +13,7 @@ properties:
>    compatible:
>      oneOf:
>        - enum:
> +          - renesas,r9a08g046-rspi # RZ/G3L
>            - renesas,r9a09g057-rspi # RZ/V2H(P)
>            - renesas,r9a09g077-rspi # RZ/T2H
>        - items:
> @@ -85,6 +86,31 @@ required:
>  
>  allOf:
>    - $ref: spi-controller.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,r9a08g046-rspi
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 2
> +
> +        clock-names:
> +          items:
> +            - const: pclk
> +            - const: tclk
> +        dmas:
> +          maxItems: 2
> +
> +        dma-names:
> +          maxItems: 2

So even after my objections here:
https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@kernel.org/

this was not fixed and Renesas did not provide actual cross-patch review.

This is still probably wrong as pointed out by other patches by Renesas.
Also, you cannot have flexible names.

NAK

Best regards,
Krzysztof

RE: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the review.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 04 March 2026 15:04
> Subject: Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
> 
> On 04/03/2026 08:49, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible
> > with the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> > b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> > index cf8b733b766d..599c06ff08e5 100644
> > --- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> > @@ -13,6 +13,7 @@ properties:
> >    compatible:
> >      oneOf:
> >        - enum:
> > +          - renesas,r9a08g046-rspi # RZ/G3L
> >            - renesas,r9a09g057-rspi # RZ/V2H(P)
> >            - renesas,r9a09g077-rspi # RZ/T2H
> >        - items:
> > @@ -85,6 +86,31 @@ required:
> >
> >  allOf:
> >    - $ref: spi-controller.yaml#
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,r9a08g046-rspi
> > +    then:
> > +      properties:
> > +        clocks:
> > +          maxItems: 2
> > +
> > +        clock-names:
> > +          items:
> > +            - const: pclk
> > +            - const: tclk
> > +        dmas:
> > +          maxItems: 2
> > +
> > +        dma-names:
> > +          maxItems: 2
> 
> So even after my objections here:
> https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@kernel.org/
> 
> this was not fixed and Renesas did not provide actual cross-patch review.

That patch is not correct. See below.

> 
> This is still probably wrong as pointed out by other patches by Renesas.
> Also, you cannot have flexible names.

You can have "rx", "tx" in any order and {rx, tx} should be unique dma specifier
and  it should have at least 1 tx and 1 rx for multiple DMAC.

For RZ/G3L SoC, only 1 DMA and Nothing prevent us to specify it as { rx, tx} or {rx, tx}

But for RZ/G3E SoC, 5 DMAC and we tested all the combinations

DMAC0{rx} DMAC0{tx}
DMAC0{rx} DMAC1{tx}
DMAC1{rx} DMAC0{tx}
DMAC0{rx} DMAC2{tx}
DMAC2{rx} DMAC0{tx}
DMAC0{rx} DMAC3{tx}
DMAC3{rx} DMAC0{tx}
DMAC0{rx} DMAC4{tx}
DMAC4{rx} DMAC0{tx}
DMAC1{rx} DMAC2{tx}
DMAC2{rx} DMAC1{tx}
DMAC1{rx} DMAC3{tx}
DMAC3{rx} DMAC1{tx}
DMAC1{rx} DMAC4{tx}
DMAC4{rx} DMAC1{tx}
DMAC2{rx} DMAC3{tx}
DMAC3{rx} DMAC2{tx}
DMAC2{rx} DMAC4{tx} 
DMAC4{rx} DMAC2{tx} 
DMAC3{rx} DMAC4{tx}
DMAC4{rx} DMAC3{tx}

{ rx, tx, rx} 
{ rx, tx, rx, rx}
{ rx, rx, rx, rx, tx}

any combinations is valid with atleast 1 tx and 1 rx.


Are we missing anything here? Please let us know.


Cheers,
Biju

Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Krzysztof Kozlowski]

On 04/03/2026 16:18, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
> Thanks for the review.
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 04 March 2026 15:04
>> Subject: Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
>>
>> On 04/03/2026 08:49, Biju wrote:
>>> From: Biju Das <biju.das.jz@bp.renesas.com>
>>>
>>> Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible
>>> with the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> ---
>>>  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
>>>  1 file changed, 26 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> index cf8b733b766d..599c06ff08e5 100644
>>> --- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
>>> @@ -13,6 +13,7 @@ properties:
>>>    compatible:
>>>      oneOf:
>>>        - enum:
>>> +          - renesas,r9a08g046-rspi # RZ/G3L
>>>            - renesas,r9a09g057-rspi # RZ/V2H(P)
>>>            - renesas,r9a09g077-rspi # RZ/T2H
>>>        - items:
>>> @@ -85,6 +86,31 @@ required:
>>>
>>>  allOf:
>>>    - $ref: spi-controller.yaml#
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - renesas,r9a08g046-rspi
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          maxItems: 2
>>> +
>>> +        clock-names:
>>> +          items:
>>> +            - const: pclk
>>> +            - const: tclk
>>> +        dmas:
>>> +          maxItems: 2
>>> +
>>> +        dma-names:
>>> +          maxItems: 2
>>
>> So even after my objections here:
>> https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@kernel.org/
>>
>> this was not fixed and Renesas did not provide actual cross-patch review.
> 
> That patch is not correct. See below.
> 
>>
>> This is still probably wrong as pointed out by other patches by Renesas.
>> Also, you cannot have flexible names.
> 
> You can have "rx", "tx" in any order and {rx, tx} should be unique dma specifier

No. You cannot. I just told you so. Please read writing-bindings for
arguments.

Look at the code which was here before that incomplete solution was merged.



> and  it should have at least 1 tx and 1 rx for multiple DMAC.
> 
> For RZ/G3L SoC, only 1 DMA and Nothing prevent us to specify it as { rx, tx} or {rx, tx}
> 

Well, I prevent you. So NAK.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Geert Uytterhoeven]

On Wed, 4 Mar 2026 at 08:49, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with
> the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] spi: rzv2h-rspi: Add support for RZ/G3L (R9A08G046)

[Geert Uytterhoeven]

On Wed, 4 Mar 2026 at 08:49, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add support for RZ/G3L RSPI. The RZ/G3L variant requires only
> 2 clocks (pclk + tclk), unlike the RZ/V2H which needs 3.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Biju Das]

Hi All,

> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: 04 March 2026 07:49
> Subject: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> 
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> This patch series adds binding and driver support for RSPI IP found on the RZ/G3L SoC. The RSPI is
> compatible with RZ/V2H RSPI, but has 2 clocks compared to 3 on RZ/V2H.
> 
> Biju Das (2):
>   dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
>   spi: rzv2h-rspi: Add support for RZ/G3L (R9A08G046)
> 
>  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
>  drivers/spi/spi-rzv2h-rspi.c                  |  8 ++++++
>  2 files changed, 34 insertions(+)
> 
> --
> 2.43.0

Gentle ping.

Cheers,
Biju

RE: [PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Biju Das]

> -----Original Message-----
> From: Biju Das
> Sent: 02 April 2026 14:00
> Subject: RE: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> 
> Hi All,
> 
> > -----Original Message-----
> > From: Biju <biju.das.au@gmail.com>
> > Sent: 04 March 2026 07:49
> > Subject: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> >
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > This patch series adds binding and driver support for RSPI IP found on
> > the RZ/G3L SoC. The RSPI is compatible with RZ/V2H RSPI, but has 2 clocks compared to 3 on RZ/V2H.
> >
> > Biju Das (2):
> >   dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
> >   spi: rzv2h-rspi: Add support for RZ/G3L (R9A08G046)
> >
> >  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
> >  drivers/spi/spi-rzv2h-rspi.c                  |  8 ++++++
> >  2 files changed, 34 insertions(+)
> >
> > --
> > 2.43.0
> 
> Gentle ping.

Better I will rebase and send new series with tags collected.

Cheers,
Biju

Re: [PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 898 bytes --]

On Thu, Apr 02, 2026 at 01:00:28PM +0000, Biju Das wrote:

> Gentle ping.

There's strongly negative feedback from Krzysztof...

Please don't send content free pings and please allow a reasonable time
for review.  People get busy, go on holiday, attend conferences and so 
on so unless there is some reason for urgency (like critical bug fixes)
please allow at least a couple of weeks for review.  If there have been
review comments then people may be waiting for those to be addressed.

Sending content free pings adds to the mail volume (if they are seen at
all) which is often the problem and since they can't be reviewed
directly if something has gone wrong you'll have to resend the patches
anyway, so sending again is generally a better approach though there are
some other maintainers who like them - if in doubt look at how patches
for the subsystem are normally handled.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

RE: [PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Biju Das]

Hi Mark Brown,

Thanks for the feedback

> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: 02 April 2026 14:20
> Subject: Re: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> 
> On Thu, Apr 02, 2026 at 01:00:28PM +0000, Biju Das wrote:
> 
> > Gentle ping.
> 
> There's strongly negative feedback from Krzysztof...

I believe Krzysztof is complaining about patch [1] and his
comments were addressed in [2].

> 
> Please don't send content free pings and please allow a reasonable time for review.  People get busy,
> go on holiday, attend conferences and so on so unless there is some reason for urgency (like critical
> bug fixes) please allow at least a couple of weeks for review.  If there have been review comments then
> people may be waiting for those to be addressed.
> 
> Sending content free pings adds to the mail volume (if they are seen at
> all) which is often the problem and since they can't be reviewed directly if something has gone wrong
> you'll have to resend the patches anyway, so sending again is generally a better approach though there
> are some other maintainers who like them - if in doubt look at how patches for the subsystem are
> normally handled.

There is no pending points, everything addressed in [2]. that is the reason for
sending gentle reminder.

if Krzysztof has any comments related to [3], I am happy to address.


[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml?h=next-20260401&id=4d28f38f64ef69ab27839069ef3346c3c878d137

[2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml?h=next-20260401&id=c2edd7841f58cf228347b91256f0d9efcc1a1f50

[3] https://lore.kernel.org/all/20260304074907.9697-2-biju.das.jz@bp.renesas.com/


Cheers,
Biju

RE: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 04 March 2026 15:43
> Subject: Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
> 
> On 04/03/2026 16:18, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> > Thanks for the review.
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 04 March 2026 15:04
> >> Subject: Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi:
> >> Document RZ/G3L SoC
> >>
> >> On 04/03/2026 08:49, Biju wrote:
> >>> From: Biju Das <biju.das.jz@bp.renesas.com>
> >>>
> >>> Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible
> >>> with the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.
> >>>
> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>> ---
> >>>  .../bindings/spi/renesas,rzv2h-rspi.yaml      | 26 +++++++++++++++++++
> >>>  1 file changed, 26 insertions(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> >>> b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> >>> index cf8b733b766d..599c06ff08e5 100644
> >>> --- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> >>> +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
> >>> @@ -13,6 +13,7 @@ properties:
> >>>    compatible:
> >>>      oneOf:
> >>>        - enum:
> >>> +          - renesas,r9a08g046-rspi # RZ/G3L
> >>>            - renesas,r9a09g057-rspi # RZ/V2H(P)
> >>>            - renesas,r9a09g077-rspi # RZ/T2H
> >>>        - items:
> >>> @@ -85,6 +86,31 @@ required:
> >>>
> >>>  allOf:
> >>>    - $ref: spi-controller.yaml#
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            enum:
> >>> +              - renesas,r9a08g046-rspi
> >>> +    then:
> >>> +      properties:
> >>> +        clocks:
> >>> +          maxItems: 2
> >>> +
> >>> +        clock-names:
> >>> +          items:
> >>> +            - const: pclk
> >>> +            - const: tclk
> >>> +        dmas:
> >>> +          maxItems: 2
> >>> +
> >>> +        dma-names:
> >>> +          maxItems: 2
> >>
> >> So even after my objections here:
> >> https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@kern
> >> el.org/
> >>
> >> this was not fixed and Renesas did not provide actual cross-patch review.
> >
> > That patch is not correct. See below.
> >
> >>
> >> This is still probably wrong as pointed out by other patches by Renesas.
> >> Also, you cannot have flexible names.
> >
> > You can have "rx", "tx" in any order and {rx, tx} should be unique dma
> > specifier
> 
> No. You cannot. I just told you so. Please read writing-bindings for arguments.

<snippet from writing-bindings >
- DO define properties in terms of constraints. How many entries? What are
  possible values? What is the order? All these constraints represent the ABI
  as well.
</snippet>

Is that the reason you're saying we cannot have flexible names for DMAs?

Are you expecting the RZ/G3L DMA entries to be like below? Please let me know.

This is not flexible — the user always needs to specify RX first, followed by TX.

+  dmas:
+    maxItems: 2
+
+  dma-names:
+    items:
+      - const: rx
+      - const: tx

Cheers,
Biju

Re: [PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Mark Brown]

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On Thu, Apr 02, 2026 at 01:32:29PM +0000, Biju Das wrote:
> > -----Original Message-----
> > From: Mark Brown <broonie@kernel.org>
> > Sent: 02 April 2026 14:20
> > Subject: Re: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> > 
> > On Thu, Apr 02, 2026 at 01:00:28PM +0000, Biju Das wrote:

> > > Gentle ping.

> > There's strongly negative feedback from Krzysztof...

> I believe Krzysztof is complaining about patch [1] and his
> comments were addressed in [2].

That's really not at all clear from the discussion.

Please include human readable descriptions of things like commits and
issues being discussed in e-mail in your mails, this makes them much
easier for humans to read especially when they have no internet access.
I do frequently catch up on my mail on flights or while otherwise
travelling so this is even more pressing for me than just being about
making things a bit easier to read.

> > Please don't send content free pings and please allow a reasonable time for review.  People get busy,
> > go on holiday, attend conferences and so on so unless there is some reason for urgency (like critical
> > bug fixes) please allow at least a couple of weeks for review.  If there have been review comments then
> > people may be waiting for those to be addressed.

> > Sending content free pings adds to the mail volume (if they are seen at
> > all) which is often the problem and since they can't be reviewed directly if something has gone wrong
> > you'll have to resend the patches anyway, so sending again is generally a better approach though there
> > are some other maintainers who like them - if in doubt look at how patches for the subsystem are
> > normally handled.

> There is no pending points, everything addressed in [2]. that is the reason for
> sending gentle reminder.

There's more there than just "make sure you've addressed review
comments".

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RE: [PATCH 0/2] Add Renesas RZ/G3L RSPI support

[Biju Das]

Hi Mark,

Thanks for the feedback.

> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: 02 April 2026 15:52
> Subject: Re: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> 
> On Thu, Apr 02, 2026 at 01:32:29PM +0000, Biju Das wrote:
> > > -----Original Message-----
> > > From: Mark Brown <broonie@kernel.org>
> > > Sent: 02 April 2026 14:20
> > > Subject: Re: [PATCH 0/2] Add Renesas RZ/G3L RSPI support
> > >
> > > On Thu, Apr 02, 2026 at 01:00:28PM +0000, Biju Das wrote:
> 
> > > > Gentle ping.
> 
> > > There's strongly negative feedback from Krzysztof...
> 
> > I believe Krzysztof is complaining about patch [1] and his comments
> > were addressed in [2].
> 
> That's really not at all clear from the discussion.
> 
> Please include human readable descriptions of things like commits and issues being discussed in e-mail
> in your mails, this makes them much easier for humans to read especially when they have no internet
> access.
> I do frequently catch up on my mail on flights or while otherwise travelling so this is even more
> pressing for me than just being about making things a bit easier to read.

Agreed.

> 
> > > Please don't send content free pings and please allow a reasonable
> > > time for review.  People get busy, go on holiday, attend conferences
> > > and so on so unless there is some reason for urgency (like critical
> > > bug fixes) please allow at least a couple of weeks for review.  If there have been review comments
> then people may be waiting for those to be addressed.
> 
> > > Sending content free pings adds to the mail volume (if they are seen
> > > at
> > > all) which is often the problem and since they can't be reviewed
> > > directly if something has gone wrong you'll have to resend the
> > > patches anyway, so sending again is generally a better approach
> > > though there are some other maintainers who like them - if in doubt look at how patches for the
> subsystem are normally handled.
> 
> > There is no pending points, everything addressed in [2]. that is the
> > reason for sending gentle reminder.
> 
> There's more there than just "make sure you've addressed review comments".

The issues related to flexible DMA names for multiple DMAs are addressed by the
commit c2edd7841f58 ("spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property").

It looks like Krzysztof wants strict ordering in bindings for DMA names, if it is
a single DMA.

I will wait for his feedback.

Cheers,
Biju

Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Krzysztof Kozlowski]

On 02/04/2026 16:10, Biju Das wrote:
>>>>
>>>> So even after my objections here:
>>>> https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@kern
>>>> el.org/
>>>>
>>>> this was not fixed and Renesas did not provide actual cross-patch review.
>>>
>>> That patch is not correct. See below.
>>>
>>>>
>>>> This is still probably wrong as pointed out by other patches by Renesas.
>>>> Also, you cannot have flexible names.
>>>
>>> You can have "rx", "tx" in any order and {rx, tx} should be unique dma
>>> specifier
>>
>> No. You cannot. I just told you so. Please read writing-bindings for arguments.
> 
> <snippet from writing-bindings >
> - DO define properties in terms of constraints. How many entries? What are
>   possible values? What is the order? All these constraints represent the ABI
>   as well.
> </snippet>
> 
> Is that the reason you're saying we cannot have flexible names for DMAs?

Yes

> 
> Are you expecting the RZ/G3L DMA entries to be like below? Please let me know.
> 
> This is not flexible — the user always needs to specify RX first, followed by TX.
> 
> +  dmas:
> +    maxItems: 2
> +
> +  dma-names:
> +    items:
> +      - const: rx
> +      - const: tx


Yes

> 
> 


Best regards,
Krzysztof

RE: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the feedback.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 05 April 2026 09:58
> Subject: Re: [PATCH 1/2] dt-bindings: spi: renesas,rzv2h-rspi: Document RZ/G3L SoC
> 
> On 02/04/2026 16:10, Biju Das wrote:
> >>>>
> >>>> So even after my objections here:
> >>>> https://lore.kernel.org/all/9d08ddda-403e-458d-95e4-4e76915df85d@ke
> >>>> rn
> >>>> el.org/
> >>>>
> >>>> this was not fixed and Renesas did not provide actual cross-patch review.
> >>>
> >>> That patch is not correct. See below.
> >>>
> >>>>
> >>>> This is still probably wrong as pointed out by other patches by Renesas.
> >>>> Also, you cannot have flexible names.
> >>>
> >>> You can have "rx", "tx" in any order and {rx, tx} should be unique
> >>> dma specifier
> >>
> >> No. You cannot. I just told you so. Please read writing-bindings for arguments.
> >
> > <snippet from writing-bindings >
> > - DO define properties in terms of constraints. How many entries? What are
> >   possible values? What is the order? All these constraints represent the ABI
> >   as well.
> > </snippet>
> >
> > Is that the reason you're saying we cannot have flexible names for DMAs?
> 
> Yes
> 
> >
> > Are you expecting the RZ/G3L DMA entries to be like below? Please let me know.
> >
> > This is not flexible — the user always needs to specify RX first, followed by TX.
> >
> > +  dmas:
> > +    maxItems: 2
> > +
> > +  dma-names:
> > +    items:
> > +      - const: rx
> > +      - const: tx
> 
> 
> Yes

Ok, will send next version making it not flexible for single DMAC.

I accidently sent v2, so the next version will be v3.

Cheers,
Biju